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IEDM Blogs – Part 5 – Intel and Micron 3D NAND

IEDM Blogs – Part 5 – Intel and Micron 3D NAND
by Scotten Jones on 12-29-2015 at 7:00 am
Categories: Foundries, Intel Foundry, Samsung Foundry

At IEDM Intel and Micron presented “A Floating Gate Based 3D NAND Technology With CMOS Under Array” authored by Krishna Parat and Chuck Dennison.

As I previously discussed in my blog on the IEDM memory short course and blog on IMEC’s work on high mobility 3D NAND channels, continuing to scale 2D Flash has become extremely difficult and the major Flash producers are all moving to 3D NAND.

The memory short course blog can be accessed here.
The IMEC high mobility channel for 3D NAND can be accessed here.

Samsung was the first to introduce 3D NAND with their Terabit Cell Array Transistor (TCAT) and Toshiba has been in hot pursuit with their Bit Cost Scalable (BiCS) approach. Both of these approaches plus proposed 3D NAND from SK Hynix and Macronix have all been based on a charge trap devices where a silicon nitride layer is used to trap electrons.

The basic process for these devices can be thought of in three parts:

  • CMOS – the fabrication of CMOS to control access to the memory array.
  • Memory array – deposition of the memory layers, channel, slot and stair step formation.
  • Interconnect – interconnect of the CMOS and memory array.

To-date the 3D NAND devices in production have been charge trap based memory cells and the CMOS has been arranged off to the sides of the memory array.

In the Intel-Micron paper the first floating gate 3D NAND cell is described as well as the first instance of the CMOS being fabricated under the memory array.

The fabrication of CMOS under the memory array follows a flow similar to CMOS off to the side but adds interconnect that will also be under the memory array. We expect a pair of tungsten interconnect layers will be required.

The memory array fabrication begins with deposition of oxide and polysilicon layers pairs. The devices described in the paper has 32 memory layers plus select transistor layers and dummy layers. After the layers are deposited the array formation proceeds as follows:

[LIST=1]

  • Cell hole formation.
  • Etch back the gate polysilicon layers to create a recess.
  • Interpoly dielectric formation – I believe this is ONO.
  • Floating gate deposition – I believe this is polysilicon.
  • Floating gate etch back to isolate the floating gates, basically islands of polysilicon are created in the recesses formed in step 2.
  • Tunnel oxide and channel formation.

    Although not specifically addressed I would expect this to be followed by slit and stair step processes.

    I have heard a rumor that Intel-Micron creates their stair step with far fewer masks than Samsung. The challenge of stair step formation is a that a thick photoresist layer is deposited, one film pair is etched and then the photoresist image is “shrunk” and another film pair is etched. Because the photoresist film is getting thinner with each “shrink” there is a limit to how many layer pairs can be done by each mask. I have heard Intel-Micron gets more film pairs out of each mask, possibly by etching stairs that are narrower.

    Following the memory array formation, interconnect would be fabricated similar to the Samsung and Toshiba processes with the additional need to etch vias down to the CMOS under the memory array.

    The Intel-Micron process trades added process complexity to put the CMOS under the memory array against die area, so how do they do?

    Samsung initially entered the market with a 24 layer 2 bit/cell device; they then introduced 32 layer 2 bit per cell and 3 bit per cell devices, and recently announced a 48 layer 3 bit per cell device. So how does the Intel-Micron 32 layer 2 bit per cell and 3 bit per cell devices compare? The following table summarizes the five parts. Please note that a die size for the Samsung 48 layer devices is not yet available and the value presented is our estimate.

    [TABLE] align=”center” border=”1″
    |-
    | style=”width: 106px; text-align: center” | Company
    | style=”width: 69px; text-align: center” | 3D layers
    | style=”width: 66px; text-align: center” | Bits/cell
    | style=”width: 108px; text-align: center” | Capacity (Gb)
    | style=”width: 96px; text-align: center” | Die size (mm2)
    | style=”width: 114px; text-align: center” | Density (Gb/mm2)
    |-
    | style=”width: 106px; text-align: center” | Samsung
    | style=”width: 69px; text-align: center” | 24
    | style=”width: 66px; text-align: center” | 2
    | style=”width: 108px; text-align: center” | 128
    | style=”width: 96px; text-align: center” | 132.2
    | style=”width: 114px; text-align: center” | 0.97
    |-
    | style=”width: 106px; text-align: center” | Samsung
    | style=”width: 69px; text-align: center” | 32
    | style=”width: 66px; text-align: center” | 2
    | style=”width: 108px; text-align: center” | 88
    | style=”width: 96px; text-align: center” | 87.3
    | style=”width: 114px; text-align: center” | 0.98
    |-
    | style=”width: 106px; text-align: center” | Samsung
    | style=”width: 69px; text-align: center” | 32
    | style=”width: 66px; text-align: center” | 3
    | style=”width: 108px; text-align: center” | 128
    | style=”width: 96px; text-align: center” | 68.9
    | style=”width: 114px; text-align: center” | 1.86
    |-
    | style=”width: 106px; text-align: center” | Samsung
    | style=”width: 69px; text-align: center” | 48
    | style=”width: 66px; text-align: center” | 3
    | style=”width: 108px; text-align: center” | 256
    | style=”width: 96px; text-align: center” | 91.9 (est)
    | style=”width: 114px; text-align: center” | 2.49
    |-
    | style=”width: 106px; text-align: center” | Intel-Micron
    | style=”width: 69px; text-align: center” | 32
    | style=”width: 66px; text-align: center” | 2
    | style=”width: 108px; text-align: center” | 256
    | style=”width: 96px; text-align: center” | 168.5
    | style=”width: 114px; text-align: center” | 1.52
    |-
    | style=”width: 106px; text-align: center” | Intel-Micron
    | style=”width: 69px; text-align: center” | 32
    | style=”width: 66px; text-align: center” | 3
    | style=”width: 108px; text-align: center” | 384
    | style=”width: 96px; text-align: center” | 168.5
    | style=”width: 114px; text-align: center” | 2.28
    |-

    From the table it can be seen that the new 32 layer Intel-Micron device with the CMOS under the memory array is significantly denser than the Samsung 32 layer device. Of course as Intel-Micron are introducing their 32 layer device Samsung is introducing a 48 layer device and undoubtedly hard at work on putting the CMOS under the memory array on their devices as well.

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    IEDM Blogs – Part 4 – IMEC InGaAs Channel for 3D NAND

    IEDM Blogs – Part 4 – IMEC InGaAs Channel for 3D NAND
    by Scotten Jones on 12-28-2015 at 4:00 pm
    Categories: Foundries

    At IEDM IMEC presented “MOCVD In[SUB]1-x[/SUB]Ga[SUB]x[/SUB]As high mobility channel for 3-D NAND Memory” authored by E. Capogreco, J. G. Lisoni, A. Arreghini, A. Subirats, B. Kunert, W. Guo, T. Maurice, C.-L. Tan, R. Degraeve, K. De Meyer, G. Van den bosch, and J. Van Houdt.

    On December 15[SUP]th[/SUP] I had the opportunity to have a conference call with Arnaud Furnemont, director of memory department, at IMEC and discuss this work.

    With the well published difficulties with continuing to scale 2D NAND, all of the leading NAND Flash producers have introduced 3D NAND. Micron has even gone as far as to announce that 16nm will be their last 2D NAND generation.

    For 3D NAND a stack of alternating layers is deposited, either oxide-nitride or oxide-poly and then a channel opening is etched down through the stack. Currently 32 layer devices are in production with 48 layer devices being introduced. The long term plan for 3D NAND is to continue to add layers to the stack until over a hundred layers will be in use creating 1 terabit memories. There is also the need to create slits down through the stack and a stair-step at the array edge for interconnect.

    Some of the key integration challenges for 3D NAND are:

    • Stress in the memory stack.
    • Creating holes and slits through such a tall stack.
    • Resistance of the channel.

    The work in this paper is specifically targeted at channel resistance.

    In 2D NAND the memory cell channels are single crystal silicon with relatively good mobility.

    For 3D NAND, once the channel opening is etched down through the memory stack, a polysilicon tube referred to as a “macaroni channel” is formed in the etch opening. As the number of memory stack layers increases, the height of the macaroni channel increases. Because polysilicon has lower mobility that single crystal silicon, the channel resistance becomes a problem as the channel height increases.

    In this work a three memory layer stack was created using the Bit-Cost Scalable (BiCS) approach championed by Toshiba and San Disk (oxide-poly layers). 45nm channel openings were etched down through the layers and an InGaAs channel was then grown. The resulting channels showed a 10x improvement versus their process of record polysilicon channel.

    To-date the work is based on the BiCS process. I asked about the TCAT process Samsung utilizes particularly in light of Samsung being the first to market with 3D NAND. Arnaud said that TCAT will be next. Also, the work presented at IEDM just covered the channel mobility, since the original work was completed they have demonstrated program/erase of data and saw no change in the memory cells versus the POR.

    For a full implementation of this process there is still work to do:

    • They need to integrate a metal gate. When the memory cell is based on a nitride trap layers such as BiCS and TCAT use a metal gate is needed to create a high work function. The Micron floating gate 3D NAND I will address in a separate blog wouldn’t need a metal gate.
    • Currently the channel is solid and they need to create a macaroni channel.

    This work is an important step in addressing the challenges of continuing to scale 3D NAND.

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    Big Auto Fearing IoT!!

    Big Auto Fearing IoT!!
    by Al Gharakhanian on 12-28-2015 at 7:00 am
    Categories: Automotive, IoT

    In my advisory role I routinely interact with many customers and IoT thought leaders and invariably get acquainted with their point of views. I find most of these insights unique, informative, and most interestingly unmentioned in major news outlets. My intention for posting this is to share some of these findings with you.

    Yet Another IoT Wireless Proposal !!
    As if having eight IoT wireless proposals was not enough, we got a new one a couple of weeks ago. The technology is named Starfishand has been developed by Silver Spring. They announced the initial rollouts to take place in 7 cites in US, Europe, and India. Silver Spring is the leading manufacturer of “Smart Grid” connectivity equipment mostly sold to electric and gas utility companies worldwide. Starfish is a IPv6 mesh-based technology built on the Wi-SUN interoperability standard of IEEE 802.15.4g and allegedly can deliver 1.2 Mbps speeds, 10ms latency and up to 50 miles point-to-point range. While in-depth and meaningful information about Starfish is scant, the following are a few notable characteristics:

    [LIST=1]

  • Like SigFox and LoRa, Starfish is based on sub-GHz ISM band
  • Similar to SigFox, Silver Spring intends to be a service provider and not just an equipment company (yet another example of a traditional hardware company vying for a recurring subscription business model)
  • The initial rollout of this public network will be based on their legacy-installed base (nearly 25M nodes). It is unclear how a public network can be deployed using equipment owned by third parties
  • No cost or power consumption information is available and the existing implementation is based on a Systems-on-Chip (SoC) developed by Silver Spring bolted to an off -the-shelf radio chip

    So why is there so much interest to gain a foothold on an IoT Wireless technology? The rationale is pretty simple. Consider billions or even trillion of dollars that has been spent by wireless operators to build a worldwide cellular infrastructure. Such a massive investment has been well justified since eventually every world citizen able to use and afford a mobile phone will have one. Now imagine a world that each person that has one mobile handset is surrounded by dozens of “smart things” that need to communicate with each other. This presents an enormous business opportunity for the carriers both in terms of subscription fees as well as valuable data collected. Promoters of winning connectivity technology for IoT will enjoy a tremendous tail wind when it comes to monetizing the IoT build out.

    Nuances in Home Automation Gadgets
    Most people envision connected thermostats, smoke detectors, and smart lighting when they hear the term “Home Automation”. We have come a long way and Home Automation (HA) devices are covering a much wider territory. This category now encompasses home security, music distribution, IoT, and Remote Health Monitoring in addition to temperature and lighting control. The advent of flexible voice-driven HA hubs such as Amazon’s Echo has eased the task of controlling wares around the house using voice commands.

    Reviewing the nuances of the upcoming CES show in Las Vegas, the following conclusions can be drawn:

    [LIST=1]

  • The sheer number of connectivity protocols is mind bugling. We now have DECT, ULE, ZigBee, Z-Wave, Thread, Weave, AllSeen, OIC, Insteon, EnOcean, WiFi, and BLE Mesh. BLE (Bluetooth low energy) Mesh is the latest entrant to the HA arena. This is essentially enhanced Low Energy Bluetooth (BTLE) in order to extend its reach and up its data rate
  • There is now a new product category added to the HA mix. The category consists of detectors and sensors for home use that are able to perform Audio & Video Analytics. Such wireless sensors contain a camera and/or a microphone and can capture and analyze images and relay their findings to the control Hub. As an example, they are able to detect motion, recognize faces, and detect fire and smoke. On the audio side, the devices are able to analyze the captured sounds and identify a cry for help or slurred speech of elderly suggesting a stroke
  • There is a trend to build devices that have multiple functionalities. One notable example is a new product from MYXYTY that is essentially a floor-standing 360-degree Bluetooth speaker but it also integrates LED lighting, camera, microphone, pico-projector, and even a perfume diffuser.
  • On the service side, there are an increasing number of companies such as iControl, and Zonoff that are capitalizing on the complexities involved in product selection, installation, and the management of all these new gadget. Their value proposition is to handle A-Z of the home automation issues of homes and offices

    Big Auto Fearing IoT !!
    Alphabet and Apple are aggressively pressing carmakers to install variations of their operating systems in the car entertainment systems (head units) for many good reasons. This obviously has many benefits for the consumer in the form of added connectivity, device integration, and a slew of innovative services. The parties that gain the most from this trend are the ones that own the operating system. Alphabets and Apples of the world are essentially able to extend their footprint into millions of vehicles. They are able to collect tons of valuable user data and a can now establish a new eCommerce front not to mention pushing targeted advertisement to the drivers and passengers.

    Major automakers view this as a loss of valuable territory. They don’t want to end up like Samsung that pays a heavy price in profit margins just because they don’t have control over the mobile OS. German behemoths are particularly worried about this loss of control since they employ one out of seven worker in Germany and they have not been particularly successful in developing a homegrown operating system.

    Happy Holidays & Peace on Earth
    Al Gharakhanian

    We at Upsideclosely track the developments in the emerging field of Internet of Things (IoT). Our mission is to discern facts from fiction. We are committed in helping our clients make the optimal product planning and strategic decisions

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    2015 3D ASIP conference: Thar’s Gold in Them Thar Hills!

    2015 3D ASIP conference: Thar’s Gold in Them Thar Hills!
    by Bill Martin on 12-27-2015 at 4:00 pm
    Categories: EDA

    Last week I presented at the 3D ASIP EDA Tutorial and attended the Conference. In previous years, leading edge papers were presented from large companies pushing a solution to meet their needs. These companies had the resources and clout to achieve some astounding successes, but the lingering question was: “what other product development companies could achieve this unless the ecosystem would enable with lower risk as well as costs?”

    This year’s conference was different. Rather than just large product development companies pushing their latest accomplishments, 4 aspects hit me:

    [LIST=1]

  • Slight language changes used at conference.

    Last year, it was one solution ‘fits all’ (ie Through Silicon Vias “TSVs”) even though several presentations clearly showed that TSVs are costly and may not be suitable for all applications. This year, it was clear that most memory applications were TSV based but others were “TSVless”. Rather than one size fits all, all presenters stated that viable, cheaper alternatives are developed or being developed (application specific packaging).

    Take away: Ecosystem is maturing and companies recognize that one size might be too expensive/complex for many to use. Better to offer different solutions for different end markets.

    [LIST=1]

  • In previous years, only Foundries presented denser system solutions using silicon interposers.

    When a single solution exists, I often question if the end market exists or if it is large enough to support a growing ecosystem. When other competitive solutions enter the market, these new entries validate the market and product space. Similar to the mid 1980’s to mid 1990’ (ASIC ‘hey day’), after VLSI Technology and LSI Logic showed the Cost of Ownership (COO) and improved performance/area from using ASIC designs, any company that produced silicon quickly started offering ASIC solutions using standard cell and/or gate array solutions. At this year’s 3D ASIP conference, BOTH Foundries and OSATs presented solutions that addressed high density packaging. TSMC’s FOWLP as well as Amkor’s SLIM/SLIT offer different capabilities and business models addressing denser, complex packaging.

    Take away: The large ecosystem suppliers are recognizing that complex packaging is a ‘must’ and that to participate in this market, they must establish a presence. This is good news for product developers where competition will produce better and cheaper products for all. The downside, product developers will need to increase their planning analysis before committing expensive resources.

    [LIST=1]

  • DARPA’s DAHI program is not focused solely with commercially available CMOS process nodes (130nm down to 10nm).

    DAHI is mixing various III-V substrate materials into complex 2.5D systems. The IP integrated in their system design are fabricated in the III-V process nodes that did not compromise the IPs’ performances or functionalities. DAHI is choosing the best of each and then integrating into a heterogeneous 2.5D structure.

    Take away: for the leading/bleeding edge; homogeneous CMOS integration was ineffective and ‘boring’.

    [LIST=1]

  • Although not huge, this year’s (pre) registered attendance was equivalent to last year’s registered plus last minute walk in registrations. I do not have the totals but I assume attendance grew.Several attendees mentioned during their introductions that this was their first time attending and they were there to understand available capabilities.

    Take away: Many companies are starting their discovery process and many will use homogeneous 2.5D products/services in the 2016-17 time frames. By 2018, many will start using heterogeneous 2.5D capabilities demonstrated by DARPA’s DAHI program.

    The end consumers will be the benefit from all of these packaging advancements with more powerful, less power hungry, lighter and cheaper products. The future looks bright, LED bright.

    Notes:    https://en.wikipedia.org/wiki/M._F._Stephenson

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    Networking through Dark Silicon Power Islands

    Networking through Dark Silicon Power Islands
    by Don Dingee on 12-27-2015 at 7:00 am
    Categories: IP, Sonics

    For decades, tracing back to the days of Deming, the way to tackle complex engineering problems has been the pareto chart. Charting conditions and their contribution to the problem leads to mitigation priorities.

    In the case of SoC power management, the old school pareto chart said the processor core was the biggest power hog and needed to be managed first. The industry developed lower power cores, dynamic voltage and frequency scaling (DVFS), power and clock gating, big.LITTLE clusters, and lower leakage transistors and processes. Power got lower.

    But, did it get better? In the world of dark silicon, where there are bazillions of transistors and uncertainty over exactly who is doing exactly what to whom at any given time, it can be very hard to say. (Batterygate, the story of the difference between Apple A9 as fabbed at Samsung and TSMC, is a great example.) Techniques to manage power become increasingly difficult. More importantly, if we look at a typical SoC, the processor core may have several challengers on the new school power consumption pareto chart.

    When the CPU cluster no longer dominates power usage, CPU-centric approaches to power management run into limits quickly.

    Managing IP hardware blocks as power/clock domains illustrates the problem. Setting up boundaries at bus interfaces and creating power islands is tempting, but inefficient using only a conventional interconnect. If an IP block were independent, fine grain and automatic coarse grain clock gating would be enough to slow or shut down an idle block.

    In complex designs, IP blocks are highly interdependent, especially if a network-on-chip is used. Fabric must remain powered if any attached block is still powered, meaning the fabric is “always-on” or needs partitioning with many wires at the domain crossing. If there are many transactions between blocks, idling a target may actually be counterproductive, causing system-level congestion and power thrashing as blocks are constantly turned on and off.

    A better approach is to group the IP into affinity domains that are on or off together, and partition the domains across a minimally wired hardware interface with a software power management protocol. The catch is there is no industry standard scheme for this. ARM has defined several channels in AMBA, including C-, P-, and Q-channel, with each serving incompatible needs and not compatible with other stuff. Using these hardware channels does little for the software side. If a design team controlled all the IP blocks and could integrate these channels into each block accordingly, it might be possible to use them, but it would take a sizable design team working on just power issues – something most SoC design efforts cannot afford.

    Using a NoC is something most SoC design efforts can afford, and the SonicsGN architecture strongly comprehends power management. Redrawing the partitioning into power islands including the network components captures three huge benefits.

    First, the wires in the hardware interface are greatly reduced – in the SonicsGN case, to a 4-wire power management interface. There is a power down request and acknowledge, and an auto wake request and enable, setting up a wake-on-demand function (similar to Ethernet wake-on-packet capability).

    Second, the NoC knows what its traffic looks like and can manage it safely. Software can look at in-flight transactions across the network and make sure they reach their target before it is idled, rather than abruptly shutting down a block unexpectedly. This amounts to a power flush operation, where initiators vote and paths to a target are cleared prior to idling. Initiators can then handle a request to turn a target block back on. If the network is fast enough, the target block can come back on before the driver receives an error – virtually appearing on.

    Third, all this management capability happens in the NoC and software without extensive modifications to hardware IP blocks to implement the protocols. Designers can choose their power management style, using gating techniques in combination with the channel-based approaches and the SonicsGN capability.

    Using the Sonics power islands approach, designers have fewer limits and more capability in power management, without massive investments tied up in creating proprietary schemes. Sonics teams remain abreast of power management developments, and continue advancing their SonicsGN architecture to enable the latest ideas. By staying in the NoC and out of each IP block (some of which may be very, very dark in power management terms), IP block obsolescence or reengineering is avoided should power management tactics change.

    Related Blog

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    Self-driving Connected Taxis Insights from Patents

    Self-driving Connected Taxis Insights from Patents
    by Alex G. Lee on 12-26-2015 at 4:00 pm
    Categories: Automotive, IoT
    13 Comments

    Japanese company Robot Taxi Inc. announced that it will start trials with self-driving taxi service beginning in 2016. US20150339928 illustrates the system for operating the autonomous vehicles taxi service. A user can request a taxi service using an application that is running on the user’s mobile device. The taxi service request can include the number of passengers to ride in the autonomous vehicle and a requested vehicle type etc. The taxi service control system receives the taxi service request from the user’s mobile device. The taxi service control system selects an autonomous vehicle from the operating autonomous vehicles to perform the taxi service for the user.

    The taxi service provides the picking up the user at a pickup location at a selected pickup time and dropping off the user at a drop-off location. The pickup location can be a current location associated with the mobile device or a specific location defined in the taxi service request. The taxi service control system selects an autonomous vehicle that is currently available to perform the taxi service from the list of autonomous vehicles based on the autonomous vehicle’s current proximity or distance to the pickup location. The selected pickup time for the taxi service can be an upcoming time. The taxi service control system identifies an autonomous vehicle that is available at the selected pickup time from the list of autonomous vehicles.

    After the autonomous vehicle is selected, the taxi service control system schedules the autonomous vehicle to perform the taxi service for the user at the selected pickup time. The taxi service control system sends a confirmation to the user that requested the taxi service, via the application on the user’s mobile device. The taxi service control system notifies the user when the autonomous vehicle is near the pickup location.

    When the autonomous vehicle arrives at the pickup location, the user can be granted access to the autonomous vehicle upon providing a form of authentication. The autonomous vehicle selects the best route to drive the user from the pickup location to the drop-off location. The route can be optimized to reduce a distance traveled or an amount of time to perform the taxi service. The user can request for the route to be altered when the autonomous vehicle is traveling to the drop-off location. The taxi service control system calculates the cost associated with the taxi service. The taxi service control system, using bank account information associated with the user, charges the user for the taxi service.

    US2015015849 illustrates the central monitoring system to control the autonomous taxi vehicles. The monitoring system receives inputs from the vehicle traveling on a road in real-time. The inputs include information regarding the environment surrounding the vehicle and other surrounding vehicles. Based on to the inputs, the central monitoring system determines if the monitored vehicle is approaching a hazardous condition. When it is determined that the monitored vehicle is approaching a potentially hazardous condition, the central monitoring system actuates the vehicle controls system (such as a brake system or steering system or collision avoidance system of the vehicle) to avoid or minimize the risk of the hazardous situation. The vehicles communicate with the central monitoring systems and other vehicles via the vehicle communication system.

    More articles from Alex…

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    Micron Misses (MU) – No surprise – Needs focus on NAND/XPoint not diving DRAM

    Micron Misses (MU) – No surprise – Needs focus on NAND/XPoint not diving DRAM
    by Robert Maire on 12-26-2015 at 12:00 pm
    Categories: Foundries

    We are surprised that everyone is surprised at DRAM, DRAM oversupply/weak demand is systemic so Micron needs to focus on NAND/XPoint.We find it somewhat amusing that many “analysts” were caught off guard about the weakness in Microns results and poor guidance. Why would you think DRAM would be OK???…Have you paid attention to prices?

    Micron had a more or less in line quarter but guided sharply lower for fiscal Q2 ending February, sending the stock down 5%- based on DRAM issues

    Anybody who has been watching Semis for more than a few years should know that calendar Q1 is always the weakest quarter for memory pricing. We are in the postpartum depression after the big ramp for the holidays coupled with several weeks lost business due to Chinese New Years. DRAM has historically under performed in calendar Q1 and this season has been weak to start off with, so why would analysts or investors think that some miracle would happen? Look at past pricing…history repeats itself…and seasonality is stronger than ever given the clockwork-like release of Apple’s iPhone every fall.

    Demand/pricing is still weak…
    DRAM is and has always been the ultimate commodity in the semiconductor space. While true that there are many variants of DRAM these days the reality is that it acts like a commodity because it is one.
    It is a simple, standard stupid balance of supply and demand that governs pricing and right now demand is not all that great while supply is. How you could conclude that this would lead to good results for a DRAM maker is beyond me.

    PCs and Windows 10 didn’t help and smartphones/tablets aren’t either…
    In the bad old days every new version of Windows significantly increased the amount of DRAM needed as the “bloatware” increased. This is certainly not the case with Windows 10. Nor did we see an uptick in sales for PCs that could have driven DRAM so the only other significant place would come from mobile devices increasing DRAM needs and it doesn’t appear to be the case either. So where is the demand to suck up the extra capacity that has come on line over the last year or so???

    Will Saudi Arabia increase oil production to combat low prices???
    We don’t think so….So the odds of Micron dumping more CAPEX into DRAM capacity is also foolish. Maybe I would put money into reducing production costs to try to prop up margins but increasing capacity is throwing fuel on the fire sale. Sure, moving to the next technology node will help costs but without a significant change in demand its going to be tough sledding going forward.

    NAND and XPoint are where its at…
    NAND seems to be the ultimate price elastic commodity, the cheaper it gets, the more we buy. For SSDs, smartphones, tablets etc; I keep buying bigger thumb drives and SD cards. In the NAND market at least Micron has a chance to see more progress and if it can ramp the 3D NAND product, should have a market to sell into to, which while constantly falling does have increasing demand to limit the downward trajectory.

    XPoint is the real differentiated product…
    If we were Micron management, we would be focusing our attention and spending on XPoint which holds the promise of differentiation and enhanced technology versus the commodity DRAM and NAND markets.XPoint is a potential winner and needs to be ramped ASAP. It could command better pricing and margins with less or no competition. It is a long term solution to being stuck in the cyclical roller coaster of commodity product price swings.

    Waiting on NAND and XPoint but with a floor in the stock
    We would be hard pressed to put money to work in shares of Micron near term. We likely will have some time before we see positive results from NAND or XPoint, as the company indicated the second half. We do think there is a floor under the shares as if they get too cheap they get a bulls eye painted on their back and become an M&A target. Perhaps if the shares went down too much Intel could notice after Altera is done. We don’t expect China to come back in any time soon….


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    Connections to Internet Drives Semiconductors

    Connections to Internet Drives Semiconductors
    by Pawan Fangaria on 12-26-2015 at 7:00 am
    Categories: EDA, Foundries, IoT

    We are going to see a big reversal in what connects to the internet in next five years. At the start of this century there were about 488 million internet connections; 85% of those were connected to people for web browsing, e-mails, on-line services etc. and only 15% were used for embedded systems, remote sensing and control, and M2M communication.

    Can you imagine what would be the composition of internet connections in 2020? It will be a complete reversal of what we have seen in 2000; 85% of total connections will be through web-enabled devices in various segments including automotive, home, consumer, industrial etc. and only 15% will be to human individuals. And that would sum up to a total of 30 billion internet connections.

    The new connections to IoT (Internet of Things) are increasing in double digits almost every year.


    I like Texas Instruments CEO, Rich Templeton’s vision around this and forming his company’s strategy according to this. A few years ago, he revealed about his company’s strategy in a briefing in one of the investors forums. This was articulated as – the world is changing from number of persons per device to number of devices per person, so it makes sense to catch those devices’ market.

    According to IC Insight’s report, the systems revenue for applications connecting to the IoT will nearly double, reaching about $124 billion by the end of 2019. And the pure IoT applications market will see a CAGR of 19.2% reaching more than 31 billion by the end of 2019.


    The IC sales in IoT market will grow at a CAGR of 15.9% whereas the OSD (Optoelectronics, Sensors and Discrete) semiconductors are expected to grow at a higher CAGR of 26%, compounding the overall semiconductor growth rate in IoT applications to a CAGR of 19.2%. Among the IC sales, the top drivers will be microcontrollers and SoC microprocessors followed by memories. It’s understandable from an IoT standpoint.

    There is no doubt internet infused a significant growth trajectory for semiconductors. Over last few decades we have seen a phenomenal growth in semiconductor business due to cellphones and then smartphones which connect to internet primarily for human users.


    Smartphone remains the largest driver for semiconductor IC market; however the smartphone market is now maturing and is expected to stay more or less stagnant. Then what will fuel further growth in semiconductors?

    It’s the number of connections to internet through devices other than smartphones. We are already seeing wearable segment of IoT having large growth at a CAGR of ~59% to reach $15.2 billion by the end of 2019. Apple watch has to be given thumbs up on this. Connected automotive is expected to show a CAGR of 31.5%. Then there are other segments of IoT such as medical, home, industrial, business, and others that will connect to internet and surprise us.

    The semiconductor industry is at an edge of another transformation. We have seen large scale M&A activities this year which is expected to continue next year. And we will see a different direction in transformation now. Stay tuned for my article on future semiconductor landscape.

    The IC Insights reports referred in this article can be found hereand here.

    Pawan Kumar Fangaria
    Founder & President at www.fangarias.com

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    DSP gives Project Tango a power dip

    DSP gives Project Tango a power dip
    by Don Dingee on 12-24-2015 at 12:00 pm
    Categories: Automotive, Ceva, IP

    Google’s Project Tango is a prime example of a sophisticated application pushing the boundaries of what is possible within the power envelope of a mobile device. Its objective is to combine 3D motion tracking with depth sensing to understand how a device is moving and gauge its surroundings precisely. Continue reading “DSP gives Project Tango a power dip”

    Posted on

    The "Great Acceleration"

    The "Great Acceleration"
    by Arthur Hanson on 12-24-2015 at 7:00 am
    Categories: General

    The “Great Acceleration” is upon us. On all fronts technology in everything is advancing at an ever accelerating rate due to improvements in education/training, increased power and functionality of hardware, software, access to information(Google, technical publications, etc.) prototyping techniques (3D Printing, sophisticated design and test software for literally everything from software, to semis, to physical objects and devices), more people working on literally everything from every angle with the net providing collaboration and off loading of just about any task. All this coupled with an ever increasing ways of raising capital and assembling talent and you get to where we are now, Rapid acceleration of any task we can even imagine, including the very problems acceleration creates.

    All this is leading to the ability to have everything in abundance if we so choose. The problem is that most individuals, social structures and government can’t keep up and this fundamental change to abundance, leading to increased instability and dislocation. The semi and software sectors are leading the way and are advancing so much faster than everything else we have dislocations that while creating great things also create great instability and damage. Organizations, companies, investors and individuals that master this will do well, while many will suffer from the dislocations and instability.

    To take full advantage of the opportunities before us will not only require changes in us, but all the organizations we deal with. A Gallup poll done in September found 75% of all adults consider corruption pervasive throughout our government and justly so. Sadly much of this is just a failure of not wanting to adapt to the accelerating changes. It is not just government that has problems, but our very social structure for government is just a reflection of the society on which is still based on the slower moving progress of the past.

    Since the semi sector is among the leaders in accelerating change, we can no longer work in a vacuum indifferent to the world around us. With knowledge and power go responsibility and to forget this will have dire consequences for everyone. When we at the forefront of change if we forget the consequences and applications of what we do, we can literally sink the ship. It is at this point we must remember “When the ship sinks, first class goes down too”.

    Technology can bring one quality that will help everyone, transparency, which is the key to honesty and integrity. Transparency also has the awesome power to solve problems by making them apparent. It is critical that transparency is maintained so we can solve problems before they become dangerous. Already it is easy to see where new forms of finance have put many people and governments in dangerous straights. Many things can now become obsolete well before the financing to pay for them is completed. There is nothing we can’t solve and the semi sector can/will play a key part in the solutions, many are already well under development. Bellow is a brief partial list of examples of solutions under way.

    Energy: solar in many forms, wind, underwater turbines, nuclear, stripping hydrogen from hydrocarbons, nuclear, advanced fracking for not only oil/gas but geothermal

    Food: advanced forms of algae and microbial that already produce 40 times what current agriculture land produces with the potential of 700 times. We might not eat this, but most food is grown for animal feed. This would solve food, land and water problems.

    Water: advanced desalinization, recycling of waste water to drinking quality

    Transportation: ultra efficient cars, ships, planes and trains

    Medical:vastly lowered costs and increased productive life span currently being literally attacked from almost every vector

    Robotics/AI: will open up the oceans with vast resources of all types, improve and lower education costs, free us up for far more productive and pleasurable pursuits and greatly leverage our labor (creating more dislocation and challenges)

    Efficiency: new glass, numerous new engines, hybrid systems, new insulating materials, new reflective surfacing coatings, etc. etc., but most of all in all processes from creation to production to distribution to use and disposal.

    Transparency and flexibility will be key if we are going to deal with these changes without massive social conflict and with semiconductors being at the heart of much of this, this is the place to start and should be taken into account from the inception of any new technology which is just another form of power and should be treated and respected as such for technology without wisdom can be very dangerous. The semi/mems sector is the leader in acceleration, so it is up to us to ask these critical questions and develop solutions.