llmda newsletter ad (2)
Semiconductor Expert Forum

Posted on

Intellectual Ventures Patents for Internet of Things (IoT)

Intellectual Ventures Patents for Internet of Things (IoT)
by Alex G. Lee on 12-07-2015 at 4:00 pm
Categories: IoT

More than 15,000 Intellectual Ventures’ US issued patents and published patent applications are reviewed for finding the good candidates for the IoT strategically packaged patent portfolio. Even if the Internet of Things (IoT) gets a huge attention recently, the concept of interconnected devices and connecting billions of devices to the internet in the IoT is not new and has been researched for over 10 years. Thus, there may be a large number of patents (that were not intended for specific IoT application at the time of invention) that can be exploited for developing new IoT business by forming the strategically packaged patent portfolio for providing the new IoT value propositions.

The strategically packaged patent portfolio is the collection of the existing patents that can be exploited for developing new products/services (and thus, new business) by integrating the value propositions of each patent of the portfolio. The strategically packaged patent portfolio can be exploited for monetization through patent sale, patent licensing, commercialization, spin-off, patent banking, and financing.

To speed up the review process, carefully designed search keywords for the specific IoT applications are used with the search tool PatSnap. Through the IoT application motivated analysis, more than 100 the IoT related patents, which can be exploited for the IoT strategically packaged patent portfolio, are found. Intellectual Ventures’ IoT related patents cover IoT Security, IoT Platform Connectivity, Connected Cars, Wireless Sensor Network, Smart Grid, Connected Health, IoT Intelligence (e.g., machine learning, predictive analytics) and Smart Home.

Followings summarize some examples of the key Intellectual Ventures’ IoT related patents.

US8195106 illustrates the system for controlling vehicle remotely via devices in proximity. The devices in proximity include an information system, an audio and/or video system, a heating and/or air conditioning system, a lighting control system, a navigation system, a lock system, an ignition system, a driver settings system, a security system, a camera and a communication system. The devices in proximity transmit a signal to the user device (e.g., smartphone) to cause the user device to display information related to vehicle operations when the user is in an area that is near to the devices in proximity. The user, then, uses the user device to control the devices in proximity using the variety of different techniques such as locking a door or adjusting the heat via heating A/C system.

The measurement of physiological data can be utilized to detect abnormal situations in individuals. In some instances, physiological monitoring methods relate to the heart rate, electroencephalography (EEG), electrocardiography (ECG), body temperature, or oxygen density in blood. However, such physiological monitoring methods are not convenient for long-term measurements. For example, ECG measurements need electrodes to be pasted on the skin, which may reduce the suitability of ECG for long-term uses. US8172777 illustrates the sensor-based health monitoring system that is suitable for long-term uses. The health monitoring system includes a sensor unit that can detect body motion of a user. The health monitoring system analyzes body motion data received from the sensor unit to detect abnormalities of the user. Then, the health monitoring system communicates with the remote site such as a home or a hospital.

US6847995 illustrates the security architecture for providing secure transmissions within distributed processing systems. A server system is coupled to a network that is coupled to the distributed devices. The server system utilizes a security measure that is partitioned and distributed to multiple distributed devices. The distributed device receiving electronic information reconstructs the security measure by obtaining the various partitioned portions from the multiple distributed devices. The security measure can be the generation of a hash value for the electronic information to be transmitted.


More articles from Alex…

Posted on

Evolution of Non Volatile Memory for Sensitive Data

Evolution of Non Volatile Memory for Sensitive Data
by Tom Simon on 12-07-2015 at 12:00 pm
Categories: IP, Sidense

When first interested in computers while I was in junior high school in the early 70’s I remember seeing a core memory board for the first time. It was a seriously large circuit board with a myriad of wires woven across it going through the tiny metal doughnuts that stored the bit values. The computers it went into only had a total of around 4K bytes of memory. The only other storage option was paper or magnetic tape, or for some extravagantly well-heeled institutions there was drum memory. I remember buying my first PC and being thrilled that it had 64K of RAM some years later.

Of course back then plain old switches were used to ‘store’ values for interrupt numbers, device addresses, or configuration data. Remember when disk controllers needed to have the dip switches set according to some cryptic data sheet so they had the correct number of heads, sectors and cylinders?

While the technology has changed incredibly since those days, the underlying need for various data storage types and sizes continues and is expanding. On one end of the spectrum there is mass storage in the form of hard disks or increasingly as solid state drives (SSD). Like core memory gave over to semiconductor based storage, we see DIP switches and even hard drives moving to the chip level. Removing mechanical components saves money and improves reliability. It also has a side effect of improving security in many instances. DIP switches could get accidentally, or even maliciously, changed. However, the need for storing small amounts of essential data has, if anything, expanded over the years.

Decades ago it was conceivable that you might add a device package to your system board just to store a couple of registers worth of data. Today it would be a crime. Even making room for traces that can be cut is out of the question with today’s board density. Really the only solution is to bring this data storage on-board into an SOC. To determine the best medium for any given storage need, we have to step back and look at the data storage requirements for the information we intent to save/use. Today designers can choose from e-fuse, NAND Flash, EEPROM, anti-fuse, mask ROM, or potentially, other types of storage.

At the bottom of the list if we go by capacity there is storage for things like MAC addresses, trim info, encryption keys, and of course configuration data that is fairly static. For this we probably do not want to add mask layers or change the fab process at all. This rules out quite a few of the above choices. If security is a concern too then we are most likely left with anti-fuse OTP, such as what is available from Sidense. They offer one time programmable (OTP) non-volatile memory (NVM) that can be added to just about any chip on any fab, even FinFET, AMS, or legacy CMOS. Their OTP NVM IP is drawn using a standard layer stack up with no special layers or extra processing.

Of course, mask ROM also uses a standard stack up, but the data has to be part of the mask set, which rules out using it for unique device trim, hardware addresses and security keys. OTP-NVM can be programmed on the tester or in the field. It also offers simulated re-write, so values can be updated in the field if necessary. Sidense can include an IP module for programming the NVM even if the supply voltages are only for logic. A higher voltage is used for programming, but it can be produced internally using a charge pump.

Next up the food chain is storage for things like boot code or microcode. These are usually unchanging as well, but could possibly be updated over the course of the life of the product. With this category of data, security becomes an even bigger issue. Having it on the SOC helps a lot, because observable circuit board bus traffic is not taking place. However, there are a number of reverse engineering techniques that rely on physical inspection or current monitoring during reads. Here is another place that Sidense OTP NVM excels. There is no physical marker when anti-fuse is programmed. During programming the 1T cell is modified in the gate oxide by overvoltage, but it leaves no detectable artifacts. Sidense also uses a symmetrical storage configuration so the read current does not change based on the bit value retrieved.

Sidense OTP can even simulate re-write up to the limit of bytes available by dynamically changing addressing. So, critical updates can be applied in the field if needed. This is known as few times programmable (FTP).

Using patented technology delivered as an IP product for one time programmable non volatile memory has a number of advantages. It comes with the physical implementation for the bit cell array and also with proven soft IP for the the support circuitry that embodies all the security. The entire package is rigorously tested using test chips for each target process for yield and reliability.

Things have come a long way from DIP switches and magnetic tape for parameter and boot code storage, but the demands for these vital pieces of data have grown and are central to our lives in many instances. We count on reliability and security in mobile communications, automotive systems, medical devices, and finance, among other things. It’s good that companies like Sidense are providing an essential link in the chain. For more information, I suggest going to the Sidense website.

Posted on

CEVA Royalty Revenues in 2015 Supports Future IoT Design Win

CEVA Royalty Revenues in 2015 Supports Future IoT Design Win
by Eric Esteve on 12-07-2015 at 7:00 am
Categories: Ceva, IP

DSP IP addressing modem for the mobile phone market is still the flagship product and CEVA enjoys design-win at major semiconductor account (one of them being vertical and also selling the smartphone), but the acquisition of Riviera Waves in 2014 has been a strong sign of diversification. CEVA’ port-folio includes signal processing and IP supporting wireless interconnects standards like WiFi and Bluetooth or BLE. If you define a generic architecture supporting IoT, you need processing, short range wireless and sensors.

Historically, CEVA has developed a family of DSP IP cores to support modem for mobile phone application. In the early 2000’s, the top cell phone OEM, Nokia, Ericsson or Motorola were using TI baseband solution, including TI DSP core. But TI DSP was not licensable as an IP which could be used with another ASIC supplier. OEM had to buy the complete solution, branded OMAP later on, to benefit from TI DSP. TI strategy appeared to be great opportunity for CEVA and the company has started to penetrate the mobile phone market with TEAK and TEAK-Lite DSP IP cores.

If we explicit CEVA business model, we better understand the company dynamic. Because CEVA DSP is unique, like can be a processor core (but not a protocol related function like USB or PCI Express controller) the company can define a business model based on up-front license fee plus royalty, usually a small percentage of the chip ASP. Such a model provides several benefits when compared with up-front license fee only. Royalties linked revenues may come several years after the IP design-win. On a long period, the company revenue flow can be smoothed, the royalties being paid by quarter all along the chip production life time. Investors tend to prefer IP vendors who can define a business model based on royalties + up-front license fee to IP vendors using up-front license fee only…

If we consider CEVA, the design-win made during the 2000 decade have generated a revenue flow strong enough to heavily invest into R&D. The company has developed a family of various DSP core, each of them tailored for a specific market segment: CEVA-XC core for baseband, CEVA TeakLite-4 to address Audio/Voice/Sensing and CEVA XM4 and MM-3101 to support Imaging and Vision applications.

CEVA has enjoyed modem design-win at major semiconductor account (including vertical OEM building chips and selling smartphone), even if the company doesn’t disclose royalty revenue by market segment, our guess is that mobile communication generates the higher share. But CEVA is rapidly diversifying; the acquisition of Riviera Waves in 2014 has been a strong sign of this diversification. CEVA’ port-folio includes the various DSP IP families above listed and specific wireless IP supporting interconnects standards like WiFi and Bluetooth, including BLE.

If you define a generic IoT architecture, you need processing, short range wireless and sensors. CEVA has no sensor IP, but the signal directly coming from the sensor, once digitalized, is sent to a DSP. Moreover, if you want to use a low cost sensor, you will need strong and efficient signal processing (coming from CEVA DSP core) to clean and process the sensor output: the better the DSP, the better the result. Once the data has been processed, the system sends the information to an upper level (network, smartphone, base station, etc…) by the means of short range wireless communication like WiFi or Bluetooth Low Energy (BLE), both IPs available on CEVA port-folio.

To develop effective solutions for emerging application and support customers far before generating revenue require R&D resource and funding. Here we come back to the royalty based business model. Just take a look at CEVA revenue for the third quarter of 2015 of $16.2 million. Licensing and related revenue for the third quarter of 2015 was $8.6 million and royalty revenue was $7.6 million, an increase of 42% compared to $5.4 million reported for the third quarter of 2014. We can guess that a significant part of this royalty revenue can be assigned to new project development.

We find an interesting indication in the third quarter of 2015 earnings announcement. CEVA concluded eight new license agreements: three of the agreements were for CEVA DSP cores, platforms and software, and five were for CEVA connectivity IPs. Riviera Waves acquisition is about one year old but more than 50% of the new licenses are coming from connectivity IP. In fact CEVA is not only preparing the future through R&D, the company is already addressing emerging applications built around varieties of connected devices.

Is CEVA healthy IP vendor? In 3Q 2015 CEVA has registered all time high revenue of $16.2 million up 15% year-over-year and royalty revenue of $7.6 million, up 42% year-over-year. We think the real question should be: will CEVA be healthy in 2020?

Thanks to royalty-based business model, CEVA has the opportunity to invest into acquisition (Riviera Waves) and R&D efforts to address emerging applications. This strategy is already successful as CEVA is enjoying this quarter more new licenses with connectivity IP than with DSP IP cores, although Riviera Waves acquisition is about one year old (September 4[SUP]th[/SUP], 2014). If the ultimate question is about CEVA success in 2020, yes we think that the IP vendor should be successful at that date, with a revenue mix made of royalties linked with DSP IP supporting LTE and with license fees generated by interconnect and DSP IP for emerging connected applications.

Eric Esteve from IPNEST

More articles from Eric…

Posted on

Optimizing power for wearables

Optimizing power for wearables
by Bernard Murphy on 12-06-2015 at 4:00 pm
Categories: Cadence, EDA

I was at the Cadence front-end summit this week; good conference with lots of interesting information. I’ll start with a panel on optimizing power for wearables. Panelists were Anthony Hill from TI, Fred Jen from Qualcomm, Leah Clark from Broadcom and Jay Roy from Cadence. Panels are generally most entertaining when the panelists disagree. This group didn’t disagree on much, but that in itself was revealing. The main messages I heard were:

· A lot of this stuff is being built on older processes, in part for cost reasons I assume
· Analog is a much bigger part of IoT devices than digital
· EDA support for power in AMS design is weak to non-existent

There was a lot of discussion on “Big A, little D” and all the compute being pushed to the fog or the cloud, which doesn’t sound quite right to me. If these are intended to sit in any fashion on the Internet, you have to have at least some local compute, you have to have communication and you have to have (these days) security. That doesn’t add up to little D. Also anything required to provide real-time control has to have more than a little local compute power.

But none of that takes away from the reality that the A part on these devices is significant. And very little we do today in the power flow is any help with that. UPF/CPF still has no real understanding of analog. Verification is also a problem. A significant percentage of reworks are caused by bad connections across the AMS interface (for example use of incorrect level shifters). Along similar lines, clever power switching or voltage scaling requires regulators and these burn power too. So you can’t get to realistic power numbers for ultra-low power applications like wearables without considering the total system. So for me big takeaways are that tools and standards need to ramp up AMS-aware modeling and verification in the system (in fairness, UPF 3.0 should help with system-level modeling).

There was also a discussion on power sources. What you’re really trying to optimize for wearables is time between charges (or alternatively to minimize the inconvenience of charging) rather than that the power consumed. Yes, they’re related, but power in these devices is intrinsically low, so thermal is not a problem. However you do have to worry about consumers losing interest because of the charging hassle. Several participants talked about wireless charging from which I infer that there is probably a lot of activity in this area (I know Broadcom has a group working on this). There’s also something called the AirFuel Alliance, a recent partnership between inductive charging and magnetic resonance charging standards. Then there’s Qi (pronounced chee) which is yet another (incompatible) solution. Busy area, still very confusing but we can hope something will emerge as a workable standard at some point.

Still on power generation for wearables, there was a brief discussion on energy harvesting. Sounds like this is still very much a curiosity rather than a practical solution, except for specialized applications. Power delivery is down in the nA-uA range, nowhere near the mA range you need for anything aiming to communicate with the internet.

Good debate – wish it had gone further and there has been more fireworks, but still good information. For a review of the messy wireless charging market, read more HERE. To get my take on power in wearables, read HERE.

More articles by Bernard…

Posted on

IDMs are Much Ahead of Fabless Semicon Companies

IDMs are Much Ahead of Fabless Semicon Companies
by Pawan Fangaria on 12-06-2015 at 7:00 am
Categories: EDA, Foundries

In a balancing global economy, it’s a common phenomenon that at certain times a few sectors or segments within the sectors grow much faster compared to others. And a few companies within the growing sectors lead those sectors. Both the growing sectors and the leading companies in those sectors become the centers of attraction. In such a scenario, we tend to overlook the real picture and look at only the largest growth numbers of those centers of attraction.

Similar is the situation with semiconductor IDMs and fabless companies. Since the start of fabless model of semiconductor design, it has seen continuous high growth rate that outpaced the growth rate in IDMs in terms of percentage points. However, it’s important to note the base figures as well. Higher is the base, more difficult it is to attain a higher percentage growth number. Lower is the base, easier it is to attain a higher percentage growth; of course the company has to do well. Okay these are general perceptions; let’s look at the actual numbers.


Reviewing this IC Insights report, one can clearly see continuous high growth in fabless companies compared to IDMs. In 2010, only once, IDM semiconductor sales growth outpaced fabless semiconductor company sales growth by 6% (encircled in the chart above). According to IC Insights forecast, 2015 will be the second time when, I must say it differently; fabless company sales growth will be lower than IDM semiconductor sales growth. The reason of this twist this time is that the fabless sales growth will go into negative, while IDM semiconductor sales will remain flat. Let’s review the numbers of top10 (post-merger) IDM semiconductor sales as well as fabless semiconductor sales. Also ponder over the base sales figures in both cases.


The reason of 5% negative growth in fabless semiconductor sales in 2015 is due to 20% decline in Qualcomm/CSR’s sales. It’s obvious because Qualcomm lost Samsung application processor business as the Samsung started using its own Exynos processors in its smartphones. An interesting point to note in the fabless semiconductor table is that both the China players, HiSilicon and Spreadtrum are about to register very handsome growth in sales. Apple/TSMC sale is the application processor sales to Apple from TSMC.

It’s expected that going forward the fabless semiconductor sales will continue their high percentage growth. So, is there any possibility of their absolute sales going higher than IDM semiconductor sales anytime in future? I don’t think so.

See the absolute total sales of top10 IDMs and fabless companies in 2015; the IDM semiconductor sales are at $175+ billions compared to fabless semiconductor sales at $60+ billions. The IDM semiconductor sales are ~2.9 times higher than that of fabless semiconductor. The base sale of top IDM company, Intel is more than 3 times the base sale of top fabless company, Qualcomm/CSR. Only top3 fabless company sales are above the lowest ranked Sony’s sale among the top10 IDM companies. Sony is making great progress in O-S-D segment, an almost exclusive segment for IDMs. Among fabless companies, only Avago/Broadcom has some presence in O-S-D segment.

Any guesses on how and when fabless semiconductor sales can catch up with IDM semiconductor sales, if at all it can? We should also consider the possibilities of IDMs acquiring fabless companies where it makes sense for them to fuel innovative designs.

The IC Insights report can be found HERE for your reference.

Pawan Kumar Fangaria
Founder & President at www.fangarias.com

Posted on

Double Digit Growth and 10nm for TSMC in 2016!

Double Digit Growth and 10nm for TSMC in 2016!
by Daniel Nenni on 12-05-2015 at 12:00 pm
Categories: Foundries, TSMC

Exciting times in Taiwan last week… I met with people from the Taiwanese version of Wall Street. They mostly cover the local semiconductor scene but since that includes TSMC and Mediatek they are interested in the global semiconductor market as well. They also have an insider’s view of the China semiconductor industry which is very complicated.

The big news of course is that TSMC is predicting double digit revenue growth and 10nm is on schedule for production in 2016. What that really means is that Apple will use TSMC 16FFC exclusively for the A10 (iPhone 7) and 10nm will be ready for the A10x. Morris Chang of course predicted this last year when he said TSMC would regain FinFET market leadership in 2016. This also means that TSMC will officially have the process lead in 2016 since Intel has pushed out 10nm until 2017. So congratulations to the hard working people at TSMC, absolutely!

The other big news is that 7nm is also on track. It will be déjà vu 20nm to 16nm for TSMC where 10nm will be a very quick transitional node right into 7nm. 20nm and 16nm used the same fabs which is why 16nm ramped very quickly, one year after 20nm. 10nm and 7nm will also share the same fabs so yes we will see 7nm in 2017 and that means TSMC 7nm will again have the process lead over Intel 10nm. Exciting times for the fabless semiconductor ecosystem!

Given the quick transition of 10nm to 7nm, quite a few companies will skip 10nm and go right to 7nm. Xilinx has already publicly stated this, I’m sure there will be more to follow. SoC companies like Apple, QCOM, and Mediatek that do major product releases every year will certainly use 10nm. I would guess AMD will use 10nm as well to get a jump on Intel. That would really be interesting if AMD released 10nm and 7nm CPUs before Intel. The server market would certainly welcome the competition.

The other interesting news is that Chipworks confirmed that the A9x in the iPad Pro is manufactured using TSMC 16FF+. I have read the reviews of the iPad Pro and have found them quite funny. One very young “Senior Editor” from Engadget, who has zero semiconductor experience and doesn’t even own an iPad Pro, made this ridiculous statement:

“It’s often vaunted that ARM-based chips are more power efficient than those based on Intel’s x86. That’s just not true. ARM and x86 are simply instruction sets (RISC and CISC, respectively). There’s nothing about either set that makes one or the other more efficient.”

I brought my iPad Pro with me to Taiwan and must say it is a very nice tablet. When it first arrived I was a little shocked at how big it actually was but the performance, display, and battery life is absolutely fabulous! I’m comparing it to a Dell Core i7 based laptop and an iPad 2 of course so the bar is pretty low. But it also runs circles around my iPhone 6. Given the size of the A9x (147mm) versus the A8x (128mm) I’m wondering if it will be used for the next iPad Air. If so, that would be the tablet of the year for sure.

And can you believe our own Oakland Warriors are 20-0 to start the season which is an NBA record!?!?!?!? GO WARRIORS!!!!!

Posted on

Design and Optimization of Analog IP is Possible

Design and Optimization of Analog IP is Possible
by Daniel Payne on 12-04-2015 at 7:00 am
Categories: EDA, MunEDA

Designing Analog IP is often referred to as a “black art”, something that only highly experienced craftsmen can produce using transistor-level techniques that aren’t shared outside of their closely held group of trusted co-workers. I’d like to suggest that Analog IP can be designed and optimized by a much wider engineering audience, especially if you choose to use some automation along the way. Last year I blogged about an EDA user group meeting held in Munich, Germany and this year I attended remotely by watching an archived presentation given by Pietro Coppa of STMicroelectronics on the topic, “Design of a BandGap Voltage Reference in 40nm technology.” Pietro graduated from the Universita di Catania in 2011 and works in the Catania area of Italy where they support embedded Flash (e-Flash).

A bandgap voltage reference circuit is a temperature independent voltage reference design used inside of chips, producing a constant voltage in spite of any power supply fluctuations, temperature changes, process variation or circuit loading. Some of the analog design challenges include:

  • Yield optimization using statistical analysis
  • Mitigating effects of mismatch and process spread parameters going from 90nm to 40nm technology

The specific EDA tool used by Pietro’s group for worst case analysis, corner analysis, statistical analysis and design optimization is called WiCkeD, provided by EDA vendor MunEDA. The bandgap circuit must work across a temperature range of -40C to 150C, operate down to 0.9V, have low power consumption, and have good PSRR (Power Supply Rejection Ration) and phase margin values. Trimming is used in this circuit design to meet the yield requirements.

For their 90nm bandgap circuit design there was about a 4% yield loss for chips operating at -40C, where the desired reference of 650mV was actually measured at 800mV. By using the Montecarlo analysis of WiCked they indeed found outlier values of 828mV for this bandgap design. An investigation of the circuit design uncovered a stable point that was different from the desired one, so they fixed the circuit and re-simulated to verify the fix. On the left is the failing circuit with two stable crossing points on IV1, and on the right side is the fixed circuit with a single stable crossing point on IV1.

On the 40nm bandgap reference circuit they needed low power consumption in standby mode, during sleep and hibernate mode the switching is off, start-up time of 15uS, and managing transitions between all operating modes properly. The voltage output of the bandgap circuit naturally spans a range of values across the temperature spectrum as shown in the chart below. Engineers simulated a DC sweep across the temperature range using 10,000 runs to determine the maximum delta in bandgap value.

Optimization analysis was run using WiCkeD with 23 parameters for their bandgap circuit and it produced results shown in both numeric tables and a histogram chart.

After the first yield optimization they simulated a delta value on the bandgap of 19.6mV with a standard deviation of 2.78mV. To improve the results they made changes to a current reference then reran optimization, improving the bandgap performance by about 60% so that the delta bandgap was just 11.3mV. A buffer for VIref was also optimized using WiCkeD. The final Montecarlo analysis showed improvements in both delta bandgap and standard deviation values.

When the 40nm first silicon came back from the foundry it showed good bandgap values for their 650mV specification across the entire temperature range, so using the optimization approach really worked out. STMicroelectronics has seen that using the WiCkeD tool during the design and optimization of 40nm analog IP blocks is helping them meet first silicon success at acceptable yield.

To view all 21 of the MunEDA User Group Meeting presentations visit this page and complete the registration.

Related Blogs

Posted on

Auto ISAC—What is it and do we need one?

Auto ISAC—What is it and do we need one?
by Chan Lieu on 12-03-2015 at 12:00 pm
Categories: Automotive

An Information Sharing and Analysis Center (ISAC) is essentially a trusted entity established by critical infrastructure owners and operators to share threat data. ISACs first emerged in 1998 when President Clinton issued Presidential Decision Directive 63, which identified the nation’s critical infrastructure that could be attacked either through physical or cyber means.

The disruption of this critical infrastructure, such as banking and finance, the electricity generation and distribution network, drinking water and treatment facilities, would have a profound effect on the nation’s economic well-being. To address these risks, the federal government worked with each industry sector to establish a sector-specific organization to share information about threats and best practices for developing defenses.

Today, ISACs have been established within most of the critical infrastructure sectors and new ISACs continue to emerge as needed. For example, in the retail space where we’ve seen a series of high profile attacks against retailers such as Target and Home Depot, that industry recently established a retail ISAC, called the Retail Cyber Information Sharing Center.

So why do we need an Auto ISAC?

While there are a couple of transportation specific ISACs focused on protecting critical infrastructure, such as roads, bridges, rail, and mass transit, there isn’t an organization that focuses on the vehicles that use the roads and bridges. And frankly, there really wasn’t a need until more recently. Modern day automobiles are complex machines that can contain various embedded systems, interfaces, and networks. Furthermore, autos are increasingly featuring modems and other wireless capabilities. These wireless capabilities can support a host of features including remote tire pressure monitoring, navigation, telematics, and keyless entry and ignition start. The prospects of vehicle autonomy, self-driving capabilities, and Vehicle-to-Vehicle communications also promise tremendous benefits for efficiency, comfort, and driving safety which may be on the near horizon. The continuing trend in vehicle safety is shifting toward more interconnected systems and a reliance on sensors to identify hazards and take appropriate action.

All of these features are great and provide tremendous safety benefits, but these features also create new attack vectors that will undoubtedly increase the risk that these systems can be compromised. And when the many different systems become interconnected, then potentially really bad things can happen. While we have not seen any real world exploits of cyber-vulnerabilities in automobiles in the wild, we do know that with the increasing level of research, testing, and demonstration, it’s certainly possible to remotely take over control of a vehicle and override all driver inputs.

In 2010, researchers from UC San Diego and the University of Washington briefed NHTSA on their research. However, in order to reach out to the auto industry to disseminate their findings, the researchers would have to request meetings with the right people at each of the different auto manufacturers. One can imagine how time consuming and inefficient such a process could be.

Furthermore, those manufacturers who weren’t directly affected may not have been interested to learn about it (i.e. it’s not my problem). Had an Auto ISAC existed then, it would have been the logical and ideal place to present the discoveries. The ISAC could have analyzed the data and ensured that the proper representatives at the different manufacturers were properly informed. This specific use case, along with emerging risks that come with the many benefits of the increasing connectivity, complexity, and reliance on electronics, led NHTSA to encourage the auto industry to consider creating an auto industry specific ISAC.

ISACs have unique capabilities to provide comprehensive threat analysis within the sector and have the ability to reach out to other sectors and with government to share critical information. An Auto ISAC will help the industry share information to identify and analyze threats, vulnerabilities, and incidents specific to motor vehicles and serve as a resource to analyze potential impacts of such concerns to the sector. An Auto ISAC would also provide the industry with access to collective intelligence accumulated across the network of existing ISACs in other industry sectors, as well as potentially intelligence from the US government.

In July 2014, the Alliance of Automobile Manufacturers and the Association of Global Automakers sent a joint letter to NHTSA indicating that the industry’s intent to pursue the development of an Auto ISAC. The auto industry the started working on identifying the appropriate elements necessary to establish and maintain an Auto ISAC. Below are the seven major elements they identified.

[LIST=1]

  • Governance—Board of Directors, Committees, Task Forces, etc.
  • Membership—Eligibility, restrictions, vetting, fee structure, external partners
  • Policy—Operating framework- submission protocols, information dissemination protocols, rules of use, operating requirements
  • Technology and Supporting Infrastructure—Underlying infrastructure technology components, data analytics, communications support
  • Legal—Articles of Incorporation, Bylaws, Charter, Member Agreement, Operating Rules
  • Culture—Development of cultural framework necessary to establish and maintain a secure and trusted environment for sharing cybersecurity related information
  • Budget—Estimation of the start-up and recurring costs for operating an Auto ISAC

    Once this foundational work was complete, the auto industry announced in July that they would be launching the Auto ISAC. The Auto ISAC should be up and running in the coming months, and the timing couldn’t be better given the recent news about researchers remotely taking control of a vehicle.

    • Posted on

    Magwel’s Current Tools Take an Active Role in Power Transistor Design

    Magwel’s Current Tools Take an Active Role in Power Transistor Design
    by Tom Simon on 12-03-2015 at 7:00 am
    Categories: EDA, Magwel

    It often seems that semiconductor industry coverage focuses on large digital markets like microprocessors or high frequency analog designs for RF applications. Yes, these are large markets, but power transistors like IBGT and VFETS make up a large and crucial sector. Not only do they make their way into discretes, but they are an important part of the mobile and IoT market where they are used for PMICs and a variety of high power and high voltage applications.

    A power transistor is not a single junction but actually dozens or often thousands of parallel junctions operating in concert. Just as in digital circuits there is a premium on switching speed and coherence so that junctions are operating with the least resistance. Due to the large distributed nature of these devices, the parasitics from the metal and poly interconnect and gate and junction play a significant role in determining device performance. Engineers designing power transistors need to look at an extensive range of characteristics to fully model device behavior so they can optimize them.

    Magwel is an EDA supplier that has made power transistor modeling one of its specialties. They offer a suite of tools known as PTM (Power Transistor Modeler) for addressing the needs of power transistor designers. Because I have been working with Magwel I have become much more familiar with these products.

    One of the fundamental parameters of a power transistor is its drain-source resistance (Rdson). Magwel’s base PTM product predicts Rdson by combining linear or non-linear models for the junction when it is fully switched on with a detailed analysis of the metal and poly network connecting the source and drain terminals. This is a large network with many parallel paths, due to the large number of parallel active areas. To calculate this all the current paths are analyzed.

    The user specifies the source and drain voltages or currents as fixed values or using excitation from a Voltage Controlled Voltage Source (VCVS) which is helpful for designing sense devices. The channel can be modeled linearly with a specified channel resistance or non-linearly to account for debiasing. PTM results include voltages, IR drop, resistance per layer and current densities, which are used to predict reliability information and to look for electro-migration violations.

    PTM features a field viewer that shows voltage and current density overlaid on the layout. In addition to 2-D views, plots of the results from user selected 1-D cross-cuts can be generated. PTM also creates comprehensive reports in csv format for later analysis.

    After Rdson, gate delay is one of the next most important factors determining device performance. PTM-GD uses a 64 bit mesh based solver to extract the distributed RC networks for the gate metal and poly interconnect up through the metal stack to the device terminals. To allow accurate and fast analysis PTM-GD uses distributed RC or distributed spice models to model the distributed nature of the gate network. SPICE is then used to compute the gate delay values.

    So far we have been talking about steady state behavior, but modeling dynamic switching behavior provides an even better understanding of a power device. Magwel’s PTM-TR offers a view of the full transistor behavior over time. Using its visual feedback, designers can optimize switching performance to ensure faster and more uniform transitions across the device, minimizing power dissipation. This is especially useful for minimizing dead-time or shoot-through current in DC-to-DC converters.

    PTM-TR produces a distributed model for the gate, drain and source networks. The active areas are segmented using SPICE derived table models so that the full switching behavior can be modeled in detail. At each time of interest during switching it is possible to see the voltages and currents across the device. This makes it possible to optimize the layout to provide more optimal switching minimizing dead-time, current crowding and shoot-through currents. For example, in the case of converters, it is possible to model high-side and low-side devices operating together to obtain a very accurate transient performance of the converter.

    The final critical performance element is thermal behavior. High currents generate joule heating in the active areas and interconnect for the source and drain that in turn affect electrical properties of the device. Other external heat sources and sinks also play a factor in the thermal environment of the device. Using PTM-ET designers can fully define thermal sources and sinks in the package and even in the board. PTM-ET calculates thermal heating during operation by simultaneously solving the electrical and thermal equations for the circuit. Doing this fully considers the interdependency between thermal and electrical operation.

    We all enjoy our mobile and battery powered devices, but without highly efficient power management circuits their battery life will disappoint, leaving us without their full benefits. Thus we find that optimal design for these circuits is paramount. Magwel’s Power Transistor Modeling suite offers a complete solution for ensuring optimal power transistor performance during all aspects of circuit design. For more information please visit the Magwel website at www.magwel.com.