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28nm FD-SOI: A Unique Sweet Spot Poised to Grow

28nm FD-SOI: A Unique Sweet Spot Poised to Grow
by Pawan Fangaria on 11-11-2015 at 12:00 pm
Categories: FD-SOI, Foundries, STMicroelectronics

I have been silently watching STMicroelectronics pursuing FD-SOI technology since quite a few years. FinFET was anyway getting more attention in the semiconductor industry because of several factors involved. But from a technology as well as economic perspective there are many plus points with FD-SOI. I remember my debate, two years ago, with an IP provider for choosing between FD-SOI and FinFET for some of his IP blocks. Although we were more positive towards FD-SOI the debate was inconclusive at that time, but today the 28nm FD-SOI technology node stands to win as the best value added proposition for the emerging markets such as IoT, automotive, consumer, mobile, and so on. To expand the FD-SOI technology ST has also signed strategic licensing of their 28nm FD-SOI technology with other foundries including Samsung and GLOBALFOUNDRIES. Samsung entered into licensing agreement with ST for manufacturing collaboration on 28nm FD-SOI in mid 2014.

The industry leaders including ST are looking at scaling down the FD-SOI technology to 20nm and even 14nm to gain FinFET like performance at lower power and cost. GLOBALFOUNDRIES has already announced the availability of their own FD-SOI technology at 22nm (the 22FDX platform). In the near future we can see more development on this technology front. How’s the technology poised to provide high-performance and low-power at a low cost? I investigated in detail in a whitepaper at ST’s website.


This is an image from STMicroelectronics showing the flexibility of 28nm FD-SOI technology to modulate the effective channel length of transistors with the same abstract. The leakage current is reduced by an order of magnitude through poly-biasing. There is no junction leakage in this technology.

A single 28nm FD-SOI technology node provides a wide range of operating voltages between 0.6V and 1.1V for trade-off between power and performance. Specialized multi-threshold-voltage (V[SUB]T[/SUB]) libraries such as RVT (Regular V[SUB]T[/SUB]) and LVT (Low V[SUB]T[/SUB] ) are available.

Major EDA / IP vendors have included support of FD-SOI technology in their design flow and availability of IP on FD-SOI. Last year Cadence announced availability of IP solutions on 28nm FD-SOI process. This year Synopsys announced support of FD-SOI technology in their Lynx Design System. Mentor supports FD-SOI process in their tools and design flow as well. There are many others looking up at FD-SOI technology.


A powerful mechanism in FD-SOI technology is body-biasing (enabled in ST’s 28nm FD-SOI technology) with extremely thin buried oxide (BOX) for controlling the channel to further boost the performance or lower the power. The biasing can be modulated dynamically over a wide range during the transistor operation.

The body-biasing provides additional benefits in process compensation. In the above graph, the worst case (WC) performance trend is built using slowest (SS) and leakiest (FF) process corners. With body-biasing the SS and FF process spreads are masked together, thereby recovering performance by 17% without any dynamic power penalty.

The FD-SOI is a planar technology, simple to process at significantly lesser cost, without channel doping, and without much process variation as seen in FinFET technology. There are fewer mask layers and fewer immersion litho layers compared to FinFET technology.

ST’s standard-cell libraries based on FD-SOI technology are optimized for mainstream, low-power and high-performance applications and come in different flavours. There are mask programmable ECO cells which can be used to implement changes by changing metal layers only without the need for full mask-set reorder, thus reducing implementation time and cost. One can choose between 12-track high-performance and 8-track high-density architectures to optimize the PPA (Power, Performance and Area).


There is a wide variety of flip-flops that enable designers to choose the appropriate ones for right trade-off in their designs. Also, there are innovative multi-bit flip-flops to reduce clock-tree load and thus overall dynamic power. The leakage power is also reduced due to sharing of clock inverters between these multi-bit flip-flops. There are multi-stage synchronizers to mitigate the effects of metastability in multiple clock domains circuits.

There is a whitepaperat ST website written by N Shivaram Venkatesh and Bedanta Choudhury. Read this whitepaper to know more details about ST’s offering of standard cell libraries with FD-SOI technology for modern SoC applications. The document also provides benchmarks of 28nm FD-SOI 8T technology against other similar HKMG external references.

The SoCs are dominated by standard cells as they occupy more than half of the area, consuming almost 3/4[SUP]th[/SUP] of total power, and falling in 3/4[SUP]th[/SUP] of the critical paths on the chip. So, it’s essential that standard cells are optimized for PPA in order to optimize the SoC.The FD-SOI technology is in a sweet spot from where it can provide differentiated PPAs for different market segments.For example, ultra-low-power and ultra-low-leakage libraries can be used in IoT and wearable devices; low-power, low-costlibraries can be used in RF analog transmission, a key requirement for smartphones and network applications.

Also read this articleon the CEA-Leti’s announcement of “Silicon Impulse”, a platform to support and broaden the use of FD-SOI technology.

GLOBALFOUNDRIES announcement for support of FD-SOI at 22nm is HERE
Samsung announcement of licensing ST’s 28nm FD-SOI process is HERE

Pawan Kumar Fangaria
Founder & President at www.fangarias.com

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GlobalFoundries Visit – Part 2 – Waking the Sleeping Giant

GlobalFoundries Visit – Part 2 – Waking the Sleeping Giant
by Scotten Jones on 11-11-2015 at 8:00 am
Categories: Foundries, GlobalFoundries

In part one of this blog I described a visit to GlobalFoundries (GF) Fab 8 site in Malta New York by Daniel Nenni and myself. In this part 2 of the blog, I will describe the second day of our trip when we visited Fab 9 in Burlington Vermont. Before we got to Burlington I thought it would likely be a letdown after seeing the state-of-the-art Fab 8, but Burlington turned out to be just as interesting as Malta.

Before describing the Burlington site visit I should set the stage by describing GF’s business unit structure. GF is organizes into three business units:
[LIST=1]

  • CMOS Platforms – GF side of the business comes from the AMD and Chartered acquisitions and GF although the IBM acquisition adds technology.
  • Application Specific Integrated Circuits (ASIC) – comes from the IBM acquisition.
  • RF – comes primarily from the IBM acquisition although GF has some presence here as well from the Singapore site (former Chartered).

    Burlington Site
    Burlington is another large site and our visit began by working our way through two security gates and finding the lobby (actually the site is in Essex Junction near Burlington).

    The first briefing of the day was by Janette Bombardier, the site Vice President and location manager. The Burlington site has been in operation since 1957 and is the largest private employer in Vermont. The site uses 3.2 million gallons of water per day including 2 million gallons per day of ultra-pure water. The water comes from lake Champlain and waste water treatment is done on-site. They have reduced their water usage by 30% over the last decade. The site is fed by 150 Kilovolt power lines and they have their own smart grid delivering peak power of 65 megawatts, they have reduced peak power by 7 megawatts. There are 60,000 sensors and meters monitoring the site. The Essex Junction site and the Williston site are a combined 750 acres. Janette was very proud of the sites environmental record and highlighted the many awards they have won in this area (see Janette’s presentation at the end of this section for a list of the awards). In my experience older fab sites have not always had the best environmental record and it was refreshing to see an older site with an environmental focus.

    The Burlington site hosts several different functions:

    • Burlington is the first trusted foundry for the United States Government. Buildings 970 and 973 are now run as one 200mm wafer fab with 40,000 wafers per month capacity after a $55 million dollar capacity expansion announced the day after our visit. The fab includes over 1,400 tools and supports 30 different unique flows.
    • Burlington has a mask shop on-site with 70 tools, approximately 180 employees, and working with their partner – Toppan they produce 15,000 to 18,000 masks per year.
    • Test and final product distribution for the former IBM microelectronics division is also done at Burlington.
    • There are quality labs and information technology on site.
    • A large office complex hosts General Dynamics, the Vermont State Department of Children and Families and some IBM functions as well as GF activities.
    • A 300KW solar array test bed – the Vermont Photovoltaic Regional Test Center in partnership with Sandia and the DOE. The test bed gives the partnership a cold weather/cloudy location test capability.

    In terms of the site history:

    • 1957 to 1990 – wire relays – captive logic and memory supplier to IBM, first 200mm wafer fab in the world. Five generations of wafer sizes (presumably 3”, 100mm, 125mm, 150mm and 200mm).
    • 1990 to 2000 – sole source for IBM processes, entered OEM business for fab fill, churn of equipment and facility, DRAM manufacturing followed by logic. IBM exited the DRAM business in the late 90s.
    • 2000 to 2003 – final new server ramp, significant downsizing, future viability dependent on developing and executing a new business model.
    • 2003- 2006 – OEM business in ASICs, >50% factory load, first trusted foundry.
    • 2007 to 2010 – ASIC OEM business declined, started new RF business (7RFSOI and SiGe5PSAe) focused on cell phone Front End Module.
    • 2011 to 2014 successful RF business.

    The Burlington site products go into HDTV, Video, DVD, laptops, Automotive, Printers, etc. They Build design for others, some as a foundry and some as ASICs with much earlier involvement.

    They have ASIC design tools that are really good if you need tight timing and complex designs. They are more focused on communications and consumer now, more cost sensitive.

    The Burlington Fab 9 briefing deck is HERE.

    ASIC Group
    Our second briefing of the day was given by Jim Rogers director of ASICs. Also present were Duncan Needler from Strategic Marketing and Mark Kimely and Paul Zilkowski.

    I have to admit that I though ASICs were kind of a dying business and no longer very interesting but I was about to learn differently. In fact I now think this part of the IBM Microelectronics acquisition could be hugely important to GF!

    IBM has been the number one ASIC supplier into networking for over ten years. They don’t disclose their revenue but noted they are a multiple of eSilicon (a $250 million US dollar business, Faraday (UMC tie in) or GUC (TSMC tie in) in size (Gartner reportedly estimates that the former IBM ASIC business is over $1 billion US dollars).

    Networking customers are power and cooling limited. They have fixed power budgets for each application and want to get more performance within the power budget. Designs are becoming more parallel, some frequency scaling as well but parallelism is growing and even with node shrinks die sizes are growing. They are focused on MIPs/watt.

    Their first ASIC offering was at 500nm. They have high performance IP, unique memory options, they are an ARM licensee now (they have been for a while but didn’t announce it). With the GF acquisition they have more scale to work with, Malta is a lot bigger than East Fiskill (Fab 10, the former IBM 300mm site). They have been doing very large ASICs for external customers plus IBM processors (they also did networking for IBM when IBM was still in networking). They have pre verified IP and test and insertion so the entire system works. They typically sell packaged – tested parts with a margin, they are sort of intermediate between a foundry and a standard product. They will sometime sell tested wafers. Wafer sort is done internally but they use Outsourced Assembly And Test (OSAT) for packaging and class test. They can take a hand off at several levels, turnkey or net lists, and then they do the physical design.

    The ASIC group is currently doing ASICs in 90nm and 65nm bulk and 45nm and 32nm Partially depleted SOI technologies (PDSOI). They have a 30G backplane and 56G is available to design now as well as PCI-express gen 4 (Dan noted that other suppliers are really struggling trying to get 56G working). They also offer Ternary Content Addressable Memory (TCAM) where memory is accessed by data and not by address; this is very useful for networking tables (TCAM uses a special bit cell). They also have smaller SRAM array capability than other IP vendors or TSMC, “best dense SRAM macro in the industry”. They have more that 50 ASICs with TCAM in production (6 generations). They can make the largest TCAMs work (Dan noted that in his experience it is hard to make TCAM work). They supply all of the major network companies and have been the #1 ASIC supplier for wired communications for 11 years. They think having IP, fab, and technology development under one roof is an advantage. They have global design centers, have done some of the industry’s most complex ASICs and have an outstanding record of success.

    As interesting as all of that is, they then went on to describe their new FX-14 ASIC offering utilizing the 14LLP process manufactured at Fab 8 in Malta. As an outside observer one concern I had for GF was how they would differentiate themselves from Samsung and become more than a second source when they are licensing the 14nm process from Samsung. While we were in Burlington we heard the AMD has committed to 14LPP giving GF a volume first source customer to drive yield learning. Now GF will also have a pipeline of ASIC designs on 14LPP from the ASIC group. This announcement combines world class 56G SERDES and multi ARM core generation support, high capacity state-of-the-art 14nm manufacturing at Fab 8 on a cost effective 14LLP process with over a decade of ASIC industry leadership!

    The 14LPP FinFET architecture provides more performance per watt for connect, compute and store application and fewer watts per GHz for mobility and wireless applications. 14LLP was qualified in Q3 of 2015 and will be in volume production in 2016. 14LPP offers a 55% area reduction, up to a 50% power reduction and 85% less leakage than the 32nm ASIC technology. 14LPP will be supported with industry standard tools (IBM was proprietary tool based), there will be multiple Vt libraries for power/performance tradeoffs and an expanded IP portfolio. FX-14 will offer 64 bit ARM cores including A53 and A72 as well as 32 bit cores, 56Gbps and multiple 30Gbps SERDES designs, leading edge TCAM and the industry’s highest density and performance SRAM.

    To my view the combination of the expertise of the IBM ASIC team with the GF manufacturing scale and improved access to IP and design tools offers a very powerful combination. Jim Roger’s apparently feels the same way because he smiled from ear to ear through his entire presentation.

    The FX-14 briefing deck is available HERE.

    RF Group
    Bami Bastani, the senior VP for RF gave us a briefing on the RF business. Also present was Stephen Lace RF Chief Technical Executive, product managers Peter and Christine and Duncan Needler from Strategic Marketing.

    The front end of cell phones has to support a variety of different frequency bands and standards for 3G and 4G data and voice. The Front End Modules (FEM) may include multiple antennas with antenna tuning for each antenna, antenna switching, multiple filters and multiple power amplifiers. IBM’s combination of Partially Depleted SOI technology (PDSOI) and Silicon Germanium (SiGe) technology have made them a huge player in this space. RF SOI utilizing PDSOI has emerged as the technology for RF switches as well as some antenna tuning and a small amount of power amplifier applications. SiGe is used to address power amplifiers and also automotive radar. IBM’s RF SOI technology has shipped over 17 billion parts and the SiGe technology has shipped over 3 billon products although power amplifiers are still dominated by Gallium Arsenide (GaAs). SiGe power amplifiers are also used in WiFi modules for cell phones. They 65nm RFCMOS typically used for WiFi don’t have a good enough power amplifier and they are often bypassed for a SiGe power amplifier. RF SOI devices reduce parasitics, provide higher Q – lower loss, increased isolation and linearity and better economics than III-V solutions such as GaAs. RF SOI can be produced on 200mm and even 300mm wafers whereas GaAs is still on 150mm wafers.

    The acquisition of IBM microelectronics by GF provides a global network for RF as well as increased investment. While we were in Burlington we heard about a $55 million dollar investment in additional capacity in the Burlington fab. GF’s Singapore site also has 200mm and 300mm capacity for RF. GF has bene doing some 300mm RF in Singapore for capacity reasons but they don’t see it as more economical than 200mm due to substrate cost and depreciations. Moving forward to 5G and millimeter wave applications 45nm RF SOI likely on 300mmm will offer the next generation solutions. They will still support 180nm/130nm on 200mm for 3G and 4G and then do 45nm for 5G.

    The current market for RF SOI is estimated to be approximately 60,000 wafers per month primarily driven by switch and tuner applications.

    By producing RF on SOI substrates logic can be integrated onto the same product. The RF business is a classic foundry business with customers doing their own designs and buying wafers from GF. GF does provide some simple standard cells. GF RF business is the leader in the market shipping primarily from Burlington with some capacity coming from Altis in Europe (former IBM site) and Singapore ramping up.

    The RF business offers another growth path for GF.

    The RF presentation is available HERE.

    Mask shop
    We ended our visit to Burlington with a tour of the mask shop. The mask shop supports masks sets all the way down to 7nm and has EUV mask capability. Currently the mask shop supports Burlington (Fab 9) and East Fishkill (Fab 10) but they are now working on masks for Fab 8 and may support provide support to other GF sites as well.

    Conclusion
    Often acquisitions are touted as providing “synergies” that are hard to envision and even harder to realize. After visiting Fab 8 in Malta and Fab 9 in Burlington the potential synergies are very clear.

    • The acquisition of an experienced IBM development team offers GF the potential to develop their own 10nm and 7nm technologies as opposed to licensing technologies from others as they had to do at 14nm.
    • The former IBM ASIC business is a leading supplier of ASICs for networking. The combination with GF provides more advanced process technology, manufacturing scale and a parent company in the same business. There is a potential here to make the ASIC business stronger while providing GF with a customer stream for the 14LLP technology.
    • The former IBM RF has been capacity and resource constrained. They now have access to greater resources and capacity to drive into 5G and continue to support 3G and 4G.

    The bottom line to me is the acquiring the IBM microelectronics business fill gaps in GF and in the IBM businesses and offers the opportunity for real and lasting synergy. Of course as we discussed in part one execution will be key. Watching how this plays out over the next couple of years will be fascinating and will ultimately determine whether GF can become a truly viable leading edge pure play foundry.

    You can read part one HERE.

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    64-bit for the masses with Cortex-A35

    64-bit for the masses with Cortex-A35
    by Don Dingee on 11-10-2015 at 12:00 pm
    Categories: Arm, IP

    It has been four years since the announcement of the ARMv8 instruction set, three years since the launch of the ARM Cortex-A57 and Cortex-A53 cores, and two years since the Apple A7 with its “Cyclone” core blew away any misunderstanding of 64-bit as being just for servers.

    There is, however, still this idea that 64-bit is only for flagship mobile devices. Continue reading “64-bit for the masses with Cortex-A35”

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    Verification with Tcl for what? – part 2

    Verification with Tcl for what? – part 2
    by Anatoly Myshkin on 11-10-2015 at 7:00 am
    Categories: EDA

    In Orion Bytes we use Tcl both for the internal research, product and different verification services. We use also SystemVerilog UVM and Python based Cocotb for different approaches. I think it’s no need to deep into the SystemVerilog and UVM principles here – today’s main verification fashion is well described through the web and books.
    Continue reading “Verification with Tcl for what? – part 2”

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    Real Men Use ASIC

    Real Men Use ASIC
    by Bernard Murphy on 11-09-2015 at 4:00 pm
    Categories: eSilicon, Semiconductor Services

    As we watch the gravitational collapse of the semiconductor industry, it becomes increasingly obvious that the tech zeitgeist, with investment in close lockstep, is squarely centered on complete solutions, not enabling technologies. That this seems unfair (they couldn’t do it without us, and what we do is really, really hard) is irrelevant. The money goes to those who provide value directly to the end-users and no amount of special pleading will change that. Believe me I understand – my roots are in EDA, an enabling technology to an enabling technology. I feel your pain.

    Back in the mists of time, Jerry Sanders of AMD said “real men have fabs”, meaning that real semiconductor companies do it all themselves – from design through to delivery of the final product. He probably wishes he never said that. Most semis ceded manufacturing, assembly and test to the foundries and other outsourced experts, allowing them focus on differentiated design expertise – all the way from architecture down to GDSII. A good part of that differentiation is in the back-end of the process, which is very expensive in highly-qualified staff, tooling and contracting with the foundries and OSATs; this represents a major fixed cost for any chip design company.

    That may be the cost of doing business if your business is building chips, but what if you are building end-user solutions? You still need the performance, power and cost advantages of semi-custom, but why carry that back-end cost if you only need to build one or two high-performance custom chips a year? Networking companies have seen it this way for a long time. They’ll do all the logic design and rely on an ASIC company to make the rest of the process completely turnkey. Increasingly I think all but the largest OEMs are going to see it the same way, especially now you can buy most of the IP you need. You’ll give up a little in power and performance and maybe some cost, but your competitive advantage is in your complete solution; for your purposes an underlying device may only need to be “good enough”, a position a device maker in a competitive market could not afford.

    Which brings me to eSilicon. ASIC as most of us remember it was certainly turnkey, but only after you had navigated a convoluted qualification and estimation stage. To get to a quote could take weeks and tied up a lot of your time. All of which significantly limited comparison shopping. eSilicon has changed this in important ways which are very relevant to this new wave of end-user solution providers, and that starts with how you get a quote. Paul McLellan already blogged about GDSII Explorer, the eSilicon quote generator, so I won’t repeat his detailed summary here. The most important point for my purposes is that you can generate a quote in real-time, on-line by providing just enough information about the process technology and foundry you want to use, die area, package and so on. Importantly, you don’t have to provide a design at this stage. You get NRE and volume costs in just a few minutes and this isn’t an estimate – it’s a binding contract with all the legal boilerplate.

    Now imagine how a solution provider can use this. In fact, we don’t have to imagine because Mike Gianfagna (VP Marketing at eSilicon) told me about a real case (no names). Without interacting at all with eSilicon, other than through the website, this company used the generator to build the cost part of their business plan, which they then used to raise funding. Once they had the cash, they ran the generator again to build a final quote, approved the quote and started the engagement. eSilicon had no (human) interaction with them until that point and was able to deliver prototypes in 3 weeks from tapeout. This looks to me like the kind of semi-custom design solution the entrepreneurs of our time really need.

    So do real men (or women) use ASIC? If you measure by what you do being really hard and producing the absolute best outcome (for a general market) that it can, then perhaps not. But there are plenty of other industries building high quality complex products which are not known for being highly profitable. If instead you want to measure by who makes the most money, then yes, I think real men (and women) are going to be flocking to ASIC, very possibly built through eSilicon.

    More articles by Bernard…

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    Automobiles and the DMCA

    Automobiles and the DMCA
    by Chan Lieu on 11-09-2015 at 12:00 pm
    Categories: Automotive

    When you drive a car off the dealer’s lot, you own the whole vehicle, right? For decades, car owners have popped the hood and crawled under the car to do their own maintenance; and for those mechanically inclined, even make modifications to improve performance or handling. However, in an era where a car is increasingly controlled by software, the right to tinker with your vehicle has been called into question. After all, software is often sold under a license and the end user doesn’t actually own the code. This means there is a lot of uncertainty about to what extent the public can modify the software embedded in a car.

    Today the Library of Congress brought a bit more clarity to the situation by granting exemptions from the Digital Millennium Copyright Act (DMCA) that would enable the public to delve into the embedded systems and software in their vehicles for “good faith security research” and “lawful modification.” This was a much anticipated decision that captured the attention of everyone from the auto industry to the cybersecurity research community.

    How did we get here?
    Section 1201 of the DMCA makes it illegal to circumvent access controls and technical protection measures. In 1998, Congress ostensibly intended for this provision to stop content pirates from defeating digital rights management (DRM) and other content access restrictions restrictions on copyrighted works (i.e. stopping people from breaking encryption on CDs and DVDs). However, Section 1201 isn’t limited to just CDs and DVDs—it applies any bit of protected software. Whether intentional or not, Congress wound up giving rights holders and and manufacturers complete veto power over any examination of their code—any interested party would need permission to avoid being in violation of the DMCA. Critics argue that in practice, the DMCA has actually chilled a variety of legitimate activities that require breaking DRM, such as in academic research.

    Petitions for Exemptions
    Once every three years, the Librarian of Congress, through the Copyright Office, hears requests from the public on whether there are any new classes of works that will be exempt from section 1201’s prohibition. Last October, the Librarian considered a number of classes eligible for exemption, including software that controls automobiles. Since modern automobiles are controlled by a mixture of software, microprocessors, and computers (known in the auto industry as electronic control units, or ECUs), the DMCA could have potentially protected or limited access to the software and logic on those ECUs. However, many repairs require access to the software, as does research into vehicle safety. Petitioners, such as the Electronic Frontier Foundation, argued that when auto manufacturers deploy technology (i.e. encryption) to prevent access to the code, that can transform an act of repair or research into a DMCA violation. The EFF concluded that only persons authorized by the vehicle manufacturer could effectively perform repairs, and independent audits of vehicle safety and security would take place under a legal cloud, if at all.

    Black Hat and VW’s defeat devices
    Access to the underlying code that runs a car came to light this past summer when two well-known independent security researchers, Charlie Miller and Chris Valasek, discovered a vulnerability in a Jeep Grand Cherokee. Presenting their research at Black Hat 2015, the two demonstrated how they were able to exploit that vulnerability and remotely take over full command and control of the vehicle. While vehicle cybersecurity vulnerabilities have been previously researched and discovered, and the results have widely disseminated, Miller and Valise’s definitely brought the issue of automotive cybersecurity into the forefront of public awareness.

    In another high profile case, researchers at West Virginia University found that Volkswagen had installed special defeat software to control the vehicles’ pollution-control systems to run cleanly during emissions testing, but allowed the vehicles emit higher levels of pollution during normal daily operations.
    With today’s announcement, the U.S. Copyright Office has ensured that important legitimate research into a vehicle’s embedded systems and software can continue without the threat of legal action.

    Don’t forget to follow SemiWiki on LinkedIn HERE…Thank you for your support!

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    Forget about ThunderBolt, USB Type C is here!

    Forget about ThunderBolt, USB Type C is here!
    by Eric Esteve on 11-09-2015 at 7:00 am
    Categories: Cadence, IP

    At the early days of Semiwiki (March 2011), I wrote about ThunderBolt, predicting low market adoption of the protocol, for various reasons. One of these reasons was the cost associated with ThunderBolt integration by the OEM. Even if the protocol (associating PCI Express and DisplayPort) was offering better data bandwidth than competitors, the over-cost was too high. Why the cost of ownership was prohibitive? Because an OEM could not just buy an IP and integrate it into an application processor but had instead to buy a ThunderBolt IC to a chip maker who had licensed the technology. This strategy (and probably other factors) has killed ThunderBolt adoption on a wide scale.

    Let’s have a look at a 20 years old success story (still going on), the massive, ubiquitous pervasion of USB protocol. USB has been with Ethernet at the source of the so-called Interface IP market (weighting $500 million in 2015). The recent launch of USB Type C could illustrate the Italian proverb: “Chi va piano va sano, chi va sano va lantano”… Between 1995 and 2015, the bandwidth delivered by USB has moved from 12 Mbps to 10 Gbps!

    As any interface layered protocol, USB is made of a digital part (Controller) and a mixed-signal physical function (PHY), both interfacing by the means of the PHY Interface for PCI Express (PIPE) function in this case. The new Type-C connector is defined to support USB 2.0, USB 3.0, USB 3.1 or a combination of two. In the above example, Type-C supports USB 3.0 compliant protocol, backward compatible with USB 2.0, so the integration of the two PHY. But the revolution is with Type-C new capabilities, one being the connector-agnostic capability: everybody has once failed plugging USB connector right the first time and turns it to finally succeed…

    The power delivery is specified up to 100W on a Type-C external connector, such a feature should be highly appreciated in the mobile application world as it’s going with scalable power charging, which means that power consumption may dynamically change depending on the application’s needs. USB Type-C complete features list

    • Reversible plugs with two-way insertion; the host and device connectors are the same
    • Higher data rates, up to 10Gbps for USB Type-C 3.1 Gen2
    • Increased power, up to 100W through support for the USB Power Delivery 2.0 specification
    • Bi-directionality, so that devices can provide and consume power
    • Scalable power charging

    Capitalizing on this USB Type-C revolution, Cadence has developed an IP subsystem going further, offering the industry’s first IP subsystem with pre-verified components including a single-chip port controller IP that integrates USB Type-C™, USB Power Delivery and DisplayPort™ Alternate Mode (Alt Mode). The IP subsystem architecture clearly shows the IP organization, including Tensilica Xtensa CPU to offload USB Type-C Port Controller:

    The integration of the IP as a single-chip solution is important for mobile and cost-sensitive consumer devices where a single connector, lower bill of materials (BOM) costs and reduced board size can provide significant competitive advantages. The complete IP subsystem includes:

    • USB 3.0 xHCI Host and Device certified controller IP, which can be combined into a Dual Role Device Controller
    • USB Type-C Port controller (TCPC) IP
    • DisplayPort 1.2a Transmitter (Tx) controller IP
    • Embedded Tensilica® Xtensa® CPU
    • Multi-protocol USB 3.0 and DisplayPort 1.2a PHY IP for 28nm
    • USB 2.0 certified PHY IP for 28nm
    • Drivers for embedded systems and Linux OS

    In consumer market, integrating a connector has always been a burden. I still remember this mature guy telling me (in 1990) about his first experience as marketing engineer in charge of Philips Razor, the rule was “no connector”, and the main reason was cost!

    The rule is obviously false for mobile products developed today for the consumer market, but if you look a smartphone, the space available on product edges is limited, adding a connector will always increase overall cost. USB Type-C connector will soon become ubiquitous and combining audio, video, USB data and USB Power Delivery, will enhance the USB functionality, and provide a very cost effective solution.

    Just remember ThunderBolt, the idea was good, but wide market adoption has failed, and the main reason was prohibitive cost (inducing low number of available peripherals), as well as the ban of IP sourcing has prevented integration and de-facto lowering the overall cost. USB Type-C connector adoption will help escaping these issues and products like this IP subsystem from Cadence will provide similar performance… at a fraction of ThunderBolt cost.

    By Eric Esteve from IPNEST

    More articles from Eric…

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    A moment of IoT silence before we disrupt

    A moment of IoT silence before we disrupt
    by Don Dingee on 11-08-2015 at 12:00 pm
    Categories: ESD Alliance, Events, IoT, Semiconductor Services

    As I sat down in the SEMI Arizona Chapter breakfast meeting a few weeks ago, a moment of semiconductor history flew right before my eyes before the IoT sessions started.

    We were seated in the cafeteria of Freescale Building 94 on Elliot Road in Tempe, a place I’d been many times before, except this time may have been the last. NXP is consolidating facilities in Arizona early in 2016 Continue reading “A moment of IoT silence before we disrupt”

    Posted on

    What do Rockets and GF Fab 8 Have in Common?

    What do Rockets and GF Fab 8 Have in Common?
    by Daniel Nenni on 11-08-2015 at 7:00 am
    Categories: Foundries, GlobalFoundries

    An interesting thing happened during the driving tour of the GlobalFoundries Fab 8 in Malta, NY. We happened by an old structure with quite a bit of history. As it turns out, the “Malta Test Station”, a former US Army fuel and explosives testing facility, was the actual birthplace of the United States’ Space & Missile programs. In fact, Hermes Road, one of the main access roads, is named for the Hermes Missile Program circa 1944.

    According to Wikipedia, after World War II we “borrowed” some German V-2 missile parts and the engineering team that invented them including Wernher von Braun. Wernher worked for the U.S. Army on ballistic missiles, then NASA where he was director of the Marshall Space Flight Center, and was later dubbed the “greatest rocket scientist in history”. Check out this guy’s resume:

    [TABLE] cellspacing=”3″ style=”width: 352px”
    |-
    | Born
    | Wernher Magnus Maximilian, Freiherr von Braun
    March 23, 1912
    Wirsitz, Posen Province, Prussia, Germany
    (now Wyrzysk, Piła County, Poland)
    |-
    | Died
    | June 16, 1977 (aged 65)
    Alexandria, Virginia, U.S.
    |-
    | Resting place
    | Alexandria
    |-
    | Nationality
    | German/American
    |-
    | Alma mater
    | Technical University of Berlin
    |-
    | Occupation
    | Rocket engineer and designer, aerospace project manager
    |-
    | Spouse(s)
    | Maria Luise von Quistorp (m. 1947–77)
    |-
    | Children
    | Iris Careen von Braun
    Margrit Cecile von Braun
    Peter Constantine von Braun
    |-
    | Parent(s)
    | Magnus von Braun (1877–1972)
    Emmy von Quistorp (1886–1959)
    |-
    | Awards
    | Elliott Cresson Medal (1962)
    Wilhelm Exner Medal (1969)[SUP][1][/SUP]
    National Medal of Science (1975)
    |-
    | colspan=”2″ | Military career
    |-
    | Allegiance
    | Nazi Germany
    |-
    | Service/branch
    | SS
    |-
    | Years of service
    | 1937–1945
    |-
    | Rank
    | Sturmbannführer, SS
    |-
    | Battles/wars
    | World War II
    |-
    | Awards
    | Knights Cross of the War Merit Cross (1944)
    War Merit Cross, First Class with Swords (1943)
    |-
    | Other work
    | Rocket engineer, NASA, Chief Architect of the Saturn V rocket of the Apollo manned moon missions, engineering program manager
    |-

    Back to the Fab 8 tour, Scott Jones and I got the VIP treatment. Scott not only has worked in fabs, he has built them, so he was my translator and chief question asker. Scott will be writing about this trip as well so you may want to read his observations and opinions here: “Global Foundries Visit – Part 1 – It’s All About Execution”.

    The clean room tour is always interesting. Since I have been through about a dozen of these around the world I have quite a few reference points and can tell how modern a facility it is, where they are in the production cycle, and how busy they are. Contrary to popular belief, the less people working inside a clean room the better and I do count people. I also look at the wafer transport system, how modern it is, how fast it goes, and how many wafers are flying around. They never talk about who the wafers belong to but in this case I already knew (AMD, both CPU and GPU, GPUs first). There are no secrets in Silicon Valley… Needless to say Malta did not disappoint in all categories above, not even close.

    GLOBALFOUNDRIES Achieves 14nm FinFET Technology Success for Next-Generation AMD Products

    “FinFET technology is expected to play a critical foundational role across multiple AMD product lines, starting in 2016,” said Mark Papermaster, senior vice president and chief technology officer at AMD. “GLOBALFOUNDRIES has worked tirelessly to reach this key milestone on its 14LPP process. We look forward to GLOBALFOUNDRIES’ continued progress towards full production readiness and expect to leverage the advanced 14LPP process technology across a broad set of our CPU, APU, and GPU products.”


    After Malta, Scott and I drove down to Burlington for a day at Fab 9 with presentations about the history of the fab, the RF and ASIC groups. I will wait for Scott to post his blog then add my two cents.

    Don’t forget to follow SemiWiki on LinkedIn HERE…Thank you for your support!

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    GlobalFoundries Visit – Part 1 – It’s All About Execution

    GlobalFoundries Visit – Part 1 – It’s All About Execution
    by Scotten Jones on 11-06-2015 at 12:00 pm
    Categories: Foundries, GlobalFoundries

    Fabless companies and the need for foundries
    The success of fabless semiconductor companies is well documented with companies such as Qualcomm, Broadcom, MediaTek, AMD, Avago and others selling semiconductors made using the fabless model (see Fabless: The Transformation of the Semiconductor Industry by Daniel Nenni and Paul McLellan for more information). Fabless semiconductor companies are growing faster than the overall semiconductor industry and are becoming more important with each passing year. Mobile devices such as cell phones and tablets are particularly dependent on the fabless semiconductor industry. There are also companies such as Apple and Cisco that produce products that are dependent on semiconductors they design and manufacture using the fabless model. Of course the fabless model can only exist if foundries are available to produce the products the fabless companies design.

    In the foundry industry today there are really only four companies that are driving to be first producers of the latest technologies, TSMC, GlobalFoundries, Samsung and Intel. The first four are the only foundries ramping 14nm class processes today and of them only TSMC and GlobalFoundries are pure play foundries. Companies such as UMC and SMIC are now followers with 14nm plans that are not yet implemented. All other things being equal, pure play foundries are the preferred solution because they are focused on foundry, it is their core business. The IDM’s such as Samsung or Intel that offer foundry have other corporate priorities and may even compete with their customers.

    The fabless industry is well aware of the dangers of being sole sourced. This was really driven home as recently as the 28nm node where TSMC was the only viable supplier for over a year. It is critically important to the fabless industry to have two or more sources of leading edge technology available and as previously discussed they would ideally be pure play foundries.

    In my opinion the preceding discussion makes the case that GlobalFoundries succeeding as a foundry is of great importance to the fabless semiconductor industry!

    A Brief History of Global Foundries
    Advanced Micro Devices (AMD) is a manufacturer of Microprocessors for Personal Computers (PCs) (among other products). For many years AMD was an Integrated Device Manufacturer (IDM) manufacturing microprocessors in their own fabs and locked in a battle with Intel for success in the PC market place. Intel consistently had larger market share, greater profitability and ultimately greater manufacturing scale and ability to invest in new technologies and facilities. Over time AMD’s cash position eroded to the point where they could no longer afford to make the investments required to stay on the leading edge for fab technology and risked falling behind Intel in performance further eroding their market share. In 2009 AMD reached an agreement to divest their fabs to Advanced Technology Investment Corporation (ATIC) a subsidiary of the Emirate of Abu Dhabi and Global Foundries (GF) was born.

    GF started with two 300mm wafer fabs in Dresden Germany with a combined capacity of approximately 45,000 wafers per month and an empty site in Malta, New York where a new 300mm fab was planned. With ATIC as a backer, GF had the financial resources to update and expand Dresden and to break ground in Malta on a new fab. GF also received contracts to supply AMD as part of the deal. From AMD’s perspective, they got a manufacturing source for their microprocessors and no longer had to make the enormous investments to build and upgrade state-of-the art wafer fabs.

    In 2010 ATIC followed up their initial acquisition of AMD’s fabs by acquiring Charted Semiconductor. Chartered was a pure play foundry headquartered in Singapore and at the time of the acquisition was the third largest foundry in the world on a revenue basis behind TSMC and UMC. Chartered had always struggled with profitability trailing their larger rivals and the acquisition offered Chartered greater scale and financial resources.

    Finally in 2015 GF acquired the microelectronics business of IBM. IBM microelectronics adds additional fabs, a huge portfolio of patents and a large and highly experienced development team. IBM had a long history of leadership in semiconductor technology development having invented scaling, the 1T DRAM cell (used in all DRAM today), developed CMP and copper interconnect and more.

    GF now has four – 300mm fabs around the world, Fab 1 (former AMD site) in Dresden producing 45nm to 28nm technologies (22nm is in development) with 60,000 wafers per month (wpm) capacity, Fab 7 (former Chartered site) in Singapore producing 180nm to 40nm technology with 68,000 wpm capacity (they also have several 200mm fabs in Singapore), Fab 8 (greenfield GF fab) in Malta, NY producing 28nm and 14nm, and developing 10nm and 7nm technology with 60,000 wpm capacity and Fab 10 (former IBM site) in East Fishkill, NY producing 90nm to 14nm technology with 14,000 wpm capacity. The IBM acquisition also added a 200mm fab in Burlington, VT producing 180nm to 130nm RF wafers (more about this in part 2).

    To-date GF has successfully brought up 28nm technology in Dresden and in Malta NY but they were later than TSMC. At 14nm GF was developing their own 14nm technology but they abandoned the development effort and licensed 14nm from Samsung. As an outside observer the impression I have of GF is they have a lot of worldwide scale and resources but that they have struggled with execution.

    When Daniel Nenni offered me the opportunity to visit the GF Malta and Burlington sites, tour the sites and meet key GF executives for briefings on the company I jumped at the chance to go. In the balance of this article I will discuss our visit to the Malta NY site; in a following blog I will discuss the Burlington VT visit.

    Malta Fab 8 Visit
    Fab 8 is GF’s flagship site and the home of their most advanced technology development efforts.

    Site Tour
    Our visit began with a driving tour of the Fab 8 site. There is currently a massive cluster of buildings on the site. Looking at the buildings from the front there are two large administration buildings, behind the administration building to the left is fab 8 – phase 1 and phase 2. Phase 1 is a 200,000 square foot cleanroom with a capacity of approximately 40,000 wpm and phase 2 is a 100,000 square foot cleanroom. The combined phase 1 and phase 2 cleanrooms are equivalent to approximately six US football fields in area! Behind the right side of the administration buildings is another 100,000 square feet of cleanroom space originally used as a Technology Development Center but now renamed phase 3. Phase 1 is currently fully fitted-out with tools and phase 2 and 3 are being fitted-out. Current capacity is stated as approximately 60,000 wpm, presumably when phase 2 and 3 are completely fitted-out that number may be higher depending on the complexity of the technologies being run.

    The Malta site also has space for two more fabs similar in size to the existing fab providing the potential to ramp the total site up to approximately 180,000 wpm.

    The site also has some interesting pre GF history in rocket development with a lot of old buildings and test structures still in place.

    The overall site and buildings are simply massive. The employee parking lot appeared to be full and there was a large contractor area that was also full and busy.

    Meeting with Gary Patton
    Gary Patton ran development for IBM microelectronics for eight years prior to GF acquiring IBM microelectronics. Gary is now the Chief Technical Officer for GF and responsible for all of their technology development. I asked Gary is being CTO at GF required a change in mind set. I suggested that at IBM development was likely performance first and cost a distant second but Gary disagreed sighting his work on the bulk technologies for the common platform. He said he had a lot of experience with developing for cost and performance per watt. His job now is to accelerate technology development at GF and make sure there aren’t silos. Gary has established a process council with members from the sites around the world to promote cooperative technology development across the company. One of the things that were clear early on in talking to Gary was a focus on execution, “Say what you do and do what you say to establish credibility”. Gary noted that GF was late on 14nm and late starting on 10nm, at 7nm they started early and they are really pushing. The 7nm technology can be run using multi-pattering but EUV may offer some advantages if it is ready.

    Gary also noted that even with the acquisition of IBM Microelectronics by GF, IBM is still involved in semiconductor R&D. IBM retained Yorktown Heights and the Almaden Research Center and is involved in Albany Nanotech. R&D developed at those locations then feeds into Malta where the development team bolstered by the influx of IBM researchers is focused on 10nm and 7nm development. The IBM acquisition brought in a lot of experienced researchers to Malta and there is now a dedicated 10nm and 7nm development team whereas in the past development was done by manufacturing. From the IBM perspective the deal has freed IBM from having to invest in low volume production. GF will provide customized processes to IBM for their relatively low volume server requirements. Former IBM operations such as RF that was constrained to Burlington and ASIC that was constrained on IP are now unconstrained (more on that in part 2).

    The IBM 14nm technology will stay in East Fishkill (Fab 10 now). 14LPE acquired from Samsung is run in Malta plus 14LPP is built off of the 14LPE base and will also run in Malta. 14LPP is the same design rules as 14LPE and offers a 10% to 14% performance improvement over 14LPE. When 28nm was brought up in Malta there was no base to work off of, now the 14nm ramp is leveraging the 28nm experience. Both 14LPE (E for early) and 14LPP (P for performance) are ramping in Malta and have “world class yields”. 10nm and 7nm development is all being done in Malta.

    I asked Gary for his view of FDSOI versus FinFETs. He said he didn’t see it as “versus”. FDSOI body bias is a great capability but FinFETs are better for high-end smart phones and performance and FDSOI is better for low power. Throughout the interview Gary was very poised and confident. He was very interesting to talk to and I would have been happy to have had more time for the discussions.

    Gary’s Presentation

    Meeting with Tom Caulfield
    Tom is the senior VP responsible for the Fab 8 site. Tom noted that Fab 8 was originally going to be an AMD fab. Phase 1, 2, and TDC (now phase 3) are now close to 400,000 square feet. Development on the site is now done as a development “corridor” inside the manufacturing “corridor”.

    As was covered above the 14nm technology was licensed from Samsung, the transfer was done as a copy smart. Some recipes were transferred one to one, some had to be modified because the tools were different. There were approximately twenty Samsung engineers on site and morning and afternoon conference calls. During the transfer they were always within one quarter of where Samsung’s S1 fab was and typically within 2 months. By buying Samsung’s process Samsung and GF basically split the cost of the development. The Samsung and GF 14nm processes are PDK compatible.

    At 10nm/7nm the technology will be IBM driven. He thinks 7nm options are so limited that industry wide the processes will be similar. Current optical technology capabilities have defined how 7nm will be done. The usage of 14nm and even 10nm is driven by performance, at 7nm the driver will be economics. 7nm as defined today is economical even if done optically; EUV will be an opportunistic adder.

    We talked a bit about the pyramid of systems companies supported by semiconductor companies supported by materials and equipment companies. Equipment companies used to just build tools but now they have to provide processes. They even supply some modules but individual steps are better. Tom talked about how the Eco system has to have a value proposition at each level or the model collapses.

    In terms of why GF acquired IBM microelectronics:
    [LIST=1]

  • Scale – you need at least $1B per year for R&D to stay competitive.
  • Bought a set of IP that makes the GF offering richer and brought in new customers.
  • Bought an R&D team. The IBM acquisition will let GF develop future technologies internally.

    GF now has the “Malbany” corridor, Malta to Albany in about 29 minutes. The scale they are building is reaching the point that suppliers are setting up locally. For example, bulk hydrogen peroxide transportation is a big part of the cost coming from Texas, but now a hydrogen peroxide plant is being set up near Malta.

    Tom also noted that 28nm launched at Fab 8 in June of 2014 established manufacturing so that infrastructure was in place for 14nm. GF currently has 14LPE in production on one part and 14LPP has two parts ramping production now and they will exit Q1-2016 with a least six parts.

    We also talked about 20nm/16nm and the possibility that 10nm/7nm will be similar. Daniel has noted that 20nm and 16nm shared the same equipment set and 20nm ended up being a very short lived node. Daniel thinks 10nm may also be a short lived node with a quick shift to 7nm using the same equipment. Tom noted that at 20nm foundries didn’t make their R&D investment back and 10nm could be similar. 20nm succeeded at TSMC because Apple designed down to it and paid for the technology. Others who didn’t design down to it weren’t successful because the power performance wasn’t there.

    I asked Tom about FDSOI versus FinFET and got my favorite quote of the trip. “FDSOI and FinFET competition is like a screwdriver and hammer fighting, they are different tools”. FDSOI is Internet of Things (IOT) and FinFET is big data. Earlier in the session we had discussed how IOT doesn’t really get interesting until you load the data up into a server and start running expert systems on it. They are complimentary pieces.

    As a final observation Tom said you put values in place to judge behaviors. GF is focused on execution and measuring against that. They have met everything they said they would at 14nm.

    Throughout our interview Tom was enthusiastic and energetic about GF and where they are going. I would also say that everything I heard from Gary and Tom matched up very well especially on the need for execution.

    In summary at Fab 8 in Malta GF seems to have gotten the message that they have to execute and they are focused on making it happen! I came away both impressed and optimistic for the future of GF.

    Tom’s Presentation

    In the next installment I will discuss Burlington. Going in I expected Malta to be the highlight of the trip but Burlington held it own and has it’s own really interesting pieces to add to the GF puzzle.