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December 15, 2015

Why Connect to the Cloud with Atmel SMART SAM W25?

Why Connect to the Cloud with Atmel SMART SAM W25?
by Eric Esteve on 12-15-2015 at 4:00 pm
Categories: Arm, Foundries, IP

Atmel SMART SAM W25 is in fact a module, Atmel names it “SmartConnect Module”. As far as I am concerned I like SmartConnect designation and I think it could be used to describe any IoT edge device. The device is “smart” as it includes a processing unit, in this case ARM Cortex M0 based SAMD21G, and “connect” remind the Internet part of the IoT definition. The ATWINC1500 SoC supports WiFi 802.11 b/g/n allowing to seamlessly connecting to the cloud. What should we expect from an IoT edge device?

It should be characterized by both low cost and power! This IoT system is probably implemented multiple times, either in a factory (industrial), either in a house (home automation) and the cost should be as low as possible, to enable large dissemination. I don’t know the SAMD21G ASP, but I notice that it’s based on the smallest MCU core of the ARM Cortex M family, then the cost should be minimum (my guess). Atmel claims the W25 module to be “Fully-integrated single-source MCU + IEEE 802.11 b/g/n Wi-Fi solution providing battery powered endpoints lasting years”…sounds like being ultra low-power, isn’t it?

The “Thing” of IoT is not necessarily tiny. We can see on the above example in the industrial world that the interconnected things can be as large as these wind turbines (courtesy of General Electrics). To maximize efficiency in power generation and distribution, the company has connected these edge devices to the cloud where the software analytics allow wind farm operators to optimize the performance of the turbines, based on environmental conditions. According with GE, “raising the turbines’ efficiency can increase the wind farm’s annual energy output by up to 5%, which translates in a 20% increase in profitability”. Wind turbines are good for the planet as they allow avoiding burning fossil energy. IoT devices implementation allows wind farm operators to increase their profitability and to build sustainable business. At the end, thanks to Industrial Internet of Thing (IIoT), we all benefit from less air pollution and more affordable power!

ATWINC1500 is a low power Systems-On-Chip (SoC) bringing Wi-Fi connectivity to any embedded design. In the above example this SoC is part of a certified module, ATSAMW25, Atmel Wi-Fi solutions for embedded designers seeking to integrate Wi-Fi connectivity in their system. If we look at the key features list:

IEEE 802.11 b/g/n (1×1) for up to 72 Mbps
Integrated PA and T/R switch
Superior sensitivity and range via advanced PHY signal processing
Wi-Fi Direct, station mode and Soft-AP support
Supports IEEE 802.11 WEP, WPA
On-chip memory management engine to reduce host load
4 Mbit internal Flash memory with OTA firmware upgrade
SPI, UART and I2C as host interfaces
TCP/IP protocol stack (client/server) sockets applications
Network protocols (DHCP/DNS), including secure TLS stack
WSC (wireless simple configuration WPS)
Can operate completely host-less in most applications

We can notice that host interfaces allow direct connection to device I/Os and sensors through SPI, UART, I2C and ADC interfaces and can also operate completely host-less. A costly device is then removed from the BOM which can enable economic feasibility for an IoT, or IIoT edge device.

The Atmel® SmartConnect SAM W25 is a low-power Wi-Fi certified module which is currently used in industrial systems supporting applications such as Transportation, Aviation, Health Care, Energy or Lighting as well as in IoT like Home Appliance and Consumer Electronic. For all these applications, certification is a must have feature, but low-cost and ultra-low power are the economic and technical enablers.

From Eric Esteve from IPNEST

Freescale Semiconductor: The End of a Long Journey

Freescale Semiconductor: The End of a Long Journey
by Majeed Ahmad on 12-15-2015 at 7:00 am
Categories: EDA, Foundries

“You don’t argue with success,” said Paul Galvin back in 1949 at the creation of a new venture that would eventually become known as Motorola Semiconductor Products Sector. He was referring to how Daniel E. Noble, one of Motorola’s top managers, had persuaded him to set up a small electronics research facility in Phoenix, Arizona geared toward solid-state electronics.

Motorola Semiconductor Products Sector facility in Mesa, Arizona

Conservatives within Motorola had opposed the idea, calling it “Noble’s Resort” and arguing that whatever Noble wanted to do in Phoenix could be done at the headquarters in Chicago. Noble had Phoenix in mind for a number of reasons, including its reputation as a clean city and prospects of hiring qualified engineers and scientists.

Noble was a pioneer in his own right before he joined Motorola as director of research in 1940 after taking a year’s leave of absence from the University of Connecticut. He had developed the first FM mobile communications system for the specialized needs of the Connecticut State Police.

The timing of this move was impeccable. In the coming years, solid state electronics would unleash the power of semiconductors, thrusting Motorola’s semiconductor division into a key position in the rapidly evolving chip industry. The first major milestone in Motorola’s journey in the semiconductor industry came in 1952 when it licensed the design of transistor from Bell Laboratories.

Daniel Noble in front of the Motorola Research facility in Phoenix

For a start, Motorola’s semiconductor division began toying with the transistor as a replacement for bulky and expensive radio power supplies. Then, in 1955, Motorola launched its first mass-produced semiconductor product: a high-power germanium transistor for car radios. Motorola was a leading manufacturer of two-way mobile radios, and initially, it facilitated the company’s entry into the embryonic semiconductor industry.

By the late 1950s, Motorola’s semiconductor division had become a major player in transistors and diodes business. Apart from radio and communications, Motorola’s semiconductor business made a major impact in automobiles, where car makers like Ford used electronic components to build alternators and replaced generators during the 1960s.

Motorola’s first chip: a germanium-based high-power transistor

Motorola’s major break in the semiconductor business came with the launch of NASA’s celebrated Apollo 11 mission to the moon for whom the company supplied components for on-board tracking and communications equipment.

The radio transponder that relayed the first words from the moon to earth in July 1969 was based on a Motorola-supplied module that transmitted telemetry, tracking, voice communications and television signals between Earth and the moon. Motorola Semiconductor Products Sector was now a leading player in the nascent semiconductor industry.

It’s the first part of the three-part series of blogs about Freescale’s long journey. Stay tuned for more about how Motorola Semiconductor Products Sector became a formidable player in the chip industry and what led to its spin-off from the parent company in 2004.

December 14, 2015

Semiconductor capital spending consolidating

Semiconductor capital spending consolidating
by Bill Jewell on 12-14-2015 at 10:00 pm
Categories: Foundries

Shipments of semiconductor wafer fab equipment are expected to grow 2.5% in 2016 after 0.5% growth in 2015 according to the December forecast from Semiconductor Equipment and Materials International (SEMI). Gartner is more pessimistic, with its October forecast calling for fab equipment to decline 0.5% in 2015 and drop 2.5% in 2016. Gartner projects the market will return to growth in 2017 through 2019.

A drop in fab equipment shipments in 2016 appears almost certain based on the combined October data from SEMI and Semiconductor Equipment Association of Japan (SEAJ). Three-month-average semiconductor manufacturing equipment bookings dropped to $2.01 billion in October, the lowest level since February 2013. The book-to-bill ratio was 0.87, the lowest since 0.84 in November 2012. The semiconductor equipment market declined 13% in 2012 and dropped 16% in 2013. We at Semiconductor Intelligence believe the current downturn will not be as severe, with semiconductor equipment down 5% to 10% in 2016 and resuming growth in 2017.

Semiconductor capital expenditures (CapEx) for 2015 are projected to be $63.9 billion, down 1% from $64.6 billion in 2014, according to Gartner’s October forecast. Gartner expects CapEx will drop 3.3% in 2016 before picking up to 5% to 6% growth in 2017 through 2019. Semiconductor capital spending can be grouped into four major segments:
1. Foundry companies such as TSMC, GlobalFoundries and UMC.
2. Memory companies including Samsung, SK Hynix, Micron and IM Flash (Toshiba/SanDisk joint venture).
3. Intel, the largest semiconductor company and dominant microprocessor supplier.
4. Other – all other semiconductor companies (numbering in the hundreds).

The chart below shows SC CapEx from 2010 to 2015. Total CapEx is based on data from IC Insights (2010 to 2014) and Gartner (2015 estimate). CapEx for each segment is based on company data and estimates for 2015.

CapEx was $54 billion in 2010, more than double the $26 billion in 2009 during the semiconductor downturn. Capital spending increased 25% to $67 billion in 2011. CapEx dropped in 2012 and 2013 before resuming growth in 2014. The four segments show varying trends. The foundry segment has generally been on an upturn, from 21% of the total in 2010 to 25% in 2015. Memory increased from 31% in 2010 to 44% in 2015. The Memory segment should decline in 2016 as both Samsung and SK Hynix plan to cut CapEx. Intel’s portion increased from 10% in 2010 to 19% in 2012 and 2013 before dropping to 11% in 2015. The most significant trend is the Other segment dropping from 39% in 2010 to 19% in 2015. In dollars, Other CapEx dropped from $21 billion in 2010 to an estimated $10 billion in 2015.

What is behind the downward trend in Other CapEx? One major factor is almost all new semiconductor companies adopt a fabless strategy – focusing on design, marketing and sales and leaving manufacturing to outside foundries. Another key factor is many existing semiconductor companies are relying less on their own fabs and more on outside foundries. As shown in the table below, the top three spenders grew CapEx from 2010 to 2014, ranging from 22% for Samsung to 94% for Intel. In contrast, three major semiconductor companies with fabs have significantly reduced CapEx. Texas Instruments, STMicroelectronics and Renesas Electronics all spent over a billion on CapEx in either 2010 or 2011. Each company has been cutting CapEx significantly since, with 2014 versus 2010 down 60% for ST and Renesas and down 68% for TI.

[TABLE] border=”1″
|-
| style=”width: 155px” | CapEx, US$Billion
| style=”width: 53px” | 2010
| style=”width: 54px” | 2011
| style=”width: 48px” | 2012
| style=”width: 48px” | 2013
| style=”width: 54px” | 2014
| style=”width: 66px” | 2014/10
|-
| style=”width: 155px” | Top 3
| style=”width: 53px” |
| style=”width: 54px” |
| style=”width: 48px” |
| style=”width: 48px” |
| style=”width: 54px” |
| style=”width: 66px” |
|-
| style=”width: 155px” | Samsung
| style=”width: 53px” | 11.0
| style=”width: 54px” | 12.1
| style=”width: 48px” | 12.3
| style=”width: 48px” | 11.8
| style=”width: 54px” | 13.3
| style=”width: 66px” | +22%
|-
| style=”width: 155px” | Intel
| style=”width: 53px” | 5.2
| style=”width: 54px” | 10.8
| style=”width: 48px” | 11.0
| style=”width: 48px” | 10.7
| style=”width: 54px” | 10.1
| style=”width: 66px” | +94%
|-
| style=”width: 155px” | TSMC
| style=”width: 53px” | 5.9
| style=”width: 54px” | 7.3
| style=”width: 48px” | 8.3
| style=”width: 48px” | 9.7
| style=”width: 54px” | 9.5
| style=”width: 66px” | +61%
|-
| style=”width: 155px” | Others
| style=”width: 53px” |
| style=”width: 54px” |
| style=”width: 48px” |
| style=”width: 48px” |
| style=”width: 54px” |
| style=”width: 66px” |
|-
| style=”width: 155px” | Texas Instruments
| style=”width: 53px” | 1.20
| style=”width: 54px” | 0.82
| style=”width: 48px” | 0.55
| style=”width: 48px” | 0.41
| style=”width: 54px” | 0.39
| style=”width: 66px” | -68%
|-
| style=”width: 155px” | STMicroelectronics
| style=”width: 53px” | 1.24
| style=”width: 54px” | 1.28
| style=”width: 48px” | 1.11
| style=”width: 48px” | 0.53
| style=”width: 54px” | 0.50
| style=”width: 66px” | -60%
|-
| style=”width: 155px” | Renesas Electronics *
| style=”width: 53px” | 0.90
| style=”width: 54px” | 1.05
| style=”width: 48px” | 0.56
| style=”width: 48px” | 0.37
| style=”width: 54px” | 0.36
| style=”width: 66px” | -60%
|-
| colspan=”7″ style=”width: 479px” | * Renesas data for fiscal year ending March of following year
|-

Mergers and acquisitions are also leading to decreased CapEx in the Other segment. Combinations of semiconductor companies with fabs leads to a consolidation of manufacturing. The combined company will spend less on CapEx than the individual companies would have spent. In 2010, Renesas Technology and NEC Electronics merged to form Renesas Electronics. Renesas was originally formed by the merger of the semiconductor businesses of Hitachi and Mitsubishi Electric in 2003. Texas Instruments acquired National Semiconductor in 2011.

Recent M&A activity contributing to manufacturing consolidation and lower CapEx includes:
· NXP Semiconductors completed its acquisition of Freescale Semiconductor last week.
· ON Semiconductor agreed to acquire Fairchild Semiconductor last month (see our November post for details).
· Infineon Technologies acquired International Rectifier in January.
Other recent M&A activity does not affect CapEx since the acquired companies are fabless. This includes Avago’s pending acquisition of Broadcom and Intel’s proposed acquisition of Altera.

The trend is inevitable – new fabs will be built by companies with the economy of scale to justify an investment of $5 billion to $10 billion per fab. Thus memory companies, foundry companies and Intel will dominate CapEx. Other companies will continue to upgrade their existing fabs, but few (if any) will build new fabs.

December 14, 2015

Latest Crop of Energy Harvesting Chips Powers IoT Sensor Nodes

Latest Crop of Energy Harvesting Chips Powers IoT Sensor Nodes
by Tom Simon on 12-14-2015 at 12:00 pm
Categories: Arm, IoT, IP

Like death and taxes, changing batteries in remote sensor nodes and wireless IoT devices is often inevitable. Huge effort has been expended on reducing power consumption for battery operated devices, but the day always comes when the battery goes dead. Taking care of this can be as simple as popping open a battery cover and swapping batteries, or as dreadful as driving or hiking to countless remote locations to do the same. Furthermore, batteries are expensive and wasteful. Energy harvesting promises to reduce or eliminate this problem by using among other things light, heat and motion to power electronics.

Huge gains in rechargeable battery life and capacity have enabled enormous progress for wireless IoT devices, but to eliminate the need for wired recharge or battery replacement other energy sources need to be harnessed. The most common sources for harvesting energy are solar, thermal and vibration. Because each of these sources are not consistent and deliver varying voltage and current profiles, the energy from them needs to be stored in a reservoir such as a capacitor or battery. To capture all the energy possible there is a need to up-convert low voltages to that the power is useful. Lithium Polymer (LiPo) batteries need to be charged up to 4.2V and require specialized charging profiles to avoid overcharging or reduced battery life.

IC’s that run off of 5V and charge LiPo batteries have been around for quite a while, but efficient energy harvesting demands the ability to operate with inputs well below 1V. Cypress offers several chips for converting power from solar, vibration and thermal sources. Each of these chips is designed for somewhat different applications.

The MB39C831 works for charging LiPo batteries with its built in charge controller. It will also charge up super capacitors which can replace batteries in many low power devices. It can drive circuit loads with lower voltage inputs, such as when 5V is needed from a 3.7V nominal LiPo battery, or even lower input voltages. The important feature of this chip for working off of solar is what is called Maximum Power Point Tracking (MPPT). This ensures the load that the MB39C831 presents to a solar panel optimizes power transfer. Solar panels provide their highest voltage under no load. If a high current load, such as charging a battery, is applied, the current will spike but the voltage coming from the panel will collapse. This can cause large fluctuations and inefficient power transfer. MPPT seeks the optimal I/V point for the connected panel.

The MB39C811 is suited for driving circuits rather than charging batteries. Despite the absense of charge control circuitry, it is still useful because it can handle power sources that deliver AC currents. It has a low-loss rectifier bridge to handle AC sources like piezoelectric generators. The other advantage this chip has for piezoelectric is a high input voltage rating – up to 24V, with over voltage protection that keep the unit operating and allows 100mA operation.

Both of these chips have extremely low quiescent current (1.5uA and 41uA). It would not do to have the voltage converter draw down what limited power should be available for the application circuit. The MB39C831 can start operating at voltages as low as 0.35V, which helps squeeze every bit of power out of a solar panel on a cloudy day. Remote sensor nodes must have the ability to tolerate periodic lack of sun if necessary.

Spansion (merged wtih Cypress) posted an interesting summary of the needs for energy harvesting on their web site. It also discusses several evaluation boards they offer to help with system prototyping. These sensor node boards come with the above PMIC’s and an ARM Cortex M3 with a FM3 MCU. There is an RF module that is included to provide communication. The board also comes with an LCD display, temperature, light sensor and I2C for attaching other peripherals.

December 14, 2015June 14, 2019

Is That My Car on Fire?

Is That My Car on Fire?
by Daniel Payne on 12-14-2015 at 7:00 am
Categories: Automotive, EDA, Siemens EDA

I was kind of shocked when the service manager at our local VW dealership told me that one of the wires in the ignition system of my wife’s New Beetle had started to overheat, melting the insulation and becoming a safety hazard. Why didn’t a fuze just blow, protecting the wiring from overheating? We decided to quickly sell that car and made a mental note to double-check with Consumer’s Report before buying another vehicle with electrical issues. Most of us drive a car and often I just take it for granted that the electrical wiring is OK, expecting that some engineer has tested out the complex system before actually building production units.

Automotive companies can use a methodology of selecting wires that are larger than needed for the actual load, then building prototypes in order to measure currents and finally determine how to protect wires with a fuze. A more modern approach is to model and simulate the wiring for a car, although it’s a challenge when each make and model of car has a variety of trim packages and electrical options. Analyzing your automotive wiring during the design phase requires that you design different by:

Entering accurate load information for all devices that draw current (motor size, Volts, Amps)
Knowing the current flow through Engine Control Units (ECU’s)
Modeling the entire electrical architecture of the vehicle with component locations, relative temperatures, and the harness interconnect points
Have accurate models for the battery, fuses, wires and basic discrete devices

Engineers at Mentor Graphics have created automation tools to help automotive designers in this area, and a full analysis can be run that produces a table showing the recommended wire size (CSA max):

Knowing the proper wire sizes before production is a much smarter way than building a prototype and measuring because it saves both time and money. Recalls in the automotive industry can be quite costly and embarrassing to the brand.

Fuses should protect against accidental shorting, and there are three types of short circuit test cases:

If you build a physical prototype and run this type of short testing (aka Wire Smoke Testing) for all electrical loads in a car it will take lots of time and engineering effort. Then you have to check for fumes caused by wires that are over-loaded, heating up and burning the insulated coating.

Knowing the characteristics of wire fumes (blue line) and the fuse blow time (orange line), we can start to get a bit more scientific about wire sizing and fuses.

The Y-axis is Amps and the X-axis is Seconds. At point 1 the fuse will blow first at about 20 amps (orange curve), which is desirable. However, at about 8 amps show as point 2 the wire will be fuming before the fuse blows, and that’s a big problem.

Summary
Automotive wire harnesses must be designed for safety, and now there’s an automated approach that can be used during the design process to ensure that the current loads of each wire do not damage the insulation, and that the proper fuse values are selected, giving us electrical protection. Mentor Graphics has been involved with cabling design systems for many years now, and Mike Stamper has written a White Paper on this topic:

What are you smoking? Automating short circuit testing for automotive systems and harness design

Related blogs:

December 13, 2015

GSA Awards Dinner: Be Mindful!

GSA Awards Dinner: Be Mindful!
by Daniel Nenni on 12-13-2015 at 5:00 pm
Categories: Semiconductor Services

The GSA Awards Dinner is the semiconductor version of the Oscars. Lights, cameras, and there is certainly plenty of action. This year there were close to 1,500 people to celebrate the semiconductor industry and all of our accomplishments so it is a networker’s paradise. Quite a few people mentioned purchasing our new book and photos were requested so I’m enjoying another 15 minutes of fame but I digress…

First there was the Dr. Morris Chang Exemplary Leadership Award presented which I always look forward to. This year it went to Mr. Ming-Kai (MK) Tsai, Chairman and CEO of MediaTek which was well deserved. We included MediaTek in our book “Mobile Unleashed” so I know the full story of how MediaTek became one of the top fabless semiconductor companies. I have also worked with MediaTek over the years and if I had to pick one word to describe MK’s secret of success it would be “mindful”. He is mindful of his humble beginnings, he is mindful of his employees, he is mindful of his customers, his company, and his country. Again, this award was well deserved.

“I greatly appreciate receiving the highest honor from these undisputed experts on the semiconductor industry,” said Chairman Tsai. “I share this honor with my colleagues at MediaTek. This award validates the success so far of our mission to help connect the world’s next billion middle class people.”

The video tribute was also very good and I hope it is made public. One person on the video that stands out as both highly intelligent and incredibly articulate is of course Synopsys Chairman Aart de Geus. And if you have ever spoken to him in person you will know that this is his normal speech pattern. EDA is fortunate to have Aart, absolutely.

You can see the rest of the award recipients HERE.

Next was the keynote which I always look forward to but unfortunately this one was a bit unsettling, for me anyway. General Stan McChrystal, Former Commander of U.S. and International Forces and Author of Best-Sellers Team of Teams and My Share of the Task, talked about integrating intelligence and operations which revolutionized the way counter-terrorism operations are approached. The General used the hunt and subsequent death of Al-Qaeda leader Abu Musab al-Zarqawi as an example. The US Military hunted him down and dropped two 500lb bombs on a “safe house” where he was meeting with his spiritual adviser.

Naturally the following dinner conversation gravitated towards domestic terrorism and for that I also have one word and that is “mindful”. Politicians will not solve this problem. “Eye for an eye” responses will not solve this problem. Arming our citizens with handguns will not solve this problem. Building walls literally or figuratively will not solve this problem. How do people amass weapons, high capacity cartridges, ammunition, bomb making materials, Kevlar vests and leggings without someone knowing? Please be mindful and remember this is nothing new:

14 dead, 21 wounded: San Bernardino, Calif.
3 dead; 9 injured, Colorado Springs, Colo.
9 dead, 9 injured: Roseburg, Ore.
5 dead, 3 wounded: Chattanooga, Tenn.
9 dead: Charleston, S.C.
6 dead, 7 wounded: Isla Vista, Calif.
3 killed; 16 injured: Ft. Hood, Texas
12 killed, 3 injured: Washington, D.C.
5 killed: Santa Monica, Calif.
27 killed, one injured: Newtown, Conn.
3 dead, 4 injured: Brookfield, Wis.
6 killed, 2 injured: Minneapolis, Minn.
6 killed, 3 injured: Oak Creek, Wis.
12 killed, 58 injured: Aurora, Colo.
7 killed, 3 injured: Oakland, Calif
8 killed, 1 injured: Seal Beach, Calif.
6 killed, 11 injured: Tucson, Ariz.
8 killed, 2 injured: Manchester, Conn.
3 killed, 3 wounded: Huntsville, Ala.
13 killed, 32 injured: Ft. Hood, Texas
13 killed, 4 injured: Binghamton, N.Y.
5 killed, 16 injured: Dekalb, Ill.
8 killed, 4 injured: Omaha, Nebraska
32 killed, 17 injured: Blacksburg, Va.
5 killed, 4 injured: Salt Lake City
5 killed, 5 injured: Nickel Mines, Pa.
6 dead: Goleta, Calif.
9 killed, 7 injured: Red Lake, Minn.
5 killed, 9 injured: Meridian, Miss.
3 killed: Tucson, Arizona
2 killed, 13 injured: Santee, Calif.
7 killed: Wakefield, Mass.
7 killed: Honolulu, Hawaii
7 killed, 7 injured: Fort Worth, Texas
9 killed, 12 injured: Atlanta, Georgia
13 killed, 24 injured: Columbine, Colo.
5 killed, 10 injured: Jonesboro, Ark.
6 killed, 19 injured: Garden City, N.Y.
8 killed, 6 injured: San Francisco, Calif.
4 killed, 10 wounded: Olivehurst, Calif.
4 killed, 2 injured: Iowa City, Iowa
22 killed, 20 wounded: Killeen, Texas
10 killed, 4 wounded: Jacksonville, Fla.
5 killed, 29 injured; Stockton, Calif.
14 killed, 6 wounded: Edmond, Okla.
21 killed, 19 wounded: San Ysidro, Calif.

December 13, 2015June 14, 2019

Palladium Moves Power (and Temperature) Modeling to the System Level

Palladium Moves Power (and Temperature) Modeling to the System Level
by Bernard Murphy on 12-13-2015 at 12:00 pm
Categories: Cadence, EDA

I had a debate with Steve Carlson of Cadence earlier in the year at the EDPS conference on whether there were really any truly effective solutions for doing power estimation in emulation. I thought there weren’t and he said I was wrong. After attending the Cadence front-end summit last week, I have to admit he has a point.

First, who cares? Why is power estimation in emulation important? Simple – power varies widely based on activity and many would agree that software load is the most important factor in determining power for a given architecture. The problem is that all standard (non-emulation-based) approaches to determining power are limited to effectively tiny samples of activity, delivering little islands of well-understood power in an ocean of otherwise unknown power behavior. Of course designers and architects work hard to find “representative” cases but this is more margining than science, with all the evils that margining brings. And even then, finding peak power problems has been effectively impossible (finding needles in a haystack) until you get to silicon running real applications. Peak power is very important because it drives temperature spikes and that can lead to system failure or even silicon failure. In fact, analyzing temperature has become so important that P-T-P (performance-temperature-power) is becoming more important that PPA (performance-power-area) in many contexts.

The obvious way to get more realistic windows of activity is through emulation but I thought I saw a problem. Power estimation needs activity data on every node but an emulator becomes very slow if it has to dump all that data; the promised speedup would disappear in data dumping and you still wouldn’t be able run realistic loads. I was wrong. Palladium™ is able to dump just a subset of the nodes (registers) and uses probabilistic modeling through combinational logic to get a reasonable estimate of activity in between. Also, Palladium connects natively through the PHY (physical access interface) to Joules, the Cadence power estimation solution, so all that work in going through an FSDB (or similar) step is avoided. This speeds turnaround time from days to hours on big jobs.

The proof is in real tests. Cadence has demonstrated running the AnTuTu test-suite, a widely-used benchmark to grade Android-based phones on many features. Since this is one of the more comprehensive system tests available today for a smartphone, their ability to run it on an emulation model of the device and produce power and temperature profiles is testament to the practical value of the Palladium + Joules solution.

Of course emulation isn’t all you need to design for and debug power. It provides good (approximate) guidance on power across realistic software loads and can identify peak power windows which need special attention in design. You can then take that into Incisive™ simulation with Joules™ for detailed analysis with increased accuracy in narrow windows (those peak power cases, for example) and then into detailed power and thermal analysis at the implementation level using Voltus™, Sigrity™ and PowerDC™. The whole flow together provides successive refinement from realistic software loads all the way down to final implementation, spanning the full range of factors that influence power and temperature.

So my apologies to Steve – this really is about the best you can do in design, short of trial-and-error on multiple silicon respins. One or two respins may be unavoidable these days, but you need this solution to make sure you keep it to no more than one or two.

You can read more about Palladium and Joules power estimation HERE.

My Life at Fairchild – 1979 Part 2

My Life at Fairchild – 1979 Part 2
by Mark Rioux on 12-13-2015 at 7:00 am
Categories: Foundries

To pick up on my last post, I wanted to expand a bit on my duties and experiences back in 1979 in the 3″ Diffusion area of fab.

I am a morning person so I was usually at work between 6am – 7am. I would immediately go into fab to check on my engineering hold table and speak with the production operators to get a sense of the problems they were having. This helped me to plan my day. The average wafer lot size was 50 wfs/lot, not 25 wfs since the wafers were much smaller than they are today. Each lot on hold would have a completed engineering hold form that would detail why the lot was on hold. My engineering technician (a nice lady named Viola Brann) and I would then proceed to diagnose and disposition this material. This often required measuring oxide thicknesses and junction depths, and processing the lots through diffusion repair cycles to get them back into the production flow. We would later review the end-of-line parametric data on each lot to get feedback on the effectiveness of the repair cycle.

In stark contrast to the advanced metrology equipment of today, we had only very crude methods for assessing process performance. For example, to measure the thickness of silicon dioxide, we would take a Q Tip, dip the wooden end into a straight HF acid bath (with acid gloves on of course), and place one drop on the backside of the wafer to be measured. The HF would etch the oxide film very fast, leaving a colorful fringe pattern consisting of the colors of the rainbow. We would then estimate the oxide thickness looking up the last color present in the color chart table (reference: Semiconductor Technology Handbook – R.A Blanchard and O.D. Trapp) as shown below. If the surface oxide was blue in color and the fringe pattern showed one other blue cycle present, we would estimate the oxide thickness to be approximately 0.31um, or 3100A.

It didn’t take too long to be able to estimate the oxide thickness by just looking at the color. Of course the measurement accuracy (+/-150A) left something to be desired.

The technique used to measure the silicon dopant junction depths was just slightly more refined but extremely crude by today’s standards. Today we use SIMS analysis to measure dopant concentration into the silicon surface. In 1979, we used the lap and polish technique. Basically, we would cut off a small piece of the wafer using a diamond tipped scribe, mount it onto a cylindrical polishing block (using wax) that had a slightly sloped 4 degree bevel surface. We would then invert the sample and polish the mounted silicon using a diamond slurry until the 4 degree bevel had transferred to the silicon surface. Once the polishing was complete, a chemical stain was applied which served to stain the p-type regions (those containing high boron concentration) dark while leaving the n-type junctions light.

After the stain was applied, a cover glass was placed over the silicon sample and a sodium lamp (wavelength ~ 0.6um) was used to generate incident light creating a fringe pattern with each fringe separated by 0.3um. We would then inspect the beveled sample using a long working distance microscope through the cover glass and count the number of fringes from the silicon surface to the emitter-base (N-P) junction and then to the base-epi (P-N) junction. So, if we counted 7 fringes to the base-collector junction, that corresponded to a junction depth of 7 x 0.3um = 2.1um. If I remember correctly, most of our processes had junctions depths in the range of 0.9um to 4.2um+. The technique worked very well. One big drawback was the damage done to the product wafer in scribing off a piece for sectioning. You can imagine the silicon particles generated during that procedure.

Viola and I would often have to process the hold lots through furnace repair cycles ourselves as the operators were busy processing production material. Actually I greatly valued the direct “Hands-On” experience because it kept me very much in tune with all the duties that an operator had to handle. I developed a deep respect for their job and it kept me humble. One time, while sliding a load of wafers into the emitter diffusion furnace, I slipped and accidentally drove the quartz push rod into the first 10 wafers in the furnace, breaking all the wafers! Needless to say, the operators never let me forget that one.

I would come out of the fab at 9:00am for morning break in the cafeteria. We would sit at our usual table with our co-workers from the Photo area, Joan Denyer, Sheila Proctor, Rolf Dries, Alicia Eaton and Ron Gagne to name just a few. Over coffee, we would talk about almost anything. The workers in Photo were always blaming the workers in Diffusion for process problems and vice-versa….but it was all in good fun.

One last thing. The absolutely most valuable tool I have from my initial year at Fairchild is my own Semiconductor Technology Handbook (see photo below):

I first received this handbook during my initial training back in the summer of 1979 and still have it today. As you can tell it is well worn as I still use it on occasion today.

More to follow….

Low Power LTE for IoT: The Webinar from CEVA

Low Power LTE for IoT: The Webinar from CEVA
by Eric Esteve on 12-13-2015 at 12:00 am
Categories: Ceva, IP

Talking about “connected devices”, we specify any system from high-end smartphones to the simplest low-cost tag, as far as this system will be wirelessly connected. IoT are by definition connected systems, and represent a significant portion of connected devices. By 2020, ABI Research predicts that there will be more than 45 billion connected devices worldwide. More than half of these devices will incorporate multiple standards in the same device, such as Wi-Fi, 802.15.4g, GNSS and cellular, including the upcoming ultra- low data rate LTE MTC Cat-M.

Some application, such as wearable, will only require a battery life of a few days, but others such as asset trackers will demand a battery life of 5-10 years. For system designers, addressing wearable related challenges will be completely different than designing an asset tracker. As of today, some wearable devices are considered as fashionable gadget, the end user accepting to pay sometimes more than for a mainstream smartphone even if the battery life is only a day or so. The designer is free to define a complex architecture, supporting multiple wireless communication standards in the same device, as soon as the end product is feature-rich enough to attract the buyer. Final cost or power consumption are important parameters, but if the system is attractive enough to justify a buying act, neither high cost nor poor battery life will prevent to develop the system.

At the other side of the scope, if you define asset tracker system specification, you may end up to count every cent as you need to meet very stringent cost requirement and the battery life is expected to last several year instead of days. It’s clear that one wireless communication standard can’t fit the demand coming from so different applications. But how selecting the right wireless standard in respect with your system needs?

This webinar from CEVA’s experts will precisely address this question. Starting by an overview and market trends in connectivity for IoT and Machine to Machine (M2M), the webinar will introduce to the latest Low Data Rate LTE standards, including LTE Cat-1 and LTE Cat-0. There is a momentum behind LTE Cat-1 and LTE Cat-0 for IoT applications that don’t need the higher bandwidth rates delivered by the version of LTE (known as Cat-4) used by today’s smartphones. CAT-1 is a 3GPP-defined LTE specification that has a maximum downlink speed of 10Mbps, upload rate of 5Mbps, and is more cost- and power-efficient than Cat-4. CAT-0 will allow for even lower bandwidth (with a maximum throughput of 1Mbps) and more power-efficient LTE connectivity in the future.

CEVA’s expert will emphasize the importance of the processor architecture to efficiently enable multimode connectivity solutions. Finally, they will describe how implementing actual solutions for various IoT and M2M use cases using the latest communication DSP.

Who should attend? If you are a curious engineer or marketer, you certainly could attend. But you definitely should attend if you are communication and systems engineers targeting multimode applications requiring emerging cellular protocols such as LTE MTC Cat-1, Cat-0 or Cat-M, the Low Power Wide Area Network (LPWAN) standards such as Lora, SigFox and Ingenu, or any other IoT-related communication standards, including Wi-Fi 802.11n, PLC, 802.15.4g, ZigBee/Thread, GNSS, NB-IoT and Wi-Fi 802.11ah.

IoT Innovation Enters Public Infrastructure

IoT Innovation Enters Public Infrastructure
by Pawan Fangaria on 12-11-2015 at 4:00 pm
Categories: IoT

I often hear about IoT being overhyped on what it needs and what it can actually provide. However, in my view, truly there seems to be a large potential in IoT enabled technologies and applications which we will see over upcoming years in the near future. It will gradually proliferate into various segments of our environment through automation and integration of devices with internet and semiconductor devices will be the driver.

Talking about the cost of IoT systems and expecting them to be cheaply available; think about the huge money spent on public infrastructure by the governments and public institutions around the world. Imagine how the use of IoT systems can save a significant portion of that public fund, yet make the public infrastructure more efficient, productive, safe, secure and easily manageable with little effort and effective use of resources.

The story has begun with Los Angeles being the world’s first city to have smart poles for street lighting that will serve dual purpose; smart lighting and smart data coverage with 4G LTE wireless technology. Ericsson has developed 4G LTE small cell technology that can be fitted on the light poles and can host mobile network operator equipment.

It’s a joint effort by Royal Philips (a global leader in lighting) and Ericsson. Royal Philipswill equip their LED light poles with fully integrated 4G LTE wireless technology from Ericsson and deploy them around the streets of LA. One can imagine how productive and efficient this collaborative technology will be. It will connect all light poles, reduce network tower clutter, provide better broadband connectivity and better network performance in dense urban localities.

Leveraging the street light poles for data traffic management will be a boon for IoT in smart cities where the volume of data is expected to grow multi-fold. The smart poles with 4G LTE will support increasing requirement of capacity to handle large data as well as efficient management of the data traffic without signal dropout.

On the other hand, the public lighting infrastructure is being infused with intelligence that can make the overall lighting system ‘smart’ and energy efficient. Also the real estate and infrastructure that’s already in place is now made smart to earn revenue by providing various network services.

The connected smart lighting system can be controlled remotely and managed very efficiently to save energy. The light levels can be adjusted according to the need in different streets from pole to pole. The lighting can be scheduled at times of the day, days of the week, and seasons and so on for different areas of the city. In fact, in the spirit of future IoT, the poles also can have sensors to detect traffic on the road and accordingly determine to keep the lights on or off.

The street lights in LA are already being controlled through a remote light management system. The Royal Philips CityTouch system connects each light point and uses mobile and cloud-based technologies to monitor and control street lights. The chip enabled light fixture in a smart pole can identify any fault in its light and report instantly to the control office through the connected system for the light to be repaired in time. Using this system uninterrupted and better lighting is provided at reduced maintenance cost and energy expense.

The system has a web based visualization tool that accurately monitors energy consumption and status of each light and reports the overall status in charts and diagrams. The report can also be used in planning the overall lighting system for the city. Here is a quick video of the CityTouch connect –

The CityTouch workflow is another web based asset management tool that provides complete visibility about the lighting assets and workflow for efficient decision making. It provides map based navigation to automate operations management. After reviewing appropriate level of details, fault reports can be created, work orders made, and distributed to maintenance crew for timely repair or installation. Here is a quick video on the CityTouch workflow system –

This is a great time to make our world smart. We are yet to see the unknown potential of IoT enabled systems in our overall ecosystem.

Pawan Kumar Fangaria
Founder & President at www.fangarias.com