To pick up on my last post, I wanted to expand a bit on my duties and experiences back in 1979 in the 3″ Diffusion area of fab.
I am a morning person so I was usually at work between 6am – 7am. I would immediately go into fab to check on my engineering hold table and speak with the production operators to get a sense of the problems they were having. This helped me to plan my day. The average wafer lot size was 50 wfs/lot, not 25 wfs since the wafers were much smaller than they are today. Each lot on hold would have a completed engineering hold form that would detail why the lot was on hold. My engineering technician (a nice lady named Viola Brann) and I would then proceed to diagnose and disposition this material. This often required measuring oxide thicknesses and junction depths, and processing the lots through diffusion repair cycles to get them back into the production flow. We would later review the end-of-line parametric data on each lot to get feedback on the effectiveness of the repair cycle.
In stark contrast to the advanced metrology equipment of today, we had only very crude methods for assessing process performance. For example, to measure the thickness of silicon dioxide, we would take a Q Tip, dip the wooden end into a straight HF acid bath (with acid gloves on of course), and place one drop on the backside of the wafer to be measured. The HF would etch the oxide film very fast, leaving a colorful fringe pattern consisting of the colors of the rainbow. We would then estimate the oxide thickness looking up the last color present in the color chart table (reference: Semiconductor Technology Handbook – R.A Blanchard and O.D. Trapp) as shown below. If the surface oxide was blue in color and the fringe pattern showed one other blue cycle present, we would estimate the oxide thickness to be approximately 0.31um, or 3100A.
It didn’t take too long to be able to estimate the oxide thickness by just looking at the color. Of course the measurement accuracy (+/-150A) left something to be desired.
The technique used to measure the silicon dopant junction depths was just slightly more refined but extremely crude by today’s standards. Today we use SIMS analysis to measure dopant concentration into the silicon surface. In 1979, we used the lap and polish technique. Basically, we would cut off a small piece of the wafer using a diamond tipped scribe, mount it onto a cylindrical polishing block (using wax) that had a slightly sloped 4 degree bevel surface. We would then invert the sample and polish the mounted silicon using a diamond slurry until the 4 degree bevel had transferred to the silicon surface. Once the polishing was complete, a chemical stain was applied which served to stain the p-type regions (those containing high boron concentration) dark while leaving the n-type junctions light.
After the stain was applied, a cover glass was placed over the silicon sample and a sodium lamp (wavelength ~ 0.6um) was used to generate incident light creating a fringe pattern with each fringe separated by 0.3um. We would then inspect the beveled sample using a long working distance microscope through the cover glass and count the number of fringes from the silicon surface to the emitter-base (N-P) junction and then to the base-epi (P-N) junction. So, if we counted 7 fringes to the base-collector junction, that corresponded to a junction depth of 7 x 0.3um = 2.1um. If I remember correctly, most of our processes had junctions depths in the range of 0.9um to 4.2um+. The technique worked very well. One big drawback was the damage done to the product wafer in scribing off a piece for sectioning. You can imagine the silicon particles generated during that procedure.
Viola and I would often have to process the hold lots through furnace repair cycles ourselves as the operators were busy processing production material. Actually I greatly valued the direct “Hands-On” experience because it kept me very much in tune with all the duties that an operator had to handle. I developed a deep respect for their job and it kept me humble. One time, while sliding a load of wafers into the emitter diffusion furnace, I slipped and accidentally drove the quartz push rod into the first 10 wafers in the furnace, breaking all the wafers! Needless to say, the operators never let me forget that one.
I would come out of the fab at 9:00am for morning break in the cafeteria. We would sit at our usual table with our co-workers from the Photo area, Joan Denyer, Sheila Proctor, Rolf Dries, Alicia Eaton and Ron Gagne to name just a few. Over coffee, we would talk about almost anything. The workers in Photo were always blaming the workers in Diffusion for process problems and vice-versa….but it was all in good fun.
One last thing. The absolutely most valuable tool I have from my initial year at Fairchild is my own Semiconductor Technology Handbook (see photo below):
I first received this handbook during my initial training back in the summer of 1979 and still have it today. As you can tell it is well worn as I still use it on occasion today.
More to follow….
TSMC CoWoS versus Intel EMIB Semiconductor Packaging