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Variation Aware FinFETs are Critical!

Variation Aware FinFETs are Critical!
by Daniel Nenni on 12-18-2015 at 4:00 pm
Categories: EDA, FinFET

As I mentioned in “EDA Dead Pool” acquisitions in our industry will continue at a rapid pace. The latest victim is 10 year old French company Infiniscale who was recently purchased by Silvaco. This was more of a “let’s put your product through our massive sales and support channel” kind of deal so it will be 1 + 1 = 3 accretive for sure. Plus, variation aware tools use SPICE licenses so it makes perfect sense for a company like Silvaco (SmartSPICE) to go into variation, absolutely.


“The increased variability associated with advanced processes result in increased yield risks that designers need to mitigate while they strive to meet aggressive power, performance and area goals,” said Infiniscale’s Chief Executive Officer Dr. Firas Mohamed. “Infiniscale invented a second generation of Monte Carlo analyses that helps designers meet these increasingly stringent goals, with a user-friendly variation-aware design methodology. We are proud of the opportunity to be part of Silvaco’s legacy of technology leadership and are deeply committed to working together to continue providing innovative solutions for our customers and the design community.”

“There is good synergy between Silvaco and Infiniscale, and this acquisition further advances Silvaco’s growth initiatives to provide our customers with a robust TCAD-to-signoff set of design tools,” said Silvaco’s Chief Executive Officer David L. Dutton. “Infiniscale’s impressive variation analyses technology strengthens Silvaco’s SPICE portfolio, which includes SmartSpice circuit simulator, EM/IR/thermal analysis, standard cell and memory characterization, bringing unique accuracy, performance and economic value to support our customers’ leading-edge IC designs. This acquisition increases our presence in the European market as the Infiniscale team will join our Grenoble, France site.”

There are four companies that play in the variation aware tool space:Solido Design, MunEDA, ProPlus, and Infiniscale. Notice none of the big four EDA companies (Synopsys, Cadence, Mentor, Ansys) compete in this area? Not yet anyway, so expect more acquisitions before #53DAC for sure.

What are the specific variation challenges FinFET designers face you ask? Great question, let’s start with PVT Corner Design at 16nm and 10nm. There are literally tens of thousands of simulation combinations to consider. You can either (1) simulate them all over a period of months with thousands of SPICE licenses or (2) you can guess at which ones to simulate or (3) you can use a variation tool to statistically tell you which ones you should care about.

Next is High-sigma Monte Carlo design. For SRAM and Standard Cells this is a no brainer since they are repeated thousands and thousands of times throughout designs and yield is extremely critical. Before FinFETs, designers would simulate to 3-sigma and extrapolate to High-sigma. If you try that with FinFETs either you will not yield or your design margins will not be competitive. Using HMC you can now do a year’s worth of simulations with a handful of SPICE licenses in a matter of hours or maybe days to get you up to 6 or 7 sigma with SPICE accuracy. Seriously, I have seen it done and know by experience that the top foundries and their biggest customers use variation tools for 16nm and 10nm SRAM and complex standard cells, absolutely.

Also Read: EDA Mergers and Acquisitions Wiki

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IEDM Blogs – Part 3 – Global Foundries 22FDX Briefing

IEDM Blogs – Part 3 – Global Foundries 22FDX Briefing
by Scotten Jones on 12-18-2015 at 12:00 pm
Categories: FD-SOI, Foundries, GlobalFoundries

While I was at IEDM I had an opportunity to sit down with Subramani (Subi) Kengeri, the Vice President, General Management, CMOS Platforms Business Unit and Jason Gorss from corporate marketing at Global Foundries (GF) for a briefing on GF’s new 22FDX process technology.

Subi told me his background was in design but that he is now the business unit head for Fab 1 in Dresden. The 22FDX platform is being developed to run in Dresden and will be the next generation process for that fab (Dresden most advanced process is currently a 28nm bulk planar process).

22FDX is targeted at mobile computing and the mobile requirements for cost, performance and power. Applications like the internet of things (IOT) will need ~$1 ASPs. Some of the key requirements include:

  • Cost.
  • Ultra-low power.
  • Security and privacy.
  • Always on sensors and modules.
  • Dynamic performance and leakage – low leakage for always-on and performance for short bursts.

Multi-patterning is driving up wafer costs. A design for a leading edge FinFET process costs $50-$80 million dollars for the design. To get a reasonable return at a 20% market share you are looking at ~$400 million dollars out of a market with a TAM of $2 to $3 billion dollars. Not many opportunities are that large.

FinFETs are used for the highest performance applications but they consume slightly higher power due to 3D capacitance. For everything else planar FDSOI is the best.

The goal with 22FDX was to maximize the shrink from 28nm, while minimizing double patterning. 22FDX can provide “FinFET like performance” while operating down to 0.4 volts. It is the only technology known today that can operate at that low of a voltage. The technology also offers software tuning of the body bias so that post silicon tuning can be used to dial in performance and recover weak SRAM bits.

My background is in process technology and I was very interested to dig in to how this process is designed. As previously stated GF wanted to minimize multipatterning.

  • The front-end-of-line (FEOL) transistor is licensed from ST Micro’s 14nm FDSOI process.
  • Middle-of-line (MOL) includes 2 metal layers (M1 and M2) with double patterning by litho-etch-litho-etch (LE2).
  • Back-end-of-line (BEOL) is all single patterned to keep down costs.

The process is basically a 14nm FEOL with a 22nm BEOL to minimize costs.

There are four versions of the process:
[LIST=1]

  • 22FDX-ulp – ultra-low power – special SRAM and doping optimization.
  • 22FDX-uhp – ultra-high performance – BEOL stack optimization and MIM capacitors.
  • 22FDX-ull – ultra-low leakage – adds dual gate oxide to create a thick oxide ultra-low leakage device.
  • 22FDX-rfa – RF & analog – passive devices and ultra-thick metal.

    The 22FDX process offers a wider range of threshold voltage/leakage options than any other known technology. As I will discuss in my forthcoming blog on Greg Yeric’s plenary talk, options on voltage/leakage are very important to designers.

    The use of body biasing in this technology is a key to its performance. Forward biasing the body (FBB) drives up performance and reverse biasing the body (RBB) provides the lowest leakage. FBB and RBB can be done on a block by block basis on a single die. For example, an IOT device might have an always on “watchdog” processor in a RBB block to minimize power. The rest of the blocks on the chip could be kept off until needed. Additional blocks could include a FBB processor block for high performance and an integrated RF block for off-chip communication. This unique feature of 22FDX allows the integration onto one chip of functions that would typically require separate chips built with different technologies.

    22FDX is 50% faster and 18% lower power than a 28nm high-k metal gate (HKMG) technology or 47% lower power at the same frequency. At 0.4 volts an ARM core can run at 520MHz while consuming 92% less power! The RF performance is good enough to implement WiFi or Bluetooth without the need for an external power amplifier.

    In terms of the schedule, design kits for 22FDX are available now and risk production is scheduled to begin mid-2016.

    Long term FDSOI can scale down to 10nm but they haven’t decided on the exact “node” for a follow on process. The 22FDX is kind of an intermediate process between 28nm and 14nm with better performance than 28nm and lower cost than 14nm. Presumably the next version will be positioned between the 14nm and 10nm FinFETs for performance and cost. Subi said the next generation process would likely be in Dresden.

    You can view the Global Foundries 22FDX presentation HERE.

    Also Read: IEDM Blogs – Part 2 – Memory Short Course

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    Mass customization coming to MEMS?

    Mass customization coming to MEMS?
    by Don Dingee on 12-18-2015 at 10:00 am
    Categories: EDA, IoT, Siemens EDA, Tanner EDA

    With the industry abuzz about the Apple purchase of a Maxim Integrated fab as a potential R&D facility for MEMS design, it begs the question: is creating a MEMS device that easy?

    MEMS technology is approaching the same fork in the road where digital design encountered LSI four decades earlier. Continue reading “Mass customization coming to MEMS?”

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    Slinging Stones at the Data Center Semi Goliaths

    Slinging Stones at the Data Center Semi Goliaths
    by Maury Wood on 12-18-2015 at 7:00 am
    Categories: Arm, IP

    For those not aware, there is quite a battle brewing in data center wired communication segment (across which most wireless data traffic traverses). A primary impetus driving the competitive positioning is the recent commercial availability of single lane 25 Gbps serdes (serializer / deserializer) channels in 28 nm CMOS from several suppliers.

    Most mainstream data centers today use 1 Gbps Ethernet over copper (1000Base-T) to interconnect server nodes to top of rack (TOR) aggregation or leaf switches, with 10 GbE over copper (10GBase-T) an upgrade path that has seen relatively slow industry adoption. For higher bandwidth uplinks between aggregation and core switches, four 10 GbE lanes on a quad SFP (QSFP) optical link provides 40 Gbps of connectivity, consuming four switch ports on both ends. Using the same approach on a larger QSFP28 optical connector, ten 10 GbE lanes provides 100 Gbps uplink connectivity to the data center core spine switches.

    By contrast, the 25 Gigabit Ethernet Consortium specification, driven by Broadcom, Cisco, Dell, Mellanox and others, 50 GbE connectivity requires only two ports, and 100 GbE connectivity requires only four ports, enabling very attractive total port ownership costs (including reduced cable costs), likely sufficient to further stunt 10 GbE uptake. Striking about this paradigm shift is that Broadcom, the 800 pound gorilla of the ethernet chip world with $8.4B in 2014 revenue, is seeing a fresh challenge to its switch dominance by much smaller companies, while its traditional 1 GbE chip competitors, Marvell and Realtek, are relative “no shows” in the race to field 25 and 50 GbE switch ports using 25 Gbps serdes technology.

    Cavium, one of the new tigers in data center semiconductors, is an impressive example. Cavium acquired Xpliant for less than $100M last year, and introduced the CNX880XX family to the market quickly thereafter. Maximum Xpliant Ethernet bandwidth is 3.2 Tbps across 128 ports (using 25 Gbps serdes), same as Broadcom’s flagship Tomahawk switch chip. Cavium’s programmable Xpliant Packet Architecture is claimed to be friendlier to Software Defined Networking specifications such as OpenFlow.

    Cavium is also offering a very competitive ARMv8 server processor family, the ThunderX, with up to 48 custom cores, dual socket coherency, and many other Xeon-class server processor features. Intel announced the 14 nm Xeon D SoC processor family at least in part as a competitive response to ThunderX and Applied Micro’s X-Gene multi-core ARMv8 server processor. Cavium also markets impressive embedded processor, security processor and network processor product portfolios. All this innovation from a company with $420M run-rate annualized revenue.

    This theme of undaunted ferocity repeats with Mellanox (current annualized revenue less than $800M). They are best known for very low port latency (down to 90 nsec) InfiniBand adapters and switches for both processor and storage connectivity. InfiniBand is more prevalent than Ethernet in high performance computing applications such as supercomputers and high frequency trading machines. Their latest Enhanced Data Rate products also use 25 Gbps serdes, with as many as 144 port instantiations per chip, same as Broadcom’s latest BCM88770 “FE3600” Ethernet switch fabric device, providing 3.6 Tbps of packet bandwidth.

    Mellanox is gaining share in the data center Ethernet segment as well, with their eighth generation 3.2 Tbps class Spectrum switch chip. To put this into perspective, mighty Intel’s highest performance Ethernet switch chip, the FM6764, offers 640 Gbps port bandwidth with 400 nsec cut-through latency. Intel reported $56B in 2014 revenue, making even the merged Broadcom+Avago operation seem small by comparison. Intel recently announced their Omni-Path Architecture, a new data center routing fabric designed to address scalability and other limitations associated with InfiniBand, and featuring 25 Gbps serdes. While this announcement raises the stakes for Mellanox, most markets generally want to see at least two competitive alternatives, and realistically it will take the Omni-Path ecosystem several years to become firmly established.

    Cloud computing data centers equipment is one of the fastest growing semiconductor application segments today and into the foreseeable future. Despite the ongoing and unprecedented level of consolidation in microchip industry, it is exciting to see small dynamic companies like Cavium and Mellanox present fresh challenges for established goliaths such as Broadcom and Intel.

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    Hyperloop: Faster Than the Shinkansen

    Hyperloop: Faster Than the Shinkansen
    by Daniel Payne on 12-17-2015 at 4:00 pm
    Categories: General

    In 1987 I made my first trip to Japan for business, then rode in my first high-speed train on the fabled Shinkansen (aka bullet train) traveling up to 200 mph on the way from Tokyo to Kyoto. Compared to the USA, our engineering friends in Japan have the most futuristic high-speed trains in the world. Today there’ s talk about another high-speed traveling mode similar to a train but running inside of tubes, dubbed the Hyperloop by Elon Musk, the billionaire made famous for SpaceX, Tesla Motors and SolarCity. The planned top speed for the Hyperloop is a staggering 760 mph, which is faster than commercial jets.

    Musk created an open source design challenge back in 2013 to create a 28 passenger pod that travels through tubes, powered by solar, and costing only $20 for a ticket from LA to SFO, while taking just $6 billion to construct. Two startups are making a quest for this project: Hyperloop Transportation Technologies (HTT) and Hyperloop Technologies Inc (HTI). At the start of 2015 Musk added plans to build a Hyperloop test track and announced a contest in 2016 where you need to build a half-scale pod. There are some 318 teams from around the world participating with pod designs.

    HTT won’t spend their efforts on the 2016 contest and they pay their engineers equity in exchange for 10 hours per week, allowing them to keep their day jobs in high tech. Ansys has partnered with HTT to run simulations of the fluid dynamics required for the Hyperloop concept. HTT has plans to build their own Hyperloop in Quay Valley, California with pod speeds up to 300 mph, quite a bit short of the 760 mph dream goal.


    HTT Concept

    HTI is raising some $80 million in its next round of growth, and they are partnered with China Railway International USA. So there are two companies kind of racing to implement the first Hyperloop system.


    HTI’s levitation ring

    Concerns about Hyperloop include:

    • Safety
    • Costs
    • Passenger experience in a confined pod
    • Infrastructure

    At the University of Illinois in the MechSE curriculum you can study the Hyperloop for credit, so Universities around the globe are getting energized with the entire high-speed transportation concept.

    I’m all for the private sector innovating and developing travel concepts like the Hyperloop, however I’d be upset if our Federal or State governments started throwing my taxpayer dollars at such a high risk venture. I was quite skeptical of the concept of powering a transportation system of this size and weight using only solar power, and then keeping the tubes perfectly aligned across any real geography, especially earthquake-prone California. The Hyperloop almost reminds me of the earlier promise of mono-rail travel where we just see relatively short distance systems in use at novelty locations like Disneyland, Seattle and some airports.

    Read the full WSJ article, “The Race to Create Elon Musk’s Hyperloop Heats Up“.

    Further Reading:

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    What’s Driving Real Medical Tech

    What’s Driving Real Medical Tech
    by Bernard Murphy on 12-17-2015 at 12:00 pm
    Categories: IoT

    I just watched a webinar on non-invasive bio-imaging as a way to detect and track disease, which gave me a sense of the way tech progresses in the medical field and makes for a positive counterpoint to my views on medical IoT, at least as envisioned in much of our industry. The webinar, on new approaches to in-vivo imaging was hosted by Science magazine and sponsored by Perkin Elmer (remember those guys?). Presenters were Christopher Contag, Professor in Pediatrics, Radiology and much more at Stanford and Anna Moore, Professor in Radiology and much more at Harvard Medical School. A lot of the focus was around detection and treatment of cancers so I’ll stick to what I learned there, though there was also mention of application to diseases like diabetes.

    Cancer is still a very challenging disease, both in detection and therapy. As we live longer and avoid what earlier might have killed us for other reasons, cancer becomes more prominent as a cause of death. Detection is hampered by the fact that current methods find possible tumors at a quite late stage (grown to as many as 1 billion cells), and remedial action such as excision always leaves the possibility of some residual cancer cells around the periphery of the surgery which then go on to metastasize. A sobering fact mentioned in the webinar is that 90% of cancer-related deaths are due to metastasis, not to the original cancer.

    For imaging, one goal is to get to much earlier detection, when a tumor has grown to as little as 1000 cells. This gives a better chance of micro-targeting the tumor, not just in where it is but also in cell biology. Some suggested methods for detection are use of photoluminescence (uptake of luminescent compounds in cancerous cells which can then be detected from outside the body), to the use of optical imaging (either from outside or through endoscopy) in short-wave IR (~1.5um) with carbon nanotubes. Imaging helps not only in detection but also in tracking progress in response to therapies. Wearables could also help here in counting tumor cells circulating through the vascular system which can contribute to metastasis.

    Another practical and possibly near term advance in imaging is in use of complementary imaging techniques to confirm diagnoses. A known problem with mammography is the rate of false positives, leading in some cases to unnecessary surgery, since X-rays cannot easily distinguish between tumors and fibrous tissue. One method that has been shown to be very complementary is optical imaging of hemoglobin concentration in the breast, combined with X-ray data. Fibrous tissue showing as a potential tumor in an X-ray does not show in the optical view and can be ruled out as cancerous (because blood concentrates around a growing tumor but not around fibrous tissue).

    Finally, remember that point about surgery leaving a residue of cancerous cells too small for the surgeon to detect? Surgical tools for excision could be supported by cancer-detecting microscopes with resolution down to 1um, helping surgeons be much more accurate in eliminating margins of tumors around the main excision. Advanced laser-based surgical tools could micro-target these margins, based on this microscopy.

    So where does this leave semiconductor and system design? First, any development would need to be in partnership with experts in the field, like GE or Perkin Elmer. Given that, suppport for imaging at specialized wavelengths, new and more portable methods for tomography combining X-ray or other sources and light images, wearables counting circulating tumor cells, creative combinations of microscopy and laser surgery – these are all possibilities and, once proven, many of these will be fairly high demand solutions. Where successful, these will certainly have more lasting value than counting how many times you stood up today.

    The literature in this domain that I have found is heavily medical, but if you’re willing to try, there are a few references HERE, HERE and HERE.

    More articles by Bernard…

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    Challenges in IP Qualification with Rising Physical Data

    Challenges in IP Qualification with Rising Physical Data
    by Pawan Fangaria on 12-17-2015 at 7:00 am
    Categories: EDA, Fractal Technologies

    With every new technology node, there are newer physical effects that need to be taken into account. And every new physical effect brings with itself several new formats to model them. Often a format is also associated with several of its derivatives, sometimes an standard reincarnation of a proprietary format further evolved by an standard body. For example, we have SPF from Cadence, and then SPEF, first proposed by OVI (Open Verilog Initiative) and later standardized by IEEE. We also have RSPF (Reduced Standard Parasitic Format), DSPF (Detailed Standard Parasitic Format), and SBPF (Synopsys Binary Parasitic Format).

    Why so many different formats for a particular physical representations? It’s to do with accuracy and different methods of modeling, efficiency and size of data, optimization, and so on. A certain type of format can be used for a particular type of trade-off, e.g. modeling preference, tool affiliation, data size optimization, and so on. One thing is common; the volume of data to represent an electronic circuit on a piece of silicon and characterize it under all physical conditions is increasing exponentially with every emerging technology node.

    The situation has become more complicated with lower nanometer technology nodes where manufacturing variation becomes prominent. The manufacturing variation can be significant to what you design, so you have to figure out the variation before manufacturing and make appropriate provisioning for that into your design.


    Above is a SEM image of contact-holes that illustrates photon shot-noise as a result of quantum effects at nanometer dimensions. When contact-hole dimension shrinks, the required number of photons to create the required response from the photo-reactive compound in the resist on wafer decreases, however the variability remains the same. Due to this, the difference in the number of photons seen by every contact-hole (i.e. photon shot-noise) makes a visible impact. There are specific formats to model manufacturing variability as well.

    It’s chaotic situation learning, understanding the pros and cons, and making use of various formats in designing, verifying, and testing semiconductor IP and SoCs. An IP must be fully qualified with all the data it possesses before its integration into an SoC. The volume of data in silicon IP has grown multi-fold.


    The above chart shows typical amount of characterization data necessary to describe the silicon IP needed to design and verify an SoC at different process nodes. It’s 1 TB at 14nm and is expected to grow to 4 TB at 10nm. Today, all factors including timing, power, noise, reliability, and variability have to be taken into account.

    At 14nm with FinFETs, power characterization requires a format like Liberty CCSP (Composite Current Source Power) to model power where the current with which an output is able to drive the connected RC network is accurately modeled in the characterization file. It takes into account the leakage as well as dynamic current. Advanced modeling for gate leakage, asynchronous operation, and voltage and temperature scaling is done to factor all effects.

    As the physical effects modeled in CCSP are highly dependent on process corner, there may be different CCSP models for different states, thus summing up to hundreds of CCSP files for each process corner for a full characterization.

    Interestingly, to add further to data, extensions to CCSP have already started; for electro-migration (EM) and on-chip variability (OCV) effects. Going forward to 7nm and below, the characterization data is bound to increase further.

    This exponential growth in volume and complexity of data per IP makes it impossible continuing with same home grown scripts to check the IP for both the IP provider and SoC integrator. Even simple checks applied on huge datasets can become a difficult and time consuming task. It needs smart automated tools which can do much more than just sanity check, for example trend check for a particular parameter, feedback and correction tips, waiver report, and so on.

    Fractal Technologies’ Crossfire is a right tool to provide an efficient and productive solution for quick IP qualification before its integration into SoC. Crossfire provides a detailed graphical as well as textual report on completeness of data, presence of all parts of a component, failed components / constructs, waived violations along with their justifications, and many more. It can quickly check large data by using separate processes on dedicated machines, thus parallelizing various tasks.

    Covering most of the design, verification, and test formats, design databases, and documentation formats, Crossfire is a tool of choice for IP providers to check the compliance of their offering and SoC vendors to qualify the IP for acceptance before using it in the SoC. Crossfire keeps adding support for upcoming new formats as well as popular vendor specific models.

    Read Fractal’s new whitepaper HERE.

    Pawan Kumar Fangaria
    Founder & President at www.fangarias.com

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    Why Did Apple Buy a Fab?

    Why Did Apple Buy a Fab?
    by Scotten Jones on 12-16-2015 at 4:00 pm
    Categories: Foundries

    It was announced today that Apple has purchased a 200mm fab located in San Jose from Maxim Integrated Products for $18.2 million dollars. My initial reaction to this announcement was shock but then I started thinking through what Apple might use the fab for and I concluded this announcement is less significant and surprising than it may appear at first look.

    The first point to make is this is a relatively old and small 200mm fab and is not suitable for production of Apple’s applications processors. According to the SEMI World Fab Watch Database the fab was built in 1987 and that is really old by fab standards. The same database also indicates that the capacity of the fab fully ramped was 10,000 wafers per month and that is also low by fab standard. Apple’s latest applications processors are made using 16nm/14nm FinFET processes with 10nm in development. 200mm equipment has only been pushed down to around 45nm and is simply not available for smaller nodes. Even if it was possible to make applications processors in this fab, low volume 200mm production wouldn’t be economical.

    So if they aren’t going to make the applications processors in the fab what are they going to do with it.

    There are two scenarios that I can envision:

    [LIST=1]

  • Apple may use the fab to develop sensors or displays using MEMS technology. This would likely be a good fab for MEMS development. Potentially it could be used for analog applications as well but I think that is less likely. Apple has historically outsourced all of their production and some kind of R&D usage fits their corporate strategy.
  • Convert the fab to a data center. Over the last several years the practice of buying older fabs and converting them to data centers has emerged. Fabs have large power feeds and large air conditioning systems both of which are needed for data centers. Fabs also typically have raised floors that are useful for connecting all of the servers together.

    In summary, although at first look Apple buying a fab may be surprising, a deeper look into the specifics of the fab they bought signals that this is likely less significant than it first appears. It is most likely for small scale R&D most likely into some kind of MEMS technology. Alternately it may not even continue to be used as a fab and instead be converted to a data center. It certainly doesn’t present any threat to TSMC and Samsung as Apple foundry providers.

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    IEDM Blogs – Part 2 – Memory Short Course

    IEDM Blogs – Part 2 – Memory Short Course
    by Scotten Jones on 12-16-2015 at 12:00 pm
    Categories: Foundries

    Each year the Sunday before IEDM two short courses are offered. This year I attended Memory Technologies for Future Systems held on Sunday, December 6[SUP]th[/SUP]. I have been to several of these short courses over the years and they are a great way to keep up to date on the latest technology.
    Continue reading “IEDM Blogs – Part 2 – Memory Short Course”

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    Tis the Season to be kWh Wasteful!

    Tis the Season to be kWh Wasteful!
    by Alex Lidow on 12-16-2015 at 7:00 am
    Categories: Foundries

    As the world gears up for the upcoming holiday shopping season, the technology needed by online retailers to meet demands will bring with it many unintended negative byproducts: increased inefficiency, waste and pollution, to name a few. Online sales are expected to grow by 12 percent in the holiday season, on top of an already unprecedented, some might say alarming demand for online information.

    Why alarming? In 2014, data centers in the United States consumed approximately 100 billion kilowatt hours (kWh) of energy. According to Sudeep Pasricha, an associate professor in the Department of Electrical and Computer Engineeringat Colorado State University, “that’s almost twice the electricity needed to power the whole state of Colorado for a year.” Further,this growing and insatiable desire for digital content is actually polluting the environment: the massive data centers that house all this digital content on servers are now responsible for an astounding 2 percent of global greenhouse gas emissions, a similar share to today’s aviation industry.


    Source: Thinkstock gyn9038

    Inefficient grid
    To add insult to injury, the power needed to support this rapidly growing demand comes from an electrical grid that is wildly inefficient and is based on infrastructure that was created, in large part, more than a century ago. To put it simply, electricity goes through several conversion stages: first, from its origination at the power plant, then on to transmission through power stations before finally feeding the remaining energy through semiconductor chips to provide computer power to servers. And due to aging equipment, a significant amount of power is lost as it travels from the power plant to the computer chip that does all the actual computing work.

    Just how significant is this waste? It turns out that the power grid supplies 150W of power to meet the demands of a digital chip that may need only 100W. Moreover, the amount of wasted energy is even greater because every watt of power lost through power conversion is transferred into heat. And it is necessary to remove that heat from the server farm by expensive and energy-intensive air conditioning. It takes about 1W of air conditioning to remove 1W of power losses, effectively doubling the inefficiency of this power conversion process. Not to mention the enormous amount of carbon-dioxide that these air conditioning units emit in an effort to convert all that wasted energy.

    In aggregate, the combined waste across the United States due to data center power conversion is enough to power over half of the state of Colorado.

    Limits of silicon
    And if the inefficiencies and waste in the power grid aren’t enough, the power conversion process has been built around post World War II silicon-based semiconductors, which have reached their theoretical power conversion performance limitations. Subsequently, these chips are responsible for creating additional power inefficiencies, with great financial and environmental costs.

    However, new materials have emerged that can convert electricity more efficiently and at a lower cost. In short, superior crystal properties in these materials enable the elimination of the most wasteful final stages of conversion. It’s a dynamic similar to the evolution of air travel in the post WWII era. Initially, air travel across the country required at least one stop for refueling. When jet powered flight became commercially available, the increased fuel efficiency resulted in not only non-stop coast-to-coast travel, but also significantly reduced costs of the journey.

    By eliminating the inefficiencies in this final stage in the server farm power architecture we can realize a direct saving of 7 billion kWh per year. This is doubled when air conditioning energy costs are added, bringing the total to about 14 percent of the total energy consumed by servers in the US alone. The cost savings are also significant. At the average cost of $0.12 per kWh, that’s a savings of $1.7 billion annually, which does not include the additional savings in system cost resulting from fewer power converters and air conditioners.

    While the need for computing power is only likely to increase in the upcoming holiday shopping season and beyond, technologies are appearing that will help reduce waste and drive subsequent environmental and financial savings that benefit future generations of information gluttons the world over.

    Now that’s a holiday gift that I believe Santa and I can both agree on!