SemiWiki – Page 685 – The Open Forum for Semiconductor Professionals

December 22, 2015

How Wireless Modem IP is Aiding Roadmap to 5G Chipsets

How Wireless Modem IP is Aiding Roadmap to 5G Chipsets
by Majeed Ahmad on 12-22-2015 at 4:00 pm
Categories: 5G, Arteris, IP, Mobile

The semiconductor industry is steadily charting its course toward 5G chipsets with the availability of extremely complex system-on-chip (SoC) designs that support the surge of data traffic over next-generation wireless networks. Take Blu Wireless Technology, for instance, the IP supplier from Britain that is using the Arteris FlexNoC interconnect in its Hydra WiGig and backhaul subsystems.

Blu Wireless, which designs and licenses wireless modem IP for multi-gigabit communications standards like WiGig, is among the early entrants in the commercial 60 GHz chipset market. The chipsets for 60 GHz millimeter wave radio with up to 7 Gbit/s speeds have passed the certification tests and are ready for production and launch in 2016.

Blu Wireless develops PHY/MAC solutions for high-speed wireless networks

The tri-band WiGig chipsets—comprising of the transceiver, power amplifier and antenna—can handle links at 2.4 GHz, 5.8 GHz and a number of unlicensed 60 GHz bands.

For s start, the WiGig-ready chipsets aim to cut the TV cord by facilitating in-home video streaming and other high-speed multimedia applications in the entertainment domain. But the far bigger prize for these chipsets is the nascent 5G market where Blu Wireless is eyeing its IP for both backhaul links to small cells as well as high-bandwidth links to 5G terminals.

Anatomy of a 5G Baseband Chipset

The Bristol, England–based Blu Wireless is a supplier of IP for gigabit-rate wireless modems operating in the millimeter-wave frequency bands. The company’s 60 GHz modem is based on its Hydra PHY/MAC technology that boasts a phased-array antenna.

It’s a baseband DSP solution that uses a hybrid hardware and software architecture while employing heterogeneous multiprocessing technology in order to reduce interference. Here, it mixes fixed-function DSP blocks with highly-optimized parallel vector DSPs, which in turn, creates a very complex DSP pipeline.

That’s essential because multiple DSPs in the digital controller have to handle a lot of arbitration and quality-of-service (QoS) tradeoffs—for example, latency vs. bandwidth—while requiring to limit the size of the die and implement SoC-wide power management. As a result, Blu Wireless needed an SoC interconnect solution that would allow it to implement end-to-end QoS and guarantee the on-chip latency and bandwidth requirements.

Blu Wireless has licensed the Arteris FlexNoC interconnect IP for its Hydra WiGig and 4G backhaul subsystems. The Arteris FlexNoC fabric primarily caters to the digital side, where it serves as the main interconnect in the baseband, allowing Blu Wireless to make latency and bandwidth optimizations per link.

The FlexNoC interconnect architecture encompasses serialization, buffering, arbitration, etc.

The digital controller is responsible for high-bandwidth digital signal processing. Arteris is also offering its FlexNoC interconnect solution on the analog side, but it’s a smaller NoC part.

The Arteris FlexNoC interconnect IP allows easy simulation and exploration to decide link widths, the number of wires and QoS setting. Here, FlexExplorer, a component of FlexNoC interconnect fabric, allows the simulation using SystemC models of candidate network-on-chip (NoC) architectures.

Specifically, for WiGig, the challenge for the digital controller is to keep the RF system “fed” to achieve the best possible data rates. The rates to and from the PHYs that are connected to the controller exceed 2 Gbit/s. Blu Wireless sells both digital and analog IP for WiGig to comms chipmakers and calls it the MAC subsystem.

Heading Toward 5G

It’s worth remembering that millimeter wave is most likely going to play a crucial role in breaking the bandwidth barriers for the realization of 5G networks. The industry giants like Samsung are heavily focusing their 5G development work on millimeter wave communication amid its potential as an ultra-dense network for small cells.

Moreover, 5G isn’t merely about mobile Internet services offered over wide-area cellular networks. In fact, the notion of 5G encompasses multiple connectivity solutions to provide communications services for a myriad of new devices, ranging from smartwatches to drones to connected cars.

Blu Wireless founder and CEO Henry Nurser demonstrating a 60 GHz module

Blu Wireless is part of the XHaul Project—one of the initiatives from the European Commission’s 5G Infrastructure Public Private Partnership (5G-PPP)—that is focusing on backhaul technologies while using both millimeter-wave radio and fiber-optic links.

Blu Wireless is contributing millimeter wave modems in the trial network that is targeting sub-1ms latency and speeds of up to 10 Gbit/s. The XHaul Project is being conducted in Blu Wireless’ hometown Bristol; other participants include Huawei, Telefonica I+D, TES Electronic Solutions and the University of Bristol.

Future Shock – IoT benefits beyond traffic and lighting energy optimization

Future Shock – IoT benefits beyond traffic and lighting energy optimization
by Bill Montgomery on 12-22-2015 at 12:00 pm
Categories: IoT

The year is 2029, approximately 35 years after the Internet went mainstream and today the world, its people and things are connected in ways that the Internet’s pioneers could never have imagined. The Internet of Things (IoT) or as Cisco put it, The Internet Of Everything (IoE) is now a reality, enhancing our lives in myriad ways.
Continue reading “Future Shock – IoT benefits beyond traffic and lighting energy optimization”

December 22, 2015

China’s chip plans an economic attack on Taiwan?

China’s chip plans an economic attack on Taiwan?
by Robert Maire on 12-22-2015 at 7:00 am
Categories: Foundries, Semiconductor Advisors

An economic “bear hug” cold war invasion? If China can’t get Taiwan by politics or force maybe it can get them by a backdoor economic takeover starting at their most crucial spot – Chips. An ulterior motive for China’s semiconductor aspirations, the $100B silicon Trojan Horse?

Its quite clear that semiconductors and electronics are the rocket fuel that has been powering Taiwan’s economy for as long as anyone can remember. I don’t know if PC motherboards are made anywhere else on the planet and clearly TSMC is an economic powerhouse which spawns many other supporting industries built around and on the semiconductor devices that come rolling out of its fabs.

The tiny little runaway island off the coast of China is economically huge and in many ways in a much better position in the critical technology area than its large and jealous neighbor.

Becoming a “player” in the semiconductor industry…
Its also clear that China needs to be even more in the technology space and a key ingredient is semiconductor device technology which they are still lacking. Yes they have SMIC and fabs from outside companies being built but they are not up to par with the US, Korea or Taiwan. This limits them to always being dependent on others .

So, spending $100B to get in the chip business makes all the sense in the world for them and I am frankly surprised they didn’t start earlier than this year (in earnest). It will help them both economically and militarily.

Infiltrating Taiwan’s economic core?
If China can intertwine its economic investments with companies like TSMC, ASE, UMC and others if will greatly accelerate what is already the “fait accompli” of Taiwan being merged back into greater China. What might otherwise take another generation could likely be accomplished in a much shorter period without so much as a rattled saber or shot fired. Essentially taken over from the inside out not the outside in…..

Other targets outside Taiwan could also help
If China buys Global Foundries at some fire sale price as Abu Dhabi exits stage left they could get their hands on a lot of IBM’s semiconductor secret sauce which they would not have been able to directly purchase a year ago. But who’s to argue now that its a foreign entity selling to another foreign entity? China could also pick up AMD at fire sale pricing and get immediate access to server/cloud capable CPU’s as well as PC compatible parts which already are produced by Global Foundries.

The only thing missing is memory….maybe the Japanese will get out of the last remaining island of semiconductor technology and sell off Toshiba’s memory operations….hey, you never know. In short , with a $100B wallet it isn’t that hard to buy your way into the semiconductor business.

Could put heat on Korea as well…
Although Taiwan is a clear target and perennial thorn in the side of China, Korea is not that far from China and the counterpoint to China’s North Korean Puppet state. Right now a big slug of both Taiwan and Korea’s technology economic output is exported to China. If that goes away because China can produce it all by itself it would put a torpedo in the sides of both economies that would significantly weaken them.

Expect China to accelerate the Semiconductor M&A in 2016
With all these benefits and a large war chest there is no reason to think that China will slow down in 2016. We would expect that China may be the gasoline thrown on the fire of an existing M&A semiconductor bonfire.

This could certainly help the depressed overall valuations in the semiconductor industry that have been left in the dust by, Apps, IOT, the cloud and everything software driven….

Apple buys a fab????
We could not help but notice that Apple has bought a former Maxim semiconductor fab in San Jose , not too far from its headquarters and right next door to a new Samsung building (interesting poetic justice…).

Although this is far from a state of the art fab running 14nm devices its does come fully furnished with 197 semiconductor manufacturing tools from the standard suspects. It was recently shut down in July so its not a graveyard.

Not building the A10 any time soon…..
It is a small, low volume/prototype capable operation that is likely suited for the other ancillary chips that go into apple devices (all that semiconductor glue that holds everything together). At $18M is not even a microsecond’s rounding error in Apples tsunami of money but the fact that they are doing it is interesting.

It was also recently revealed that Apple has a secret R&D facility in Taiwan that appears to be aimed at display technology.

Both of these moves appear to make Apple appear a lot more “Samsung like” in their ability to develop chip and display technologies.

Going Vertical?
Samsung has been a vertical manufacturer for a long time now and it has obviously served them well. These two moves seem to imply that Apple is perhaps taking a more active/controlling role in the design and manufacture of all parts that go into its devices. It sure sounds like a change in strategy, perhaps its a way to try to say ahead and differentiate Apple products as having outsiders develop technology doesn’t keep it out of the hands of competitors.

If these are the first two shots in this new direction we can imagine that Apple could easily buy its way into a lot of other key technology areas, after all its not doing a lot else with its cash hoard and this seems like a great strategic use.

Maybe Apple will put the silicon back in silicon valley!!!

December 21, 2015June 14, 2019

How to Overcome HW Project Release Nightmares

How to Overcome HW Project Release Nightmares
by Tom Simon on 12-21-2015 at 8:00 pm
Categories: EDA, Perforce

Is a software development release methodology a “square peg in a round hole” when it comes to hardware design? To answer this question we have to look at how exactly hardware design projects differ from their software counterparts. Intuitively we know they are fundamentally different. Let’s take a second to dig deeper to understand why development methodologies for software do not map well into the hardware space, and then discuss solutions that do work.

HDL’s are a lot like the source code found in software projects, but downstream in the flow we encounter many binary files. These include custom layout files, place and route data bases, and models for simulation, etc. The presence of binary files breaks the ability to use diff and to merge two separate but parallel versions of a file. Really only one person at a time can work on a layout cell, for instance.

Hardware projects involve large teams that often are using or modifying the the same data. It’s common for sub-teams to have tens of members and for the entire project to include hundreds of members. These teams are arrayed over partitions of the design and they also cross functional boundaries, such as front end, simulation, verification, physical, physical verification, test, DFM, silicon engineering, etc.

When it comes to the number of files that need to be managed and the amount of data, we see tremendous numbers. A single workspace may consist of tens of thousands of files, or even more. Not just the number of files, but the total amount of data is enormous. It can head up into the tens or hundreds of gigabytes.

Lastly, the flow steps themselves can take days, or weeks. Place and route steps, verifying physical design rules, extraction for LVS or simulation, and many other steps easily can take days or longer.

All of these characteristics make it hard to overlay the popular branch/merge release flow onto physical design projects. In this approach each designer or developer creates a branch of the main trunk and can work on any or all of the files. It is isolated from the work of others, and down the road it will be merged back into the trunk. For software projects, files can be diff’ed and separate versions can be merged, based on the specific edits.

Because each team member has their own copy, it means that there are potentially many branches. In a hardware design team of 20 or 50 people, you can see that this can create a lot of branches, and eventually it will be some unlucky team member’s job to try to recombine them into something like a workable release. The lengthy work cycles mentioned above add to this by causing the branches to live long lives before any attempt to merge them back into the main trunk. This means that the baseline will have moved along significantly and increases the amount of data that needs to be reconciled.

Methodics has posted an interesting summary of best practices for data management used in hardware design projects. Their EDA focused data management solution is agnostic when it comes to the underlying revision control system that is used. This makes it easier for large enterprises to combine systems and achieve better integration. As a result of this a lot of people use Perforce based data management systems for their design data. The summary that Methodics provides talks about the alternative to the branch merge release process as used in Perforce. This recommended solution is referred to as Release on Trunk.

The Methodics white paper goes into more detail, but the main points are that each user creates a workspace based on a known good release. When they make changes they return them to the main trunk. They also keep current on releases that are updating the main trunk. Finally, when it is time for them to create a release based on their updates, they ensure they have the latest release updates in their workspace and run full regressions there before making the release.

Methodics also briefly also covers how to deal with the massive workspaces that are generated in hardware design flows. They point back to underlying capabilities in Perforce Helix and show several examples of ways they can be used to minimize the storage requirements.

The entire white paper is on their website and is interesting reading. It’s good to know that enterprise data management solutions can be applied to EDA design flows. But at the same time it is critical to understand where and how differences arise and how to adapt to them.

December 21, 2015June 14, 2019

How to Solve the Business Gap in SEMI Industry?

How to Solve the Business Gap in SEMI Industry?
by Eric Esteve on 12-21-2015 at 4:00 pm
Categories: Cadence, IP

This white paper about Cadence innovative mixed-signal IP concept “Cadence Multi-Link PHY IP (SerDes, Analog Front-end, and DDR) to Design SoC Platform breaking the “Business Gap” on 14/16FF” describe the problem, the emergence of a “business gap” linked with incredibly high development cost when targeting most advanced FinFET technology nodes, and the solution, integrating a Multi-Link PHY IP. Chip makers targeting the lucrative market segments like FPGA, Mobile, Networking or Data Center are forced to jump on the most advanced technology node for several reasons. They all have to be the first to bring the highest possible processor performance or bandwidth (servers, networking), or the first to launch an Application Processor (smartphone) offering both maximum possible features, higher performance and at par or lower power consumption than the previous generation. The SoC development schedule is constrained by the market expectation, pushing for the lowest possible Time-To-Market (TTM). Designing a SoC on 14/16FF nm and below, also means finding a solution to a critical business problem linked with the increasingly high development cost. The IP reuse concept is born in the 1990’s to help optimizing the chip design. Commercial IP market took off in the 2000’s to solve the so-called “design gap”, as designer productivity didn’t grow fast enough to allow building System-on-Chip although CMOS technology scaling made it possible. In this white paper, the author introduces the “business gap” concept: amortizing the incredibly high development cost for a SoC targeting a single application is becoming extremely difficult if not impossible, except for very few applications like smartphone… Taking 14/16nm FF node as an example, the average number of IP blocks in a SoC is about 120 (source: IBS report, 2014). Still in the same SoC, interfaces represent about 50 IP blocks. This Cadence Multi-link PHY IP concept applies to high speed SerDes based interfaces. Let’s make it clear: Multi-Link is much more than Multi-protocol, a 10 year old, very cleaver concept reaching the limit, due to the business gap. The figure below is very helpful to understand that the Multi-link concept provides the flexibility of Multi-protocol plus re-use capability (here is the innovation): a single SoC can be designed to address multiple markets or applications. Let’s take a customer example as a real case. Designing a single but configurable SoC, this company has integrated 16 lanes Multi-Link PHY IP. To target Networking application, the PHY is configured as 16 lanes PCIe, to target Storage as 8 lanes PCIe, 8 lanes SATA and for Computing as a 12 lanes PCIe, 4 lanes 10G-KR. Amortizing the SoC development cost will be much easier as the ROI is now coming from three different markets, instead of a single application as it was the case before using the Multi-link concept. The benefits of using this Multi-link PHY IP concept are multiples as the various cost and resource intensive activities like IP integration, characterization setup and board design, qualification or PDK update are done only one time, leading to faster SoC design. Shorter TTM can be a priceless advantage for SoC addressing highly competitive markets. Such a Multi-protocols/Multi-links PHY IP offering Cost of Ownership (CoO) and TTM benefits all along the supply chain from fabless to foundries and EDA ecosystem. Cadence has enlarged this Multi-link concept to Analog Front End (AFE) IP for wireless communication, as well as to DDRn (LPDDRn) Memory Controller PHY IP. Reading this white paper, you will find much more detailed explanations which can’t fit in a blog like this, I really encourage you to read it (I must recognize that I’m the author…). You can access the white paper here. Moore’s law evolution is generating a “business gap”, designing a SoC on advanced technology nodes requires such high investment that the return may not be guaranteed if you target only one application. A conservative approach would be to keep designing on affordable nodes, 28nm or above, but it would prevent to benefit from extra performance and lower power, known to be the keys of success. Moving from chip architecture, one SoC targeting one application, to system architecture and creating a SoC platform allowing targeting several applications with the same SoC may break this “business gap”. This new approach is made possible by the flexibility offered by Multi-link PHY IP (SerDes or AFE). By Eric Esteve from IPNEST

Semiconductors and Conflict Minerals

Semiconductors and Conflict Minerals
by Daniel Payne on 12-21-2015 at 12:00 pm
Categories: Dassault Systemes, EDA

Our semiconductor industry uses many different materials and chemicals in the production of chips, boards and electronic systems. But what should we do if the minerals like tantalum, tin, tungsten and gold are coming from the eastern provinces of the Democratic Republic of the Congo where armed bandits are forcing workers against their will? In the United States there’s a law called Section 1502 of the Dodd-Frank Wall Street Reform and Consumer Protection Act that requires companies to identify where the minerals used in their products came from. Our semiconductor companies need to have a Materials Declaration (MD) and a Conflict Minerals Report (CMR) to be in compliance with directives and industry data reporting standards like:

RoHS (Restriction of Hazardous Substances)
REACH (Registration, Evaluation, Authorisation and restriction of CHemicals)
ELV (automotive End of Live Vehicle requirements)
GADSL
Battery
Packaging
WEEE (Wasted Electrical and Electronic Equipment)
Dodd-Frank Conflict Minerals
IEC-62474
Aerospace & Defense DSL

Mike Zepp from Dassault Systemes spoke with me by phone to share his background in plastics R&D, then the automotive industry where he has first-hand experience with what it takes to be compliant and produce a CMR. In 2005 Mike joined Dassault because they had a vision and software to help companies be compliant with these types of regulations and laws.

The specific software from Dassault is called Material Compliance Manager and it lets you assess product materials compliance during product design through integration with engineering BOM management. You can even integrate Material Compliance Manager with your favorite PLM and ERP systems. The basic process follows this sequence for your supply chain of outsourced components:

Requesting
Receiving
Reviewing
Approved material compliance
Conflict minerals declaration

Mike shared that many electronics companies started out building their own in-house tools to track compliance, but now many have started to considering switching to something off the shelf so that they can focus on their core business competence. Starting with their 2014 SEC filings, the new US law applied to US publicly traded companies, and they must declare that their products don’t contain any conflict minerals, an extensive process where companies have to request data from the OEM all the way down the supply chain, ultimately reaching the smelters of mined ore. Fortunately, the Dassault software manages all of this information throughout the supply chain, ingesting the data, sending out emails, and managing the process.

The Materials Compliance Manager is a browser-based tool that helps any organization create their materials compliance declaration. Companies like Keysight Technologies (ex Agilent) have about 100 people using this software, then thousands of engineers use the results of the tool to confirm that their products are compliant. Other companies that you might of heard about also use the software: AB Sciex (a division of Danaher), GE Healthcare, and Tesla Motors.

I’ve recycled my old consumer electronics devices at the local Staples store, where they gather a variety of scrap electronics and an electronics recycler then decides how to re-use and dispose of all the bits and pieces to protect the environment from hazardous chemicals. Lots of companies need to worry about being compliant: Foundries, Fabless companies, packaging companies, the electronics supply chain.

You can learn a new tool like the Material Compliance Manager in about a week or two to become proficient, and the folks at Dassault can help get your engineers trained. In summary, the key features and benefits of using this approach are:

Manage materials to meet environmental compliance
Analyze your product’s compliance
Security and IP protection
Assess impact of new compliance directives
Manage supplier material declarations
Export of product compliance to customers
IMDS integration for auto suppliers
Integrate the supply chain for supplier data collection
Start supplier material declaration requests
Determine engineering BOM materials compliance
Maximize reuse of compliant components

How Can Big Data and EDA Tools Help?

Enterprise Design Management Comes of Age

December 21, 2015August 22, 2024

Why Medical IoT is Set to Take Off!

Why Medical IoT is Set to Take Off!
by Rajeev Rajan on 12-21-2015 at 7:00 am
Categories: Foundries, GlobalFoundries, IoT

In a recent SemiWiki post, “Why Medical IoT Won’t Take Off,” the author raised some very interesting points on why certain IoT applications won’t succeed. But, it’s important that these points are looked at holistically, within context, and compared to other IoT features that are already improving health by increasing the availability and quality of care.

Source:N2M Advisory

On the author’s first point of bridging the gap between the IoT community and the medical community, focusing on the largest healthcare organizations that serve the most number of patients, you will be hard-pressed to find any that don’t have some form of a Digital Health office, with leaders ranging from Chief Digital Officer, Chief Information Officer (CIO), Chief Medical Officer / Chief Medical Information Officer (CMO/CMIO). Their charters are to be abreast of the technological advances in the medical space ranging from Smart Devices, IoT, Healthcare Information Technology (HIT), and Data Management and applying them to care delivery protocols. . Today, there are quite a few healthcare startups being launched by experienced doctors who are very knowledgeable in the medical and technology ecosystem space as well as multiple pilots and publicly announced rollout plans. Similarly, the majority of US government agencies such as the FDA, FCC and FTC are augmenting their staff with cross-domain expertise. Numerous HIT consulting firms are managing the technical implementation, while incorporating the applicable policy and regulatory requirements.

On the regulatory side, the FDA has been making policy revisions over the past few years for communication, smartphones, and Mobile Medical Apps (MMAs) to reduce the regulatory burden; terming this as Smart Regulation.

Today’s IoT technologies typically provide the processing, communicating, sensing, gateway capabilities that enable data collection, security, and battery/power management for long-term operation. These IoT features need to be combined with compelling user experiences to create effective patient-consumer solutions. In a broader context, when applied to the medical field, the promise of IoT is to enable Remote Patient Monitoring (RPM) solutions.

On the point of IoT devices generating a large amount of data, we need to clarify what is the data and which device is generating it. Typically in RPM today, there are two ways medical and IoT operate to collect the patient’s vital signs medical measurement reading: (1) an IoT gateway (example) device gets the reading from a patient’s medical device (e.g. blood pressure monitor, weight scale, blood glucose meter etc.), and (2) a medical device and the IoT gateway are a single device (example) that gets the reading. Afterwards the reading is communicated over a wired or wireless network to the doctor’s office/provider system/3[SUP]rd[/SUP] party healthcare partner/other. The amount of data generated from a typical home-use medical device can vary from a few kilo-byte (KBs) to a few hundred KB’s per reading. Data growth is caused, not by the per measurement readings, but by the patient taking multiple readings over the span of a day and making it available, near real-time, to their doctor’s office. Imagine a patient going to their doctor once or twice a month to have their vital signs taken versus doing it themselves at home twice a day over a month. Of related importance, is the flow of digital measurement readings from the medical/fitness device/wearable sensor to the patient’s Electronic Medical Record (EMR), to aid in Clinical Decision Support (CDS). In the end, it could be a normal reading, or an anomaly or something else, but it has a place in the continuum of the patient’s health and longitudinal medical record especially if it has been triggered by a health event or condition. Connecting the “dots” of data is what IoT medical nodes do best, that can lead to actionable outcomes as a result of analytic systems that marshal and process the data. On the cloud side, this has become easier in recent years with more provider’s adopting EMR systems as well as CDS systems. We are starting to see the shift towards smart IoT edge-nodes, which don’t blindly collect the “dots” but, instead, process data based on rules, triggers, and algorithms and reduce the amount of that data sent to the cloud.

Lastly, the author calls out motivation as a problem intrinsically tied to human psychology. With the IoT lens in mind, it should be understood that it is the patient’s responsibility to manage their healthcare. IoT features, applications and systems attempt to influence healthcare and fitness discipline from reactive to proactive, incorporating them as part of daily routine. Patients with chronic disease conditions such as hypertension, diabetes, and COPD, and who are committed to manage their health, do adhere to take their medications. This will become easier as the onset of multiple wearable sensor smart patches and garments that monitor and collect our vital signs become a part of our day-to-day lives.

Many companies are showing interest in making connected health care devices. Whether it’s a wearable sensor or smart patch which tracks your workout or a garment that monitors and collects a patient’s vital signs, IoT will bring improvements to healthcare. It is not a question of if it will take off, but when. Here is a sign of “Things” to come.

Also Read: Why Medical IoT Won’t Take Off

December 20, 2015June 14, 2019

Auto Introspection

Auto Introspection
by Bernard Murphy on 12-20-2015 at 4:00 pm
Categories: Automotive, Cadence, EDA

It is an indictment of our irrationality that our cars are now more health-conscious than we are. Increasingly safety-conscious readings of the ISO26262 standard now encourage that safety-critical electronics (anti-lock braking control for example) automatically self-test, not just at power-on but repeatedly as the car is in operation. Any reliability failure will be used to trigger a driver warning that a critical system may be performing below expectations and therefore the car must be taken in for service as soon as possible. We in contrast tend to monitor our health reactively only after something has gone wrong. Ah well – perhaps someday we will be as wise as our cars.

The Cadence Encounter Test family goes a long way to addressing these needs for cars and other safety-critical systems. Good health starts with being born healthy so the auto industry requires a very high standard for DPM (defects per million) in shipped silicon. Cadence has a strong solution in which test is integrated during Genus synthesis: scan of course and scan compression but also LBIST, MBIST and IEEE1500 wrapping to simplify core testing and isolate analog components in test.

In big digital companies, test is a domain staffed by a team of specialists skilled in all the arcane arts of scan, BIST and more. Automotive electronics development teams aren’t so lucky. Historically their content has leaned much more to big A, little D with minimal understanding of requirements for advanced DFT. As the digital content in auto electronics has exploded, their need for ease-of-use in insertion and optimization of test becomes more than a nice-to-have. The Cadence test solution is attracting an enthusiastic following because users are commenting that it is the most push-button flow they have seen. This also becomes incredibly important for non-experts to manage constrained test solutions: minimum number of test pins (even as low as one test pin), low DPM area, small pattern counts and more. All ho-hum to those big digital test teams but critical to these automotive teams feeling their way into DFT in a market setting ultra-high standards.

This handles the healthy neonate checks, but what about post-silicon self-test, the ongoing wellness checks? As I mentioned earlier, power-on self-test is already a requirement for critical systems, but the ISO standard also encourages diagnostic coverage requirements which repeatedly test as the car is being driven. This means that periodically your ABS controller goes off-line to check if it’s OK. That creates an interesting constraint – you’re happy that it’s checking itself frequently but you really don’t want it staying off-line for very long. Which in turn means that LBIST checking must be both high coverage and run very quickly.

Cadence Encounter Test addresses both of these problems. Since LBIST testing is based on random patterns, it is sensitive to random-resistant faults such as the output of a wide comparator which has a low probability of being triggered by random vectors. The software uses Random-Resistant Fault Analysis to correct for these cases, also Deterministic Fault Analysis which finds and corrects for generally hard-to-detect faults (those hard to detect even with directed tests). Both of these are used to drive insertion of test points which both improve coverage and reduce test time – as much as 50% reduced as reported by one Cadence customer. Your ABS controller can spend less time in introspection, which, all things considered, is probably better for your health.

Cadence is also increasing support for in-system test through their MBIST solution by allowing customers to add their own algorithms to test for new failure modes they may have discovered. I really like where Cadence is headed with this and their LBIST work. I have commented before that an important way for EDA to break out of its doldrums is to add value post-silicon. Encounter Test is breaking that trail and I hope other EDA domains will follow.

You can read more about the complete Cadence Encounter Test solution HERE.

Calibre in the Middle of Semiconductor Ecosystem

Calibre in the Middle of Semiconductor Ecosystem
by Pawan Fangaria on 12-20-2015 at 12:00 pm
Categories: EDA, Siemens EDA

Albert Einsteinhad said, “In the middle of difficulty lies opportunity”. In today’s world dominated by technology, or I must say internet which has initiated collaborative information sharing, “leading from the middle” is the new mantra of life.
Continue reading “Calibre in the Middle of Semiconductor Ecosystem”

December 20, 2015

The Cult of IoT! (FitBit)

The Cult of IoT! (FitBit)
by Daniel Nenni on 12-20-2015 at 7:00 am
Categories: IoT

Granted the word “cult” can have a negative connotation, especially when applied to small religious groups but cult can also mean a great devotion to a movement or intellectual fad. Some people call Apple a cult with Apple Stores being their Churches. If you look at the lines around the block or down the mall for new product releases the term cult can certainly come to mind. And that brings me to the cult of IoT and wearables.
Continue reading “The Cult of IoT! (FitBit)”