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Is FPGA Intel Next Big Thing for IoT ?

Is FPGA Intel Next Big Thing for IoT ?
by Eric Esteve on 11-04-2016 at 4:00 pm

I write this article in reaction to another article from Seeking Alpha titled “Intel Next Big Thing”. I have extracted this from the article:

The IoT space is growing rapidly with the advent of connected cars, smart homes and a variety of connected devices and appliances. However, before a full-blown ecosystem around these devices is developed, device makers have to deal with power efficiency. The good news is that with the help of low-power FPGAs, the devices can be made power efficient.

People writing in SA are expected to explain why you should (or should not) buy stock from a company in respect with this company’ strategy. In this case, the “Next Big Thing” for Intel is the Altera FPGA product line and the article explains how Intel could generate high return on their ($37B) investment by developing the FPGA business in Data Center and IoT. Data Center and IoT are completely different stories and the IoT ecosystem interesct with the data center only if you consider that the amount of data generated by a multitude of IoT systems will end up in the cloud, in the data center. Let’s see why I think that the flagship FPGA from Altera (or Xilinx, by the way), the products priced over $1,000, very performant and extensively used in Networking are NOT the best choice for IoT application, if you agree with the prerequisite “have to deal with power efficiency”.

At first, let me say that I think that FPGA is a great technology. FPGA has brought a benefit of an inestimable value in the fast changing world relying on networking systems to carry the data we are consuming for work or entertainment: flexibility. This flexibility has a cost and I am not talking about IC ASP (multiplied by x10 or x20 for the same function implemented into FPGA), but about power consumption. I have searched the web to find a short definition of the FPGA architecture: “Modern SRAM-based FPGAs have highest densities, but consume a lot of power and need an external non-volatile memory to store configuration bit-stream”.

This definition applies to both Altera and Xilinx FPGA, and we can verify what “a lot of power” means by taking a look at this figure extracted from an Altera white paper titled: “Leveraging HyperFlex Architecture in Stratix 10 devices to Achieve Maximum Power Reduction”:


Moving from Stratix V to Stratix 10 device means you move from 28nm to 14nm FinFET technology node. You don’t expect to integrate Transceivers (high speed SerDes based interfaces) into IoT, so let’s focus on Core Dynamic power, decreasing by 42%, as expected when you move from 28 nm to 14 nm, and Static power. In fact, the static power has two components. The first is the leakage power that you would have on any other Bulk of FinFET technology, but the second component is inherent to FPGA technology. This is the power dissipated by the SRAM (remember that FPGA is SRAM based architecture), considered as static as you have to refresh SRAN continuously to keep the FPGA programmed. The author is very proud of the 10 to 12 Watt of static power but imagine that you use such FPGA for an IoT application! Typical IoT has to stays always-on, and the logic to be wakes-up from time to time, but you have to keep the SRAM alive… at the price of this huge static power.

As far as I am concerned, I would not consider Stratix 10 product line for IoT application, such a static power consumption being far too high (by several order of magnitude) to comply with IoT requirements.

To end this article on a positive point, Intel is developing interesting new products, like this multi-chip package (MCP) integrating Broadwell CPU and Arria 10 GX FPGA in the same package. Such product will address data center application (not IoT), providing flexibility thanks to the FPGA and should help to slightly decrease the power consumption. The power consumption related to the chip to chip communication (Transceivers in the above figure) should benefit from the lack of package between the two chips. Let say that this is not a revolution, but a move in the right direction to reduce the power…

Frankly speaking, if the embedded FPGA (eFPGA) technology development becomes effective and if eFPGA could be used in the data center, it could be the revolution: instead of putting a SoC inside a FPGA, or beside a FPGA like in the above example, integrating just the amount of needed FPGA into a SoC would bring both flexibility and lower power. We will need to wait and see if eFPGA adoption will occur…

Eric Esteve from IPNEST

About Static Power:

The leakage power issue is so serious that in its 2009 report, the International Technology Roadmap for semiconductors (ITRS) describes the situation in terms of an existential crisis:

While power consumption is an urgent challenge, its leakage or static component will become a major industry crisis in the longterm, threatening the survival of CMOS technology itself, just as bipolar technology was threatened and eventually disposed of decades ago (14).



EUV transition comes into focus

EUV transition comes into focus
by Robert Maire on 11-04-2016 at 12:00 pm

We attended ASML’s analyst day in New York on Halloween. We were very impressed with the quality, content and clarity of the presentations and thought it was one of the best strategic positioning presentations we have seen in the semi industry. We also had an opportunity to meet with several members of senior management after the official presentation to have more detailed and candid discussions.

We came away with the view that after many years of hard work and obstacles that we are to the point where we have a clearer sense of the timing and remaining issues to be worked through to get into production in a “predictable” timeframe.

The vision of the EUV promise finally coming into focus is also amplified by the potential upside offered by the synergistic combination of the Hermes acquisition which recently passed its final hurdles.

Not an “imaging” company but rather a “patterning” company
Although ASML has spoken about this in the past, the length and content of the analyst meeting was able to articulate ASML’s desire and potential roadmap to dominate the entire patterning process rather than just the litho step and litho cell.

While Yieldstar has been a successful first step in growing into the overall space, the addition of Hermes adds the foundation of a much larger footprint and marketshare of the overall patterning market.

It is also clear that ASML is doing what Lam had attempted to do with the KLA acquisition, and that is put together more processes within the patterning arena to dominate this critical area. Without the KLAM combination ASML is somewhat unopposed in stringing together more processes.

Although it would never pass in todays regulatory environment (especially post KLAM) Lam itself would be a potential acquisition target of ASML to complete its full circle of the patterning process, but there are still other things that ASML can do to seal the deal.

Building a “Wall”…
One can think of ASML trying to build a “walled garden” around this patterning technology in order to try to keep others out, such as KLAC , NANO and NVMI etc;. Given that they “own” the litho process they can indeed limit others access to it and more tightly integrate Hermes much as they did with Yieldstar with great success.

In a way it is very interesting to note that this combination sailed through regulatory approval unopposed as compared to KLAM. This would imply that customers don’t have a problem with giving ASML more dominance in patterning even though they couldn’t stomach KLA and Lam together (obviously Nikon and Canon are too weak and far behind to even matter…as compared to TEL, Hitachi and ASMI etc;)

Not just sidestepping KLA but taking them head on…

ASML is not just content about finding a way around the KLAC “actininc” blockade, in which KLA halted development of an at wavelength EUV mask inspection tool, but rather ASML wants to take on KLAC (and NANO, NVMI and others) directly in the CD market by moving the E beam tool of Hermes out of just being a slow, R&D development tool into the arena of HVM monitoring and control which is the wheelhouse of KLA.

This frontal assault could be significant as ASML has the financial and technical wherewithall to execute on the needed work to get to multi beam and faster E beam tools. In addition since ASML owns the litho process they hold the keys to the information and control knobs which impact the process as compared to KLA which is just an observer. (obviously all this applies to both NANO and NVMI as well…)

The financial model…
Even though it sounded like a shock to many in the room the EUV had negative gross margins of 75% it should come as no surprise given where we are in the process. It should also not be a great surprise to expect 50% plus gross margins, similar to other products, when EUV finally gets up and running given ASML’s dominance in litho.

From a very simplistic perspective EUV tools cost roughly twice that of DUV tools but you need half as many EUV tools because of double patterning issues. This makes EUV somewhat of a “wash” in Litho cost but overall litho intensity keeps increasing which supports the overall revenue increases in the litho space. Essentially, all you need to do is get EUV on a more normal run rate and thus gross margin and EPS growth will fall in line with revenue growth to get to the 8 Euro per share in 2020 as suggested by the company.

You add to that another billion in revenues and one Euro in EPS for Hermes and you get to a total of 11 billion Euros in revenues and 9 Euros in EPSin 2020.

The stock…
Although we are more positively biased over the last 6-9 months the stock is still not cheap. If we assume 9 Euros of EPS in 2020 and use a 15X multiple, we get to a $137 stock price in 2020 (or 2019). Given that we are 3 years away from that with significant execution risk ahead of us, the stock is fairly valued.

For longer term investors, collecting a dividend with the patience to wait a few years is not too bad either as the certainty of EUV has increased and thus reduced the overall risk model.

On a relative basis it seems like a reasonably safe long term investment as compared to others in the industry.

PS; For those who were not able to attend in person , you missed a very politically incorrect halloween costume worn by the head of IR, Craig DeYoung……


RRAM Redux

RRAM Redux
by Bernard Murphy on 11-04-2016 at 7:00 am

Advanced memory technologies are a perennially hot topic thanks to a proliferation of data-hungry applications pushing our demand for more capacity and performance at less power and area. Among several technology contenders is Resistive RAM or RRAM (also called ReRAM). In this technology a conducting filament is grown through a dielectric on application of a voltage. RRAM is promoted as a replacement for traditional flash (non-volatile) memories and in principle should be a significantly superior solution. It is lower energy, bit-writeable and much faster to read and write. It also lends itself to 3D stacking which could enable high capacities as well as RRAM stacked directly on top of logic.

But RRAM has offered this hope before, only to get bogged down in an inability to deliver high memory capacity. Building small (~Kb) memories demonstrated all the expected advantages of RRAM – reads and writes in microseconds or less compared with milliseconds for flash, and lower voltage operation with much more fine-grained writeability, thus lower power. But capacity was limited by sneak-path currents on read. In RRAM writing a cell is voltage-based, but reading is current-based; when current flows through a cell you want to read, it also flows through neighboring cells, which makes it difficult to confidently interpret the read value. Those added currents also negate the power advantage.


Crossbar positions themselves as the leader in this field, claim they have solved the sneak path problem and have transitioned their technology to production. They were founded in 2010 and came out of stealth mode in 2013; they have raised over $80M so far, including a $35M D-round last year (per CrunchBase), so they certainly have the credibility and funding to play in this game. I talked with Sylvain Dubois (VP of marketing and biz dev) at ARM TechCon last month to get a sense of why they believe they have a scalable solution.

Sylvain first agreed that the big foundries have rejected most RRAM implementations so far because they don’t scale in size. However, Crossbar announced at IEDM in 2014 their own solution to the sneak path problem, using a method they call field-assisted superlinear threshold (FAST) selection which provides very high selectivity. They reported the method suppresses sneak currents in a 4Mb array to below 0.1nA across the commercial temperature range and selectors reliably cycle over 10[SUP]11[/SUP] cycles. He also noted that RRAM has a lower leakage current than flash as feature size decreases. Crossbar summarize a partial comparison of their RRAM with flash technologies below.


An important feature of the Crossbar RRAM is that it is compatible with standard CMOS processes, which makes it usable as an embedded macro in a larger design. They announced earlier this year a partnership with SMIC to provide this technology on a 40nm process. They have built an 8Mbit reference macro which is now available for licensing and they are actively working with customers to adapt the macro to their needs. They expect to pursue opportunities in embedded and IoT applications especially (obviously) in China. They are also working on a partnership with one of the mainstream foundries at a more advanced process node, announcement still TBD.

Based on density measurements they have gathered so far, Crossbar expects they should be able to scale up to terabits per die. If they are right, this could be a real game-changer for non-volatile memory both in embedded and mass storage applications. You can get an overview of Crossbar technology and applications starting HERE. There’s a detailed set of slides on 3D capabilities HERE.

More articles by Bernard…


How to nail your PPA tradeoffs

How to nail your PPA tradeoffs
by Beth Martin on 11-03-2016 at 4:00 pm

How do you ensure your design has been optimized for power, performance, and area? I posed this question to Mentor’s Group Director of Marketing, Sudhakar Jilla and product specialist Mark Le. They said that finding the PPA sweet spot is still often done by trial and error – basically serial experiments with various input parameters until the target specs are met.

Is this efficient? Clearly not. It could take weeks or months or really never come to fruition because of deadlines. Jilla and Le say that the ugly reality of finding the optimal PPA under the pressure of tight design schedules has been ripe for better EDA solutions.

What’s needed is an RTL-level automated “design space exploration” that lets designers simultaneously explore various design alternatives prior to implementation. The solution must be efficient, easy to use and provide the most useful analysis in the shortest time.

Mentor offers a design space exploration solution in their physical RTL synthesis tool, Oasys-RTL. Jilla says it is different than other available ‘what-if’ analysis solutions because it works at a higher level of abstraction, which makes it faster, while still achieving a good level of accuracy. He said it is also pretty easy to use. Oasys-RTL’s integrated commands control the various configurations; the designer just modifies existing synthesis scripts to add new variables to define the functionality of the desired exploration.

Download the new whitepaper RTL Design Space Exploration for Best PPA Using Oasys-RTL.


For example, Le poses a situation in which a designer needs to determine the top frequency at which the design can meet timing. If the performance is set too high, critical timing paths will be extremely difficult to close. Also, large SOCs have multiple complex clocks and frequency tuning becomes a challenge when there are tens or hundreds of clocks. Say the design uses four multi-vt libraries with four target frequencies.

Library: LVT 0.95 V, LVT 0.85 V, HVT 0.95 V, HVT 0.85 V
Frequency: 0.8 GHz, 0.9GHz, 1.0 GHz, 1.1 GHz

There are 16 different combinations, or scenarios, to analyze. Oasys-RTL processes each of the 16 scenarios as if they were individual configurations, and then provides a comprehensive summary of results for comparison. The results show the design meets the 0.9 GHz timing target for both LVT libraries.

Say you also want to include power in this analysis. Le points out to a case in which the results were counter-intuitive because the HVT 0.95 V library consumed more power than the LVT 0.85 V library. It turns out that the slower HVT library requires more optimization to meet timing, which causes increased area and power.


What about floorplan exploration? Jilla says that Oasys-RTL reads in the entire design and automatically creates a floorplan based on the high-level RTL modules and design data flow. Because it uses a patented “PlaceFirst” technology, physical placement information is available early in the design flow for accurate timing and congestion analysis.

Starting from scratch, you can set utilization targets for the design and use a design space exploration command to scale the values automatically, stepping through higher or lower increments. Other physical attributes can be manipulated as well to change aspect ratios, die size, macro grouping, macro packing, pin locations, etc.

This image shows three unique production-quality floorplans in parallel based on different recipes. Jilla says that real customer experiences have shown that Oasys-RTL reduces the time required to generate production quality floorplan to a matter of days.

The analyses generate reports that can be saved to a comma separated values (.csv) file to import into a spreadsheet. The CSV format can further be employed to create graphs, charts and scatter plots to help visually analyze the metrics. From this vantage point, managers can decidedly select the best power, performance, or area.

To learn more about the getting the best PPA with Oasys-RTL’s design space exploration, download the new whitepaper from Mentor.


A Peek Inside the Global Foundries Photonic Death Star!

A Peek Inside the Global Foundries Photonic Death Star!
by Mitch Heins on 11-03-2016 at 12:00 pm

Last week I wrote about the Photonics Summit and hands-on training hosted by Cadence Design, PhoeniX Software and Lumerical Solutions and in that article I mentioned that Ted Letavic of Global Foundries laid out a powerful argument for why integrated photonics is a technology that is going main stream. This article dives into more details from Ted’s presentation. There are some basic misconceptions about photonics that need to be cleared up and Global Foundries did a good job of doing that in Ted’s presentation.

The first misconception is that integrated photonics will be a small niche market. Ted did a nice job of pointing out that the major growth driver for photonics will be cloud-based computing. Up to 75% of enterprise IT deployments are now hybrid-Cloud based. Cloud deployments are driving most of the server, network and storage growth, and it’s that grow that will drive a 10X growth in data center traffic over the next five years. Mobile data is another contributing part of this growth and it alone is forecast to grow at an astounding 53% CAGR from ~6 exabytes (EB) in 2016 to over 30 EB in 2020. In conjunction with greater data volumes comes the need for greater data bandwidth and flexibility. Ted noted the two biggest drivers for increased bandwidth as being the new 5G standard for cellular networks and the dis-aggregation of the data centers with suppliers moving away from super centers to many smaller centers that are connected together with high band-width networks. Both of these drivers will require increased bandwidth density and speed and decreased latency. With this in mind, networking bandwidth is forecast to double every two years for the foreseeable future and integrated photonics will be the prevalent solution in all areas of networking for telecom (long and short haul), mobile networks and data centers. Transceivers alone for telecom and datacom are forecast to be a $3B market by 2020.

The second misconception is that integrated photonics is still in the labs and hasn’t made it to the production fabs. Global Foundries made it abundantly clear that they are ready to take production runs in as many as three different fabs (Fishkill 90nm/300mm, Burlington 90nm/200mm and Singapore 45nm/200-300mm). All of these fabs are able to run SiGe (silicon germanium) on SOI wafers and support PDKs with all of the necessary components for integrated photonic designs including vertical grating couplers, low loss edge couplers, dense high-contrast waveguides and passive components as well as high-speed active modular and photo detectors.

A third misconception about integrated photonics is that because photonic components are large in comparison to their transistor counterparts that 300mm lines would be overkill for such devices. As it turns out, signal loss is a key concern of large photonic circuits and many of the major sources of loss such as line-edge roughness in waveguides, alignment errors at junctions, and line-edge placement errors of resonant structures caused by poor critical dimension (CD) control, can be mitigated by 300mm tooling. Global Foundries showed results comparing their 200mm and 300mm tooling with the 300mm lines having a 3-5X reduction in CD and overlay errors, 2.5-3X reduction in line-edge roughness and a 4-5X reduction in CD and overlay errors in modulators giving them a substantial boost in their RF definition. This tooling combined with judicious optical proximity correction (another staple of 300mm processing) makes for a very low loss photonic platform.

A last misconception about integrated photonics is that monolithic solutions combining electronics and photonics are a long way off. Global Foundries has a solution now, says Letavic. Global Foundries’ offering boasts monolithic and hybrid process integration including high bandwidth RF and Analog for broadband systems and 5G synergy. To strengthen their offering, Letavic also pointed out that Global Foundries has a wealth of capabilities for handling advanced packaging (C4/Cu pillars, TSVs and MCMs) and test requirements and have included support for integrated photonics by adding lower-cost passive fiber alignment-and-attach technologies and surface grating couplers for inline on-wafer testing.

Letavic rounded out his presentation by outlining the fact that they have PDKs for their capabilities now that are compatible with the Cadence, PhoeniX, Lumerical EDPA (electronic-photonics design automation) flow covered by the rest of the photonic summit.

As I mentioned in my last article, this truly is a watershed event for photonics. The AIM Photonics effort in the U.S. needed a production fab into which designs could go from prototype to production and now they have not one, but three!

Also Read: The Fabless Empire Strikes Back, Global Foundries and Cadence make moves into Integrated Photonics!


Always-On IoT – FDSOI’s Always Better? What About Wafers? (Questions from Shanghai)

Always-On IoT – FDSOI’s Always Better? What About Wafers? (Questions from Shanghai)
by Adele Hars on 11-03-2016 at 7:00 am

Mahesh Tirupattur, EVP at low-power SERDES pioneer Analog Bits lead off the panel discussion at the recent FD-SOI Forum in Shanghai with the assertion that for anything “always on” in IoT, FD-SOI’s always better. They had a great experience porting their SERDES IP to 28nm FD-SOI (which they detailed last spring – see the ppt here). The port from 28 bulk to 28 FDSOI took 2 1/2 months (vs. to FinFET, which took almost 6). Even without using body bias, they got performance up by around 15% and leakage down by about 30% (he added that with body bias, they could get five times that).

He compared porting to FD-SOI to playing high school ball, vs. a port to FinFET which is like competing in the Olympics. ESD was different, but not a big deal – you just need to “read the manual”. Heating? Nothing an engineer can’t resolve. For IoT, FinFETs are like using a cannon to shoot a mosquito, he quipped.

He later ticked off a few more advantages of FD-SOI for the IoT design community: system cost, lower power – and here’s a particularly interesting observation – cheaper packaging. They were able to do wire bonding, so they were able to package a wearable video app in a plastic capsule. All things considered, FD-SOI offers the perfect solution, he said (and now he’s got silicon with “dramatic results” to prove it), adding that the IP guys need to evangelize this.


Shanghai FD-SOI Forum Panel Discussion (left to right): Wayne Dai, CEO Verisilicon (moderator); Marshal Cheng, SVP Leadcore; Mahesh Tirupattur, EVP Analog Bits; Subramani Kengeri, VP GlobalFoundries; Handel Jones, CEO IBS; Christophe Maleville, VP Soitec. (Photo courtesy SOI Consortium and Verisilicon)

Moving really fast
GloFo VP Subramani Kengeri took a moment to look back before he looked forward. “FD-SOI is not new,” he reminded the audience. It was explored and researched for a decade. But at the beginning, CPUs were driving the industry, and everyone else followed suite. But now in mobile and IoT, RF is becoming more important, and what was good for the CPU is no longer what’s good for everything else. He tipped his hat to Soitec, ST and Leti, who “kept the lights on” and kept driving FD-SOI forward. Now with 5G on the horizon, FD-SOI is the enabler, he added.

He also noted that FD-SOI gets you the maximum memory onchip, and that with 12FDX, we’ll be seeing the world’s smallest SRAM. So that opens a new degree of freedom. The EDA partners have been working on automating body bias in the PDK for greater power management. He cites an ARM core with on-demand performance that can be used “intelligently”. Is it complicated? Not really, he says, especially if it’s automated. In fact he sees body bias opening the market for “extraordinary, innovative products” very soon. Key IP is in place. And it’s not just for IoT: if you don’t count high-end CPUs, FD-SOI is optimal for everything. “Everything’s happening now, and it’s moving really fast,” he said.

Clear substrate path to 7nm
SOI wafer leader Soitec VP Christophe Maleville was asked if he saw any limit on manufacturing the ultra-thin wafers for the 7nm node. No problem, he said – they can do those wafers with 4nm of strained top silicon and a 10nm layer of insulating BOX. They’ve been working on FD-SOI wafers for over a decade, he said, with Leti, IBM and ST. Back in 2013 when ST announced the Nova-Thor hitting 3GHz (or 1GHz at just 0.6V) on 28nm FD-SOI, everything was in place: the metrology was ready, reliability was controlled.

Today they’ve got a 15nm BOX layer in manufacturing, with no limits in moving to 10nm for customers going for very low power. For the strained top silicon needed for the 7nm node, they spent years working on strain with IBM et al in Albany, so they’re not starting from scratch. That substrate will be mature in just two years, so from a substrate point of view, he said, “7nm is no problem”.

Coming fast: lots of products (and a fab for China?)
In response to a follow-up question from a well-known financial analyst covering the China tech industry, panel moderator and Verisilicon CEO Wayne Dai said that the design community in China has the skills to do FD-SOI, no problem. He’d like to see more IP, but FD-SOI has powerful advantages in terms of cost, analog, memory and back biasing.

Dai then asked the panelists if they thought we’d be seeing a foundry in China opting for FD-SOI next year – all but one said yes. One thing all the panelists agreed on, however: they all expect to see FD-SOI products (and lots of them) on the stage at the Shanghai FD-SOI Forum in 2017.


Protium for the win in software development

Protium for the win in software development
by Don Dingee on 11-02-2016 at 4:00 pm

Cadence Design Systems is a long-standing provider in hardware emulation, but a relative newcomer to FPGA-based prototyping. In an upcoming lunch and learn session on November 11 in San Jose, Cadence teams will be outlining their productivity strategy. What’s different with their approach and why is this worth a lunch? Continue reading “Protium for the win in software development”


Keeping It Fresh with the Veloce Deterministic ICE App

Keeping It Fresh with the Veloce Deterministic ICE App
by Rizwan Farooq on 11-02-2016 at 4:00 pm

In The Times They Are A Changin’ Nobel Laureate Bob Dylan advised us to “heed the call” of change or suffer the consequences. This couldn’t be more true, considering what design and verification engineers face every day in the midst of the technological revolution.

Change has never been so rapid. And it requires we constantly adapt. Within the world of emulation, we are witnessing tremendous efforts to keep pace, making emulators more useful, more available, and more efficient. Virtualization and around-the-clock, concurrent availability of emulator resources to multiple project teams are primary strategies for better serving global design teams and the growing number of emulation use models and applications.

Yet traditional ways of doing things continue to have value. For example, in-circuit emulation (ICE) is needed for many SoC verification scenarios. Used to exercise a design under test (DUT) by connecting physical targets to an emulator, ICE delivers the significant advantage, among other things, of being able to run real-world usage scenarios before tape-out.

However, even when it is advantageous to use an ICE-based verification environment, verification engineers face four challenges:

  • Insufficient trace depth
  • Iterative and long debug cycles
  • Randomness
  • Lack of flexibility

To address these debug challenges, and keep ICE current with modern design and verification trends, Mentor developed the Veloce® Deterministic ICE App.

The Veloce Deterministic ICE App takes the randomness out of ICE, dramatically shortening the time to find and fix bugs. It delivers a repeatable and virtual debug flow for an ICE-based environment. It addresses debug limitations, including randomness, by creating a virtual debug model of an ICE run and generating a replay database to repeat a test without cabling to physical ICE targets.

Figure 1: The Veloce Deterministic ICE App use model.

The Veloce Deterministic ICE App use model is very simple. To generate a replay database, you specify your requirements and enable the Veloce Deterministic ICE App replay mode. Veloce generates the replay database while it runs the standard ICE test case with the ICE targets connected. Once the run is complete, the test case can be run as often as necessary using the replay database without the use of ICE targets.

Figure 2: Veloce Deterministic ICE use model.

Because the replay database has eliminated the use of ICE targets, you can run this database on any Veloce hardware. The emulator ICE targets are freed up for use by other project teams, and you can stop a run and inspect both data and full waveforms. This provides a rich debug platform and increased productivity in addition to efficient use of emulation resources.

The Veloce Deterministic ICE App also enables advanced debug methodologies like assertions, protocol monitors, and $display, which are commonly used in today’s advanced verification methodologies. You can also do power analysis, coverage closure, and offline SW debug using the Veloce Deterministic ICE App within an existing ICE setup.

To find out more about how the Veloce Deterministic ICE App improves your debug productivity and helps your team get the most out of your emulation resources, download the new whitepaper Using the Veloce Deterministic ICE App for Advanced SoC Debug.

“If your time to you is worth savin’” you’ll be glad you did.


Medicine will advance more in the next 10 years than it did in the past century

Medicine will advance more in the next 10 years than it did in the past century
by Vivek Wadhwa on 11-02-2016 at 12:00 pm

Mark Zuckerberg and his wife, Priscilla Chan, recently announced a $3 billion effort to cure all disease during the lifetime of their daughter, Max. Earlier this year, Silicon Valley billionaire Sean Parker donated $250 million to increase collaboration among researchers to develop immune therapies for cancer. Google is developing contact lenses for diabetic glucose monitoring, gathering genetic data to create a picture of what a healthy human should be and working to increase human longevity.

The technology industry has entered the field of medicine and aims to eliminate disease itself. It may well succeed because of a convergence of exponentially advancing technologies, such as computing, artificial intelligence, sensors, and genomic sequencing. We’re going to see more medical advances in the next decade than happened in the past century.

We already wear devices, such as the Fitbit and Apple Watch, which monitor our physical activities, sleep cycles, and stress and energy levels and upload these data to distributed servers via our smartphones. And those smartphones contain countless applications to keep track of our vitals and gauge our emotional and psychological states.

Then there is sequencing of the human genome, first completed in 2001 at a cost of about $3 billion. It’s possible today for about $1,000, with costs falling so fast that, by 2022, genome sequencing may be cheaper than a blood test. Now that it has been mapped into bits that computers can process, the genome has become an information technology.

With increasingly large sample sizes and tools such as IBM’s A.I. system, Watson, scientists are gaining an understanding of how our genes affect our health; how the environment, the food we eat, and the medicines we take affect the complex interplay between our genes and our organisms.

The next big medical frontier is on the horizon: our microbiomes, the bacterial populations that live inside our bodies. We may think we are just made up of cells, but in reality there are 10 times as many microbes in our body as cells. This is a field that I am most excited about, because it takes us back to looking at the human organism as a whole. The microbiome may be the missing link between environment, genomics, and human health.

Some children, for example, are born with a genetic predisposition to type-1 diabetes. Researchers tracked what happened to the stomach bacteria of children from birth to their third year in life and found that those who became diabetic had suffered a 25 percent reduction in their gut bacteria’s diversity (possibly from antibiotics). In another study, on Crohn’s disease, scientists took a small sample of feces from a healthy person and gave it in an enema to somebody with Crohn’s. Though that seems a disgusting procedure, it proved extremely effective in curtailing the condition. Scientists are also finding a correlation between the microbiome and obesity. It may well be the bacteria in our guts that make us fat — not just the food we eat.

Within a few years, our genome, microbiome, behavior and environment will all be mapped and measured, and prescriptive-medicine systems based on artificial intelligence will help us feel better and live longer.

The most amazing — and scary — genetics technology of all is CRISPR. It uses an enzyme, Cas9, that homes in on a specific location in a strand of DNA and edits it to either remove unwanted sequences or insert payload sequences. With it, Chinese scientists have genetically modified pigs, goats, monkeys and sheep to change their size and color. They also claim to have edited a human embryo for resistance to HIV. For better and for worse, CRISPR has the potential to eliminate some debilitating diseases and to create a species of superhumans. And it is so cheap and easy to use that hundreds of labs all over the world are experimenting with it.

There are also advances in 3D-printed prosthetics and bionics. One company, UNYQ, for example, is “printing” new limbs for people with disabilities. Ekso Bionics has developed robotic exoskeletons to help the paralyzed walk again. Second Sight is selling an FDA-approved artificial retinal prosthetic, the Argus II, which provides limited but functional vision to people who have lost their vision due to retinitis pigmentosa, a retinal ailment. I expect that, by 2030, we will have developed enhancements that give us perfect vision, hearing, and strength as seen in the 1970s television series, “The Six-Million Dollar Man.”

Yes, it will take time for the inventions to get from the lab to people in need, and the technology elite will have these before the rest of us. But this will only be for a short period, because the way the tech industry builds value is by democratizing technology, reducing its cost and enabling it to reach billions. This is why I am so excited that companies such as IBM, Facebook, and Google are taking the mantle from the health-care industry. These companies have a motivation to keep us healthy: so that we download more applications rather than remain hooked on prescription medicines.

This column is based on my upcoming book, “Driver in the Driverless Car: How Our Technology Choices Will Create the Future,” which will be released this winter–and you can preorder on Amazon.com


AI on the Edge

AI on the Edge
by Bernard Murphy on 11-02-2016 at 7:00 am

A lot of the press we see on AI tends to be of the “big iron” variety – recognition algorithms for Facebook images, Google TensorFlow and IBM Watson systems. But AI is already on edge-nodes such as smartphones and home automation hubs, for functions like voice-recognition, facial recognition and natural language understanding. Qualcomm believes there are good reasons for functions like this not only to stay on the edge but to continue to evolve there. I talked with Gary Brotman, director of product management at QTI to understand what’s driving this trend.

Part of the reason is availability. Carrier claims notwithstanding, there are still plenty of places you can’t get cellular or WiFi coverage. That might not be a huge deal for image recognition in Facebook photos, but it becomes a very big deal if you use biometric id(s) to unlock your phone or perform other critical functions. Which makes it a big deal in the rural/ mountainous/ heavily wooded areas that still account for the great majority by area of the US. Even urbanites accustomed to gigabit access can feel this pain when travelling any distance across country.

Part of the reason is privacy. If your dermatologist wants to use a mobile diagnostic device to check a possible melanoma, you have a right to expect that data will be handled with extreme care and especially that it won’t be shipped off to the cloud for analysis.

And part of the reason is security. No matter how great your hardware security may be, there are plenty of holes in software, and traditional signature-based approaches to malware detection are too cumbersome, too power-hungry and too slow to change to be effective against zero-day threats.


This is not an academic concern. Gary mentioned an IDC survey reporting that while less than 1% of applications use cognitive (aka AI) technologies today, more than 50% are expected to have that capability by 2018. The demand for cognitive-enabled functions is rocketing and if at least some of that capability has to be able to work untethered from the cloud, effective local solutions become essential.

Of course this doesn’t mean that everything has to be done locally. Training for deep-learning and related methods still happens in the cloud. But once training is downloaded, recognition should be able to function independently. If permitted, new data to enhance the training dataset can be uploaded when feasible, as Tesla does in gathering data from customer vehicles.


What powers this local analysis? Gary repeated a point he and others made on a panel earlier in the day. While there are now commonly-used hardware platforms for cognitive applications (CPU, GPU and DSP for convolutional and recurrent neural nets, along with frameworks like Caffe and Cuda), the bulk of application know-how today is still in software, not least because the domain is evolving so rapidly. Qualcomm sees platforms like their Machine Learning Platform as the best way to deliver a foundation for application developers. An SDK and frameworks offered within that SDK hide the gory details of implementation from the developer and can provide some level of future-proofing from changes in the underlying technology.

One example application can be found in Snapdragon™ Smart Protect. This is malware detection which uses not signatures for malware but rather machine-learning-based behavior triggers to protect against multiple types of attack and particularly against zero-day attacks. This is clever stuff. Signature-based approaches are impossibly clunky for mobile devices, are too easy to fool through mutating malware and cannot defend against zero-day attacks. Smart Protect behavioral detection looks instead at ~360 low-level behaviors which are harder to hide if the malware wants to achieve its intended objective (some examples cited include sending text messages when the user is not interacting with the device or taking photos when the display is off).

Finally, Gary noted that, to further support this trend to more processing (including AI) on the edge, Apple recently announced their position on “differential privacy” – the need to keep customer personal data out of their hands. Whatever you may think of Apple’s announcement, the principle they support is important. What we would consider personal used to be logins, passwords, bank data and other forms easily reduced to text. But increasingly we need to worry about information for facial recognition, typing behaviors, voice recognition and other biometrics which seem more abstract but could be just as damaging if leaked beyond our devices. I like what Qualcomm is doing; I might lose my phone or it might be stolen but I still have a better sense of control over something I can hold than over what ever might be happening in some distant cloud.

You can learn more about the Qualcomm Machine Learning Platform HERE.

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