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The Failure of IoT Platforms

The Failure of IoT Platforms
by Glen Allmendinger on 12-01-2016 at 7:00 am
Categories: IoT
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Creative Evolution and the Post Platform Era
When telephones first came into existence, all calls were routed through switchboards and had to be connected by a live operator. It was long ago forecast that if telephone traffic continued to grow in this way, soon everybody in the world would have to be a switchboard operator. Of course that did not happen because automation was built into the systems to handle common tasks like connecting calls.

We are quickly approaching analogous circumstances in the IoT arena with the proliferation of connected devices. The tools we are working with today to make products “smart” were not designed to handle the diversity of devices, the scope of interactions and the massive volume of data-points generated from devices. Each new device requires too much customization and maintenance just to perform the same basic tasks. These challenges are diluting the ability of organizations to efficiently and effectively manage development.

Today, platforms for the Internet of Things are still a kludgy collection of yesterday’s technology and architectures that do not address the most basic development challenges. Even though many companies are telling fantastic IoT marketing stories about what their solutions can do, you wouldn’t know it from today’s fragmented collection of incomplete platforms, narrow point-solutions, and software incompatibility.


We need better software to empower users and developers to exploit the vast potential of the Internet of Things.

Download Our Storyboard on IoT Frameworks

We’re Having a Crisis of Perception About “Future Computing”
In times of radical change, crises of perception are often the cause of significant failures, particularly in large established companies. Such failures result from the inability to see emergent discontinuities. We believe this is the case with most large developers and suppliers of technology attempting to address the emerging Internet of Things opportunity. Many players’ assumptions about future architecture for Smart Systems are being shaped by the past and are being extrapolated into the future in a linear fashion. Most of the large established IT equipment, software and network players appear to be stuck in this tyranny of replication.

Today the world of smart communicating devices is mostly organized in hierarchies with smart user interface devices at the top and the dumb devices [often analog or serial sensors and actuators] at the bottom. Within this structure, there are typically various types of “middle box” supervisory and gateway devices forming a point of connectivity and control for the sensors and actuators as well as the infrastructure for the network. From our perspective, this description of today’s IoT systems architecture looks very familiar and is largely organized like client-server based computer systems….. no surprise given they were designed in the 1990′s.

As the Internet of Things opportunity matures, the sensor and actuator devices will all become smart themselves and the connectivity between them (devices, for the most part, that have never been connected) will become more intelligent and the interactions more complex. As the number of smart devices grow, the existing client-server hierarchy and the related “middle boxes” acting as hubs, gateways, controllers and interfaces will quickly start to blur. In this future-state, the need for any kind of traditional client-server architecture will become superfluous. In a future Smart Systems world, the days of hierarchical models are numbered.

We can now begin to imagine an application environment where there will be widely diverse operational technology (OT) computing devices running applications dispersed across sensors, actuators and other intelligent devices sharing and leveraging the compute power of a whole ‘herd’ – a smart building application, for example, where the processor in an occupancy sensor is used to turn the lights on, change the heating or cooling profile or alert security.

In this evolving architecture, the network essentially flattens until the end-point devices are merely peers and a variety of applications reside on one or more [OT] computing devices. In a smart systems application designed to capture, log and analyze large volumes of data from sensors, such as we are describing here, peer computing devices will carry out the process of taking raw data and distilling it into information “locally.” Local processing is required to reduce the otherwise untenable Internet traffic challenges that arise from connecting billions of devices.

This is the move we’ve been waiting for…….. to a truly distributed architecture because today’s systems will not be able to scale and interact effectively where there are billions of nodes involved. The notion that all these “things” and devices will produce streaming data that has to be processed in some cloud will simply not work. It makes more sense structurally and economically to execute these interactions in a more distributed architecture near the sensors and actuators where the application-context prevails.
Dispersed computing devices will become unified application platforms from which to provide services to devices and users where the applications run, where the data is turned into information, where storage takes place, and where the browsing of information ultimately takes place too – not in some server farm in a cloud data center. Even the mobile handsets we admire so much today are but a tiny class of user interface and communications devices in an Internet of Things world where there will be 100 times more “things” than humans.

From our view the movement towards peer-to-peer, and the view that many people hold that this is somehow novel, is ironic given that the Internet was originally designed for peer-to-peer interactions. We seem to be heading “back to the future.”

Today’s IoT Platforms Don’t Liberate Data; They Trap It
In the course of the last two decades, the world has become so dependent upon the existing ways computing is organized that most people, inside IT and out, cannot bring themselves to think about it with any critical detachment. Even in sophisticated discussions, today’s key enabling information technologies are usually viewed as utterly inevitable and unquestionable.

The client-server model underlying today’s computing systems greatly compounds the problem. Regardless of data-structure, information in today’s computing systems is machine-centric because its life is tied to the life of a physical machine and can easily become extinct. With today’s IoT platforms information is not free (and that’s free as in “freedom,” not free as in “free of charge”). In fact, thanks to today’s platforms and information architectures, it’s not free to easily merge with other information and enable any kind of systemic intelligence.

All of this adds up to a huge collection of information-islands whether on your servers, your service provider’s servers or anywhere else. Assuming the islands remain in existence reliably, they are still fundamentally incapable of truly interoperating with other information-islands. This is the issue with all of the so-called IoT platforms that have flooded the market – they are really “data traps” and information islands. We can create bridges between them, but islands they remain, because that’s what they were designed to be.

What would truly liberated information be like? It might help to think of the atoms and molecules of the physical world. They have distinct identities, of course, but they are also capable of bonding with other atoms and molecules to create entirely different kinds of matter. Often this bonding requires special circumstances, such as extreme heat or pressure, but not always. In the world of information technology, such bonding is not all that easy.

Smart Systems requires we fundamentally change this paradigm, treating data from things, people, systems and the physical world as “neutral” representations. In other words, treating diverse data types equally. But even this makes too many assumptions about what the Smart Systems phenomenon will be. Encoded information in physical objects is also smart computing—even without intrinsic computing ability, or, for that matter, without being electronic at all. Seen in this way, a printed bar code, a DVD, a tag, a disc, a house key, or even the pages of a book can have the status of an “information device” on a network.

Today’s holdover client server architectures are just making matters worse. With each additional layer of engineering and administration, computing systems come closer and closer to resembling a fantastically jury-rigged Rube Goldberg contraption.

The reason for all of this is simple. Today’s computing systems were not really designed for a world driven by pervasive information flow and are falling far short of enabling adaptable real-time intelligence.

Creative Evolution Will Force a “Post-Platform” World
Machine learning, artificial intelligence and the Internet of Things are all in some way trying to break from today’s computing paradigms to enable intelligent real-world [physical] systems. As these devices and systems become more and more intelligent, the data they produce will become like neurons of the brain, or ants in an anthill, or human beings in a society, as well as information devices connected to each other. The many “nodes” of a network may not be very “smart” in themselves, but if they are networked in a way that allows them to connect effortlessly and interoperate seamlessly, they begin to give rise to complex, system-wide behavior that usually goes by the name “emergence.” That is, an entirely new order of intelligence “emerges” from the system as a whole—an intelligence that could not have been predicted by looking at any of the nodes individually. There’s a distinct magic to emergence, but it happens only if the network’s nodes are free to share information and processing power.
Today’s platforms for Smart Systems and the IoT should be taking on the toughest challenges of interoperability, information architecture and user complexity. But they’re not.

We need to creatively evolve to an entirely new approach that avoids the confinements and limitations of the today’s differing platforms. We need to quickly move to a “post platform” world where there is a truly open data and information architecture that can easily integrate diverse machines, data, information systems and people – a world where smarter systems will smoothly interact to create systemic intelligence – a world where there are no artificial barriers between different types of information.

In our years of experience, we have all too often seen the unfortunate scenarios that managers create when uncertainty and complexity force them to rely on selective attention. Unfortunately, when this happens, selective attention naturally gravitates toward what’s readily available: past experience, existing tools and uncertain assumptions. Today’s IT and telco infrastructure players are doing just this. By ignoring important trends simply because it’s difficult to perceive an alternative future, these managers are certainly leaving the door open for competition that will lead to their eventual obsolescence…which will make for a very interesting world to live in…

For more information on how to overcome these obstacles in the market email us

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OpenCL hits FPGA-based prototyping modules

OpenCL hits FPGA-based prototyping modules
by Don Dingee on 11-30-2016 at 4:00 pm
Categories: FPGA, S2C EDA

OpenCL brings algorithm development into a unified programming model regardless of the core, working across CPUs, GPUs, DSPs, and even FPGAs. Intel has been pushing OpenCL programming for some time, particularly at the high end with “Knights Landing” processors. Where other vendors are focused on straight-up C high-level synthesis for FPGAs, Intel is taking Altera technology deeper into OpenCL.

Using OpenCL, a developer can write an algorithm once, emulate it on a PC, then choose what hardware to run it on – or partition it across several different types of hardware depending on cost and packaging. Intel’s FPGA SDK for OpenCL helps abstract out FPGA complexity for hardware acceleration. Their compiler can perform over 300 optimizations, then synthesize the FPGA in a single step.

Several different hosts are supported, including ARM Cortex-A9 cores typical of SoCs, IBM POWER Series processors, and X86 CPUs. The solution can be scaled across multiple FPGAs, which makes it ideal for the FPGA-based prototyping scenario. Instead of taking overt partitioning steps and spreading out RTL across several FPGAs, OpenCL code distributes seamlessly across FPGA devices. This is a huge advantage for HPC teams who want to concentrate on software, not hardware, and especially not the nuances of FPGA programming.


Screenshot from video: https://www.altera.com/content/dam/altera-www/global/en_US/video/opencl-overview-tutorial.mp4

In fact, OpenCL could be one of the key differentiators between the Intel/Altera combination and the ARM/Xilinx ecosystem. There are OpenCL ports on lots of platforms since it is an open standard, but Intel has gone all in on optimization for OpenCL across the board including its FPGA offering. Combining the benefits of an OpenCL development flow with the power of an Altera Arria 10 FPGA brings a bunch of algorithm acceleration possibilities.

S2C has solved the problem of how to get many FPGAs interconnected in a single prototyping platform. With their new Arria 10 Prodigy FPGA Prototyping Logic Module, users can have anywhere from a single Arria 10 1150GX FPGA to a scaled-up system with 16 FPGAs in the Cloud Cube chassis. As the name implies, a single Arria 10 logic module has 1150K logic elements along with a full suite of programmable I/O including 48 transceivers running at up to 16Gbps, and 576 high performance I/Os. It’s an incredible leap, not only for those interested in working in the Intel/Altera environment, but for those working on OpenCL.

You can read more about the Intel FPGA SDK for OpenCL, and download a copy, here:
Intel FPGA SDK for OpenCL

For more information on the S2C Arria 10 Prodigy FPGA Prototyping Logic Module, here’s the full S2C press release:

S2C Expands Its FPGA Prototyping Library with Arria 10 Solution and Delivers Its Powerful Technology to the High Performance Computing Market

The thing about FPGA-based prototyping is it is becoming less about the FPGA and more about the software running on the platform. While the entire S2C prototyping portfolio including expansion daughter cards, configuration, and debug capability comes to bear, the real news here is how OpenCL speeds up the software development process. The shape of HPC is changing from big, expensive iron to reconfigurable, accelerated computing with FPGAs underneath the hood.

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IOT – Think Big – Start Small – Scale Quickly

IOT – Think Big – Start Small – Scale Quickly
by Bill McCabe on 11-30-2016 at 12:00 pm
Categories: IoT

There’s an old philosophy that business coaches often use. It’s the saying that you think big, start small, and then scale quickly. If you follow it closely, you have the potential to make a lasting impression in an industry and achieve actual results in the process.

Let’s look at this in terms of the internet of things to see how it pertains to this industry. The first thing we do is think big. This means to think about the transformation in the industry and how it will not only impact you, but others. With this, you’ll know what technology you need to be successful, and have the building blocks in place that others can come to you as they need your technology in order to operate more effectively.

Now that you understand the big picture, you can start small. Begin to work a process into the latest trends. Identify any weaknesses the competition has, and work to design and processes to help combat these weaknesses. Consider adjusting the structure and then release products that address these concerns. You can begin to gain attention as you do this, and others will follow your suit. Chances are, other technology companies will be willing to work with you to address their own internal concerns.

It’s at this point, you scale quickly. You begin to unroll solutions quickly, release prototypes, and aggressively work to be the leader in the industry. The goal at this time is to show you are on the cutting edge of things and to drive the process further harder. As you do this, make sure you keep looking at the future, especially since you know the direction you are taking trends and work on building from this. Even though you did start small, you have cornered a section of the market at the head. That way, people will keep looking to you in order to determine the future of things.

The thing to remember is that as long as you are innovative, and follow through with the process, there is no reason why you cannot succeed. Mobile technology has used this approach for years and it continues to propel the smart phone industry. With more devices headed toward total connectivity, it will pay to be the company who decides to start small and scale quickly, and unleash the new popular trends that will propel the internet of things into the future.

Please check out our new website for more information www.internetofthingsrecruiting.com

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Car Companies Should Steer Clear of Uber’s Red Ocean

Car Companies Should Steer Clear of Uber’s Red Ocean
by Roger C. Lanctot on 11-30-2016 at 7:00 am
Categories: Automotive

It is no secret that Uber drivers struggle to make a living driving for Uber. The most popular guidance for Uber drivers is to use the service to supplement existing income, not as a full-time job. But Uber is transforming transportation with billions of dollars of investment, billions of dollars in fares and billions of dollars of self-driving car research. Car companies wanting to participate in this transformation should beware.

Most users of Uber have had the delightful experience of chatting with Uber drivers thereby discovering usually non-professional drivers who have turned to Uber as a result of mid-career pivots or unanticipated unemployment or underemployment. The average Uber driver I have encountered around the world has usually been on the job for well under a year.

For many of these drivers taking fares from place to place is still a somewhat new and novel experience and likely one that they don’t anticipate making a permanent career choice. Also, in chatting with these drivers, you almost invariably hear the same assessment of Uber as an oppressive master constantly manipulating driver compensation and fares to manage supply and demand.

Of course, Uber’s not-so-invisible hand is often perceived as unfair and driver compensation insufficient. That insufficiency may be less than obvious, though, to an Uber driver who has not figured in the costs associated with maintaining his or her vehicle. One of the most positive aspects of the Uber experience, as a passenger, is the generally nearly-new condition of most Uber cars.

It’s somewhat sad and not unusual to see a nearly-new Toyota or Audi or Tesla racking up mileage at the rate of 25K or more within a 3-4 month period. It’s true that maintenance intervals for new cars are getting longer and longer – stressing out new car dealers that depend on service revenue – but usage rates for ride hailing service providers – using their own cars – is a big red flag and usually the final straw that breaks the back of the business model.

This is just one of many reasons behind the high rate of churn of Uber drivers. It is also the reason behind Uber’s widening efforts to put drivers who don’t even own cars into leased or rented vehicles. Of course, this strategy simply substitutes the additional cost of the lease or rental for the burdensome cost of vehicle maintenance – all to overcome the diminishing pool of available or interested drivers.

Of course, in some markets, where the demand is high, there are too many drivers. This, too, contributes to the churn challenge and the inability to make a living.

But my real motivation for writing this brief note is the fact that Uber is using its drivers to help build the infrastructure that will put these drivers out of work entirely. Uber is putting a sizable chunk of its investor capital into developing driverless cars – and the data gathered from its test mules and existing vehicles will be used as part of that development effort.

In effect, Uber is using the independent weavers to build the looms that will put them out of business – to make a slightly tortured analogy to the 19th century Luddite movement in Northern England.

A car maker I was chatting with yesterday described the Uber and Lyft ride-hailing sector as a Red Ocean – as part of describing why his company was not planning to subsidize Uber or Lyft leases, or invest in either of these companies. A red ocean is a market where everyone is talking a different version of the same thing versus a blue ocean which is an uncontested market sector.

I had to chuckle, because, unfamiliar with the expression “red ocean” I simply envisioned a sea of “red ink,” which is in fact what Uber has been producing in its run up to ad hoc transportation domination. The whole concept of Uber seems intended to undermine both the taxi and rental car industries using financially oppressed drivers offering untenably low fares.

We know how this ends. Existing services are disrupted. Professional people and organizations may be forced out of work or out of business. The insurgent takes over and new forms of discrimination and pricing emerge.

Uber’s reason for being is predicated upon a variety of shortcomings all or some of which may exist in a particular market including: poor taxi availability, high fares, poorly trained or rude drivers, and dirty, old or poorly maintained vehicles. Given the wide disparity in the quality and availability of taxi services around the world, I understand the convenience, economy and efficiency offered by Uber.

At the same time, I depend upon those taxis lined up at airport taxi ranks to be there when I need them. Uber threatens the availability of those taxis at the expense of drivers who have a limited professional stake in delivering me to my destination.

Under these circumstances it is probably best for car companies to steer clear of the Uber’s of the world. The auto industry is in transition from a B2B to a B2C business where direct interaction with consumers will increasingly be the rule.

Car companies are naturally allied with the taxi and rental car industries. Collaboration with these incumbents to create more customer friendly offerings makes much more sense to me.

But don’t take it from me. Hail yourself a taxi instead of an Uber today. You may have to download a different app to do it. But chances are you will get a professional driver in a well maintained car who will know your destination without the need of a map and most likely speaks your language.

I truly enjoy chatting with Uber drivers – but I feel the most sympathetic thing I can do for them is to not encourage them. It’s a lousy living and the employer is actively seeking to put them out to pasture.

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Expert Interview: Rajeev Madhavan

Expert Interview: Rajeev Madhavan
by Daniel Nenni on 11-29-2016 at 12:00 pm
Categories: CEO Interviews, EDA

This blog was originally posted on Paysa.com but since Rajeev Madhavan is one of our EDA Heroes I thought it was worth a re-post. In case you do not know Rajeev, he started his EDA career at Cadence then was co-founder and VP of Engineering at LogicVision (acquired by Mentor). Next he was Founder, President, and Chairman of Ambit Design Systems (Acquired by Cadence) and finally he was Founder, Chairman and CEO of Magma Design Automation (Acquired by Synopsys):

Rajeev Madhavan is a Founder and General Partner at Clear Ventures. With $120 million of capital, Clear is a VC firm that is purpose-built to help startup teams win in business technology and services.

We recently asked Rajeev for his advice to recent graduates in the engineering field on best practices for their career and what the steps to success look like. Here’s what he had to say:

Tell me about your early years and how they contributed to who you are today?
When I was a kid, I absolutely loved reading comic books. I would go through comic books quickly, reading the latest edition and be ready for the next, but my dad was not a fan of comic books. So, I built a lending service on the school bus – I charged a small fee to read my comic books—which enabled me to support my hobby. It was a comic book business with a few friends. We started to run into trouble when it came to collection though, especially with the bigger kids. We solved the problem by getting one of the bigger kids to collect for us, with a deal that he would get to read the books first. However, the school principal caught us and we were suspended from the school bus. It took away all business interests in me for quite a while!

What business lessons did you learn?
This very early business-building experience taught me several business basics. I learned valuable practices like how much money to charge, the delicate art of money collection and, perhaps most importantly, the role of rules and regulations in business. Even the suspension in that story had a critical effect on how I operate in a business setting.

Who has been your biggest influence?
There were 3 people who contributed to my successes – one was my manager, Ed Vopni at my first job – he challenged me to execute better, work harder and set better goals for myself. Another was Lucio Lanza who I met when he was an Executive VP at Cadence and a General Partner at USVP. His questions on various ideas that were being proposed to him made me want to think of doing startups. The last person was Jim Solomon, founder of Cadence who told me when we were on a customer trip to Florida, that he should have done the analog business at Cadence (the business group I was in) as a new startup – this made me realize that I am better off doing a startup. Hit with that deep desire, I joined with two others to do my first startup, LogicVision. One year into it, we had a product and our first customer, Apple. During that time, I learned that creating technology is not enough. Extracting value is what is the most important. I then started Ambit Design Systems, and Ambit was sold to Cadence for $280M. Then I started Magma, which went public on NASDAQ and was eventually acquired in 2012 by Synopsys for $650M.

What motivates you to succeed?
I love to compete. So, the fact that 30 VC firms turned me down when I was looking for funding for Ambit Design was an invitation for me to prove them wrong. Being able to show them I could succeed in spite of this was incredibly rewarding for me.

I also love the opportunity to create a new, exciting product and bring it to life. The mantra has always been that failure is not an option. As an entrepreneur, I believed that I needed to find a way to make it, whether that means needing to pivot, redoing or changing direction.

What career and life advice do you give to new college grads?
Not everyone is built to do a startup. Some may want to work in a large company because it offers stability and less risk. There is nothing wrong in choosing either of these paths. But if you truly want to pursue a startup in the tech space, Silicon Valley is the place to be. Building great relationships is important. Doing a self assessment of your strengths and weaknesses and building a team that addresses your weaknesses is very important. It takes a village to succeed and the invaluable, supportive infrastructure here will help pave your way to success, if you tap into the right relationships. In the same vein, you should take any opportunity that presents itself to build your network.

How do you define success?
Success means different things for different people.

To me, success meant success for all the people in the village that helped build the company. Success means having happy customers who rely on you to do key pieces of their day to day tasks and ultimately success to me implies changing the status quo.

Ensuring that everyone succeeds with you is something which is important to any good entrepreneur. After all is said and done, ask yourself, “Have I done the right things to make sure that my employees have been rightfully rewarded? Am I helping them to succeed too? Have you built a culture that ensures people can provide their honest, open feedback to improve the company?”

Do you have a mentor and if so who is it?
I have been lucky that in the Silicon Valley Village, I have had great mentors during my startup days. Mark Perry, now a retired General Partner at New Enterprise Associates, has given me several pieces of advice about how to put the right systems in place for my company. He also helped me understand the complex financial and legal sides of business.

Andy Bechtolsheim was also an important mentor for me. I always got a lot of much appreciated advice, which was always great, to the point, and highly relevant.

What do you think of the opportunities out there today for engineers and their salary and career potential?
In the valley, engineers carry tremendous value. It’s important for every engineer to know his or her true worth and that over time, that worth increases. It’s easy for engineers to move from company to company to company. There is a lot of distraction out there. It’s great to have the opportunity, but it’s important to assess all angles of a career move before taking the leap. A bigger project name might be appealing, but the management might not be a culture fit. You should stay focused on what really matters to you in your career. Seeing an opportunity for engineers to understand their true worth, prompted us to invest in Paysa.

What is the one piece of advice you’d give to young, entrepreneurial-minded engineers who want to launch a company?
Know your strengths and weaknesses from the get-go, but also know what resources you have at your disposal. Improve and cultivate the appropriate skills you need to succeed. Leverage the experience and knowledge of your team and look for opportunities within your desired startup arena. Building a cohesive unit and having the right co-founders often creates the best outcome.

What are you passionate about outside of your career?
I’m passionate about gardening. I started with 3 or 4 rose bushes in my first house. Now I have 400 varieties of roses and 2,000 bushes in my home. Walking around in the garden always has calmed me and given me peace of mind. So for me, gardening is a past-time that helps balance the immense pressure of the start-up world. That being said, I still haven’t been able to shake my competitive nature to my wife’s dismay – even in my gardening. I see beautiful places like Filoli Gardens and feel determined to out-do their roses.

What were your best/worst subjects in school?
My best subject was math, and all language classes were a challenge for me.

Why did you choose your profession?
I did not have much of a choice – I had a tiger mom who wanted me to be an engineer or doctor – I could not stand blood, so engineer it became. Half way through I wanted to become a CPA (called CA in India). Luckily my dad made me realize that I was too close to finishing to quit. I coasted through to my first job at Bell Northern Research and had the right manager to light up the fire. I knew I had an entrepreneurial streak in me though, dating all the way back to my comic book business. I believe that entrepreneurial spirit is inherent to a degree. The first chance I had to pursue something entrepreneurial, I ran with it. I only worked two years with large companies, but the rest of my career has been in startups.

What do you think about most of the day?
With my current companies, think about new technologies I’ve seen that we could be pursuing. Silicon Valley is fantastic at coming up with new technologies that change status quo – I am lucky to be in the valley and to meet and work with world class entrepreneurs who have passion and wealth of knowledge in so many areas of technology.

Also Read:

CEO interview: Rene Donkers of Fractal Technologies

CEO Interview: Albert Li of Platform DA

CEO Interview: Mike Wishart of efabless

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How to Secure a SoC while Keeping Area and Power Competitive?

How to Secure a SoC while Keeping Area and Power Competitive?
by Eric Esteve on 11-29-2016 at 7:00 am
Categories: IP, Security, Synopsys

I have attended LETI conference last June and remember the paper presented by Alain Merle, their security guru. Alain said that smart cards are secured because up to 50% of the Silicon area is dedicated to security. When you design a SoC to address applications like smart metering, NFC payment or embedded SIM, you know in advance that these will require more protection, but your challenge is to define a competitive architecture.

The chip area may increase if you implement certain feature in H/W instead in S/W to improve the level of security, but if your architecture is smart enough, the chip area will not necessarily double. Synopsys is proposing a good illustration of this concept with the Trusted Execution Environments (TEE), allowing creating a secure perimeter in the SoC. If TEE is still unclear for you, take a look at the picture below, or, even more efficient, listen to thiswebinar “Balancing Advanced SoC Security Requirements with Constrained Area and Power Budgets”.


There’s different ways of implementing a trusted execution environment. A simple way would be using a physical separate module, or on a SoC, use a separate CPU. But a more efficient solution, instead of using a second CPU or even a separate module, is when the trusted and the normal computation can be combined on a single processor.

The designer can define a secure, isolated area of the processor to guarantee code and data protection for confidentiality and integrity where you can securely run software, trusted software. So, the environment basically guarantees confidentiality, integrity, and authenticity of the software running in that trusted execution environment. The designer can now separate the application in parts that are less security critical and parts that are more secure critical. For the less secure critical, you apply normal software engineering. For the highly secured or the highly secure critical part, you can do additional security hardening.

The memory is protected by using secure MPU with per region scrambling protects memory based on privilege levels based on privilege levels. Accesses to secure peripherals and system resources are restricted by using secure APEX or system bus signaling. In secure mode, the Trusted Execution Environment can’t be accessed from the peripherals.

Synopsys ARC processors are actually extendable processors as users can (at design time) add their own instructions, this is APEX technology: ARC processor extensions. Access to those extensions can be controlled making the extensions very secure by using SecureShield technology. SecureShield enables you to combine trusted and normal applications on a single processor, and resources can be shared.

ARC EM CPU pipeline has been designed to be tamper resistant as there is no store in the 3-stages pipeline. The CPU can detect tampering and software attacks, thanks to integrated watchdog timer detecting system failures and enable counter measures.

In fact, ARC-EM Enhanced Security Package interleaves protected processor pipeline registers and in-line instruction and data encryption ensure decrypted instructions are never stored or accessible, protecting algorithms from reverse engineering without impact to the timing of instructions. Sourcing both the processor IP and the security package to the same provider is the key for maximum protection allowing optimized implementation, reducing area and power consumption.

The Enhanced Security Package with SecureShield is a part of Synopsys’ comprehensive portfolio of security IP solutions, which also includes the CryptoPack option for ARC EM processors as well as the DesignWare Security IP solutions, which comprise a range of cryptography cores and software, protocol accelerators, root of trust, platform security and content protection IP. On top of these security hardware features, Synopsys provides content protection, platform security and cryptographic cores. The designer will benefit from common crypto algorithms such as AES, 3DES, ECC, SHA-256 or RSA.

During this webinar, Ruud Derwig, who started his career at Philips Corporate Research, worked as a Software Technology Competence Manager at MXP Semiconductors, and now Software and Systems Architect at Synopsys will tell you many, many things about security. You will learn about side channel analysis, the non-pervasive attacks using information leaked by an implementation, like simple power analysis (SPA) or differential power analysis (PPA), which can reveal secrets, like cryptographic keys. You will also learn how to use simulation based power analysis to implement counter measures against the power analysis for data dependency.

This webinar is essential as the description of the various threats is very precise, so you clearly understand how the security can be built by using the different solutions proposed by Synopsys. Instead of providing “one size fits all” type of solutions, Synopsys propose various techniques to implement the right level of security in respect with the applications, taking into account the specific power, performance and area requirements.

You can attend to a webinar replay here.

From Eric Esteve from IPNEST

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Fabless and IDMs Training up on Integrated Photonics

Fabless and IDMs Training up on Integrated Photonics
by Mitch Heins on 11-28-2016 at 12:00 pm
Categories: Silicon Photonics

I had the good fortune to be able to attend a very informative five-day photonic integrated circuit (PIC) training this last week in Santa Clara, CA. The training was organized by Erik Pennings of 7 Pennies consulting and hosted by Tektronix. Several ecosystem partners from the design automation, photonic foundries and photonic packaging and test industries presented to a full room of more than 25 trainees from 15 different companies. The mix of companies was intriguing as there was almost an equal mix of system houses and IC providers with PIC providers outweighing the electrical IC (EIC) providers 2-to-1 and at least one of the system houses that was also doing both PICs and EICs. Of the companies doing EIC design, it was roughly an equal split between IDMs and Fabless component makers.

Training content was rich and started with a general tutorial on different types of passive and active photonic components along with basic principles behind how those components work. This was followed by an overview of the different photonic material platforms being employed for each. It was quite clear that the III-V ad II-VI group materials are here to stay for lasers, optical amplifiers and photonic detectors. There is however a definite shift underway to make use of Si and Si-based materials to enable smaller, denser and in theory lower cost photonic devices. Methods for integrating light sources and amplification to these silicon-based solutions is still up for grabs with lots of competing solutions. For detectors Ge is being grown on the Si to form SiGe based detectors.

In conjunction with the move to use hybrid photonic solutions is the push to move the photonic components closer and closer to the electronics with which they communicate. The biggest impetus for this is the next jump in modulation speed per channel. Most 100G applications are using 25Gbps channel modulation with some form of higher level encoding such as QPSK to increase effective baud rates. As the industry moves to 200G and higher rates there will be a push to move the channel speed up to 50Gbps modulation rates and when that happens there will be a push to reduce or eliminate the metal RF traces on the boards between the electronics and photonics. Flip chip seems to be the method of choice to shorten these leads by using through silicon vias (TSVs) and bump technology between the electronic-based driver chips and the photonics (see picture from Luxtera). This will however will require some help from the design automation industry to put in place more robust CAD for 2.5D and 3D design and verification methodologies.

The training rounded out with hands-on sessions from design automation vendors VPI Photonics, Lumerical Solutions, PhoeniX Software and Cadence Design who covered photonic system-level design and verification through PIC design, verification and implementation. Presentations were also given by photonic MPW aggregator JePPIX, and Si-photonics foundries CEA-Leti, imec, IHP, VTT. Presentations were also given by silicon nitride foundry LioniX as well as InP foundries HHI/Fraunhofer and Smart Photonics. Advanced photonic packaging was covered by Chiral Photonicsand photonic test and measurement were covered by Tektronix and Venista. Lastly, design housesBright Photonics and VLC Photonics each spoke about their photonic design services offerings.

Other key concepts from the training included:

  • Integrated photonic solutions may at first need to be sold at the system level. Disruptive change doesn’t happen at a single component level. It tends to impact the entire system which includes software and hardware infrastructure changes that must happen together. Look for these kind of changes from system suppliers that will use photonics to disrupt the current status quo.

  • The advent of 100G has provided great momentum for PICs especially with 100GbE (with LR4 and ER4 requiring 4 wavelength channels) and 100Gbps coherent (DP-QPSK). The volumes for these devices will be sufficient to boot up the manufacturing infrastructure to the point that other photonics markets will become cost viable. As a result, the market for PICs is now growing at >35% / year

  • Package design and 2.5D/3D integration with a mixture of EIC and PIC will become crucial to enable higher speed solutions. Thermal analysis of these modules will be important as the EICs will be generating a considerable amount of heat and designers will need tools to understand and accommodate for inadvertent heating of the photonics.

All-in-all this was a very comprehensive training class that was both wide in breadth but also comprehensive in its depth. I learned a lot and would encourage anyone interested in photonics to look into future classes offered of this nature.

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CEO Interview: Rene Donkers of Fractal Technologies

CEO Interview: Rene Donkers of Fractal Technologies
by Daniel Nenni on 11-28-2016 at 7:00 am
Categories: CEO Interviews, EDA, Fractal Technologies, IP

Fractal is another one of those very successful emerging EDA companies that you don’t read a lot about, except on SemiWiki. Rene Donkers is co-founder and CEO of Fractal Technologies, a company addressing IP quality assurance. This is a niche in the SoC tooling market that deserves some justification. Why not use an IP as-is if it comes from a trusted vendor? And if IP needs to be checked – why would you need yet another tool to do so?


What does Fractal do?
We help our customers make sense of IP they receive before they include it in their design flow. With any component you use to build your SoC, you want to make sure that everything you need is there and is consistent. Regardless of whether it came from an external supplier or an in-house design group, you cannot afford to take quality for granted. Think of trivial issues like missing pins in a Milky Way view or SPICE file. But also of trends in power and timing arcs in the terabytes of .lib files that library IP typically is made of these days. You don’t want to find something’s missing there when you’re running your final design-validation. At that stage debugging is both very hard as well as mission-critical, so catching IP issues before the IP is completely integrated is vital to our customers.

All this doesn’t sound very new, design teams have been running incoming inspection on IP for years?
We have seen all our customers transition from some form of home-grown validation scripts to a dedicated tool like Crossfire. The scripts and maintenance that used to be sufficient a few process generations ago all started to break in several places. The need for including yet another database or format was often the trigger for engaging with Fractal. The reason is that it wasn’t only the parsing and some extra checks: the checks to be run on for example CCS are far from trivial, on top of that the amount of data is huge. And then you get to fix things in a radical cost-cutting regime that leaves no resources left for proprietary tooling development. CAD-groups are simply not coping anymore without bringing in dedicated QA tooling.

There’s another aspect of IP data volume I’d like to point out, which is that you have to engineer your tools from the ground up to cope with it. Within Crossfire we have a distributed data-management framework where the different formats are managed by dedicated servers in the computing infrastructure. Once that is established, checks can be run in parallel, requesting different parts of the data when needed without being concerned with data management. This allows an extensive Crossfire check-set to be passed within a couple of hours.

More data sure, but Moore’s law is also giving us faster computers isn’t it?
Moore’s law is completely not catching up with the increase in IP data. In node-transitions during the last 2 years we have observed a 4X increase of IP data – that’s 4 TB. landing in your ‘Inbox’ to be inspected these days. Following Moore’s law, 2 years at best only doubles the amount of transistors. And that increase is mostly driven by economics, speed increases for next generation process nodes are only there in history books.

IP comes in many flavours, does Crossfire support them all? And what do you check?
In fact we do, as that is exactly how the tool has grown and matured. We started out 10 years ago with standard-cell library qualification, then added IO cells, and then moved into analog and digital Hard IP- think of memories, AD converters and physical interfaces like USB cores. Checking synthesizable IP is of course also included.

Obviously not all checks apply to all IP categories. Basics like presence-checks or terminal-equivalence are pretty universal and provide a good sanity check to start with. If timing models are provided, we make sure all arcs are present so that back-annotation will always work. Timing and power models need extensive trend checks across the 100’s of process corners for which a typical Hard-IP is characterized these days. Netlist related checks are particularly rewarding– like checking bulk connections for the different power domains. Finally we see double patterning manufacturing driving all kinds of layout specific checks that typically affect formats like LEF, layout views and GDS.

It’s important to note that all these checks and different IP formats were made for and requested by our customers. The good news is that they’re not customer exclusive in any way. By supporting and enhancing Crossfire, Fractal accumulates QA demands from the industry and is able to deliver a more complete solution with every release of Crossfire.

Does Crossfire enforce a one-size-fits-all quality standard?
That’s now how it works. it’s always the user that decides which checks to be applied to which IP. This is what we call a ‘standard’: a collection of checks to be applied, for which we have our own format called Transport. In Transport, IP users specify their QA requirements which they then communicate to their IP providers. During designing the IP, the provider already may use Crossfire to make sure the final shipment fulfills all the Transport requirements.

You can compare it to exchanging a DRC-deck between foundry and design-team: these are the rules the design-team needs to stick to if they want their GDS processed properly. For a DRC-deck, designers and foundry can have a conversation on the interpretation of certain rules. Similarly, Transport provides a communication handle between IP-designers and IP-integrators. Because of the easy-to-read descriptions in Transport and the unambiguous implementation of the rules in Crossfire it’s now possible for the first time to discuss and improve QA requirements, so parties can jointly develop improved formulations that better serve their needs. Both sides have a vested interest here, IP integrators want properly qualified IP, but overly rigorous checks do not help their suppliers in providing efficient IP releases in time.

Getting back to those design-teams that have internal qualification tools, how do you get them on board?
First of all by pointing out that we embrace and not compete with internal solutions. These internal checks have been developed to serve the specific needs of the design-flow and the application area the customer focuses on. What we’re proposing is to integrate those dedicated checks into the Crossfire framework. Not by re-writing but by simply calling the existing code and making sure the checks show up in our index and that errors can be debugged from within Crossfire. This way the experts working on these checks can dedicate themselves to adding corporate-specific value, rather than having also to spend time on infrastructure-related subjects like format-parsing, visualization and parallelized data access – all areas where Crossfire excels, but which can take 70% or more of your time. So by working with Crossfire, the experts become a lot more productive.

This opportunity to focus on adding unique value is the way to engage customers, knowing that they will also benefit from a “QA-subscription” as Crossfire is continuously extended with new QA requirements from the entire industry.

That implies Fractal already has an industry-wide adoption, who are your customers?
You find our customers in all categories, we have system companies but also foundries, IDMs, independent IP design houses and fabless companies. All use Crossfire either during their design-flow, to have an end-of-line check before IP shipment or as an incoming inspection tool. I can’t disclose names, but half of the top-20 semiconductor companies already use Crossfire, and we expect the rest to come on board in the near future.

We support them preferably through local AE’s that speak their language and can be on-site quickly to deal with any issues or train new users.

What do you see as the next challenges for Fractal?

Managing growth is of-course key. We organically grow the engineering and AE teams so we get the right, qualified people on board and can make a proper investment in training them in our way of working. At the same time without compromising on the timing and quality our deliverables.

For our customers Fractal’s position as an independent QA tool provider is of prime importance. After all, who would buy a QA tool from either an IP provider or an EDA company? Absolutely no-one: in such a scenario a lack of test-coverage would only be the least suspicion. In essence, Crossfire would no longer have the authority it now has as an independent QA certification tool. The adoption of Crossfire and the Transport formalism by the industry is allowing us to continue with this strategy.

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