CEVA Dolphin Weninar SemiWiki 800x100 260419 (1)
Semiconductor Expert Forum

Posted on

Of distant dreams and violent delights

Of distant dreams and violent delights
by Don Dingee on 10-05-2016 at 4:00 pm
Categories: Mobile

Another report today of a Samsung Galaxy Note 7 catching fire, this time an allegedly refurbished unit, takes us back to the turning point in Samsung mobile phone history. It’s not the first time a defective Samsung phone – or a pile of thousands of them – has been on fire.

Samsung Chairman Lee Kun-Hee issued a powerful edict to his mobile phone team in 1993: “Produce mobile phones comparable to Motorola’s by 1994 or Samsung will disengage itself from the mobile phone business.” Samsung engineers had been struggling with a multipath problem and inferior signal quality, and set out to completely redesign their SH-700 phone and its SH-770 successor. Quality is a combination of design and manufacturing efforts, however. From “Mobile Unleashed”, p. 139:

What most consumers didn’t see, but Samsung employees felt, was the real quality story. Individual phone screening at the factory reduced problems before shipment, but a massive bone pile of dead phones developed. Lee sent some of the first SH-770s as holiday gifts, getting back reports of some of them not working. Embarrassed by quality escapees, he investigated further – and discovered the bone pile.

In March 1995, Lee visited the Gumi facility where the SH-770 was manufactured. Two thousand employees were invited to a rally in the courtyard, complete with “Quality First” headbands for all. Under a “Quality is My Pride” banner was the bone pile with phones and fax machines from the plant – some say numbering 150,000 units. A handful of workers smashed the defective devices with hammers, threw them into a bonfire, and bulldozed the ashes. Many of those who saw the spectacle wept openly. It was a lesson never forgotten.

I should know better by now: never say never.

A robot with a nervous breakdown, from HBO’s Westworld

There is no such thing as “good” quality, or “poor” quality. Quality exists, or it is absent, and the judge is the end user, not the manufacturer. We take the existence of quality in electronics for granted these days, after decades of advances in semiconductor, printed circuit board, and packaging and assembly technology. The era where electronic hardware used to fail dramatically mostly succumbed to reliability science years ago.

Failures today are far usually subtler. Software types invented the phrase, “It’s not a bug; it’s a feature.” Fixes are often quietly executed by reloading a new version of code, or perhaps walking back a change gone haywire. Devices magically get well, or at least quit misbehaving to the point where we don’t notice.

Phones catching on fire are hard to not notice. How Samsung has managed to produce a device, and follow up with a hardware fix, and still not solve the problem is absolutely baffling. Maybe there’s a Wells Fargo mentality at work here – ship phones, meet goals, worry later. I’ve found over the course of my career that idiotic behavior is almost always directly correlated to a compensation incentive lurking behind it. What looks dumb to you and me makes perfect sense to someone who has real money at stake.

Quality is a difficult, unforgiving master. Earlier this year when Huawei’s Richard Yu suggested they would pass Apple in smartphones within two to three years, and Samsung in five, many snorted. Now, that once seemingly locked door seems to be opening, inviting Huawei to execute on product and channel strategies. All those concerns about Huawei’s business ethics and intellectual property appropriation may be a distant dream.

Our violent delights – a compulsive need for mobile connectivity and content – now demand satisfaction. If Apple and Samsung can’t fill them, someone else will. There is no access to a previous configuration.

Putting on my black suit and heading back to work …

Posted on

You’re Going to Want to Attend the Cadence Photonics Summit Workshop, October 19-20

You’re Going to Want to Attend the Cadence Photonics Summit Workshop, October 19-20
by Tom Dillinger on 10-05-2016 at 12:00 pm
Categories: Cadence, EDA, Events

Photonics IC’s (PIC’s) are used to transmit and receive data through a (single-mode or multi-mode) optical fiber carrier, and provide the requisite electro-optical conversion for system integration. The architecture of the PIC spans the full characteristics of data transmission and reception:

  • light generation

Typically, an external source is used, either a separate module or combined with the PIC in a system-in-package configuration. Active research is underway to utilize silicon-based materials as an integrated light source.

  • injecting the data sequence onto the optical carrier

Optical waveguides patterned on the PIC are subjected to electrical (or potentially, thermal) stimulus to alter the characteristics of the waveguide propagation, modulating the phase or amplitude of the optical waveform. The difference in refractive index in the waveguide materials confines the light propagation.

  • splitting, multiplexing, and filtering of the optical power, to provide the target optical wave
  • coupling of the PIC optical data from the PIC to the fiber for data transmission

and, subsequently

  • coupling from the fiber to a (demux and) photo-detection structure – e.g., a photodiode – for the data receiver

Although fiber optics technology has been utilized for long distance communication for some time, new short-haul applications are emerging. Fiber-to-the-home will experience growing demand. Increasingly, data center server communications will employ fiber connectivity. The signal losses and power dissipation of traditional copper backplane technology used in rack servers are imposing limits on the available bandwidth between systems. (Advanced signal methods, such as the multi-bit encoded signal levels of PAM-4, are extending the effective data rates using the same unit interval. Yet, signal losses, and especially, signal noise impose difficult design constraints.) As a result, the market for PIC’s is forecasted to grow significantly, from $190M in 2013 to $1.3B in 2022, according to Transparency Market Research.

To date, PIC’s have been the epitome of “full custom” design. PIC designers have covered both optical structure and electronic circuit implementation and verification. These engineers work closely with fabrication suppliers, for detailed technical background on the waveguide material properties, mask making, and photolithographic capabilities. Specific photonic structures are typically added to shuttle testsites and characterized, providing a fixed IP library consisting of basic cells. (With regards to mask making, of specific concern is the discretization of the arcs that are prevalent in photonic structures, as discontinuities in the curvature result in adverse impact to propagation.)

To support the growing demand for PIC components, the current custom design methodology will need to scale – an integrated environment will be required, to support design capture, simulation, layout automation, parameter extraction, and post-layout validation. Cadence has partnered with Lumerical Solutions and PhoeniX Software to provide such a design environment, building upon the familiar Virtuoso tool suite.

The general design flow steps of this methodology are:

  • capture the optical and electronic “circuits” in the Virtuoso Schematic Editor
  • co-simulate the photonic and electronic elements with Cadence Spectre and Lumerical’s INTERCONNECT simulators
  • run circuit optimizations in the co-simulation environment
  • implement the layout in the Virtuoso Layout Suite XL, using the PhoeniX Software OptoDesigner algorithms for waveguide routing and photonic pCell generation
  • run in-design DRC using PhoeniX Software’s curvilinear DRC engine
  • extract photonic simulation parameters, re-simulate for final validation
  • generate masks, tapeout release to foundry

The architecture of the simulation tools is illustrated in the figure below.


Of specific note is that Cadence and Lumerical have developed a co-simulation solution – designers no longer have to deal with the accuracy and productivity issues of attempting to manually interface testcases between separate photonic and electronic simulators.

Referring to the Analog Design Environment box in the center of the figure, Cadence Spectre manages the overall simulation timestep. Lumerical’s INTERCONNECT simulator communicates with Spectre through an interface provided by INTERCONNECT’s dynamic link libraries, part of a Verilog-A module. The Verilog-A ports represent the electrical/optical partition interface. INTERCONNECT maintains a distinct optical simulation timebase, with appropriate interpolation to return results back to the Spectre time step.

The figures below illustrate the overall flow:

  • the Cadence schematic, combining electrical and optical components
  • the Verilog-A view, incorporating the Lumerical interface
  • the expanded optical model used by INTERCONNECT
  • simulation results, showing a ‘sweep’ of component parameters – in this case, the phase shift of the top branch of the waveguide in the optical model

(1) Cadence Virtuoso XL schematic

(2) INTERCONNECT optical model (expansion of the optical block in the parent schematic)

(3) Verilog-A view, integrating INTERCONNECT optical simulation

(4) simulation results, illustrating a parameter sweep

Note that this is indeed true co-simulation, with data exchange between simulators. (Verilog-A is not used as the optical model representation, as the semantics available are not well-suited to the unique characteristics of optical propagation.)

A key feature of INTERCONNECT is the use of compact models (an approach familiar to electronic designers), with S-parameter representations that span both time and frequency domains. These models have the specific advantage of enabling photonic structure parameterization through external variables, maintaining the underlying protection of IP designs.

Another productive feature of the co-simulation methodology is that familiar Spectre simulation capabilities are supported, enabling the designer to perform parameter sweeps and statistical analysis for optimization.

The integrated methodology flow for physical implementation involved the following steps:

  • Virtuoso Layout XL provides support for schematic-driven layout
  • PhoeniX Software’s integrated OptoDesigner provides pCell generators, specifically supporting advanced curvilinear shapes
  • co-floorplanning of electronic and photonic components (including Cadence support for SiP hybrid package designs)
  • layout-to-schematic back-annotation of waveguide parameters supports layout-accurate optical re-simulation

The PhoeniX pCells utilize PDK-like technology information from the foundry, to ensure that layout parameters are realizable (e.g., min/max waveguide bend radius).

An emphasis of this flow is the generation of compact model parameters from the PhoeniX pCells, for post-layout optical simulation. For example, the centerline of the waveguide is represented mathematically, which can subsequently be represented as an S-parameter matrix model.

Cadence is offering a two-day Photonics Summit and Workshop on October 19th and 20th, to provide an update on photonics technology, as well as hands-on experience with the new integrated PIC design methodology. The first day is the Summit, with an exceptional set of presentations from eminent speakers. The second Workshop day offers a set of hands-on experiences with the schematic capture, layout automation, and simulation tool flow.

Design engineers who will be expanding their scope of responsibilities to include photonic structures should attend this free summit and workshop. CAD and PDK technology engineers will also find the material extremely insightful. The link for registration on the Cadence Events site is here.

A link to the Cadence site that serves as the portal to photonics methodology development is here.

See you at the summit + workshop!

-chipguy

Posted on

The Unreasonable Effectiveness of Neural Nets

The Unreasonable Effectiveness of Neural Nets
by Bernard Murphy on 10-05-2016 at 7:00 am
Categories: General

In 1960, the Nobel-winning theoretical physicist Eugene Wigner published an article titled “The unreasonable effectiveness of Mathematics in the Natural Sciences”. His point was that, at least in the physical and chemical worlds, mathematics is able to describe the behavior of nature to an uncannily accurate degree, which leads to foundational debates on whether nature arises out of mathematics. Of course there are counter-views which I’ll get to later.

A similar argument was proposed recently for the surprising effectiveness of neural nets, though this time founded on physics rather than mathematics. (But if you accept that physics arises out of mathematics, perhaps it is a part of the same argument after all.)

First a quick review of how a neural net (NN) works and how effective they have become. An NN is a stacked layer of networks in which each layer is a plane of simple elements, where each element takes a small part of an input (an image, or speech or some other complex stimulus) and calculates a simple function based on that input. In image recognition for example, elements in the first plane would recognize simple characteristics like edges, each in a small segment of the image. Those are passed on to a second plane to recognize slightly more complex structures based on those edges, and so on. These systems are not programmed in a conventional sense; they must be trained to recognize objects but once sufficiently trained, they have proven able to beat humans at differentiating characteristics in images as closely related as different breeds of dog.

Deep neural nets/learning have proven to be more than an incremental refinement to existing methods – these methods radically improve accuracy and that in turn has led to an explosion in applications in image, speech and text recognition. Which naturally leads to improved applications for voice-based control, car safety and autonomous cars, medical advances and more. Sufficiently accurate voice-based control alone is likely to dramatically change the way we interact with automation, witness Amazon’s Alexa and similar systems.

An article in Fortune details the activity in this area, particularly investment activity, both internal and VC-funded. We all know about work that Google, Facebook, IBM, Microsoft and others are doing. What you may not know is that equity funding of AI startups reached $1B last quarter. Apparently VCs are now wary of any startup that doesn’t have such an angle, if only because they are losing interest in devices or software controlled through menus and clicks. Their view is that natural language (eg. speech) interfaces are now the hot direction.

So there’s definitely money to be made, but of course VCs don’t give a hoot about the fundamentals of physics, mathematics or the ontology of those domains. But debate in those areas might have something to say about how long-lived this direction could be, so let’s get back to that topic. Henry Lin at Harvard and Max Tegmark at MIT, both physicists, have proposed a reason why neural nets should be so effective and their claim is grounded in physics.

Their reasoning works like this. The physics of the universe can be modeled extremely well with low-order equations and with a small handful of relatively simple functions, much smaller certainly than the range of all possible functions. They attribute this to causal sequences in the evolution of the universe. The universe started from a completely ordered state (the big bang) but is still nowhere near an entropic death, as evidenced by structure in the cosmic microwave background (CMB), for example. This, they assert, is why we see significant structure and why we are able to explain physics with a limited set of equations and functions – evolution through causal sequences leads to relatively simple behavior, at least up to the current era.

So, they argue, the effectively hierarchical structure of recognition in deep neural nets is sufficient to recognize the complexity of systems we encounter in nature, whether the CMB or galaxies, or dog breeds or speech, because they need not model arbitrarily complex systems. The hierarchical structure of how systems evolve in nature, whether cosmological or biological, as evidenced in quite universal characteristics like symmetry and locality ensures they can be modeled with excellent accuracy by neural nets. (In fairness, I am greatly oversimplifying their argument – you can follow a link to an arXiv paper in one of the links below.)

This steers closer to philosophy than science, which doesn’t necessarily make it uninteresting to the more grounded among us, but it does open the floor to counter-arguments. In fact, there were early counters to Wigner’s position. One (interestingly from Hamming) was that humans see what they look for, another that we often find it essential to create new mathematics to fit a requirement (the simple equations and functions we construct are perhaps more to fit within our limited mental capacity than they are a characteristic of nature). The same arguments could be made about the neural net/physics connection. Still, physics (and engineering even more so) is about approximation. If, to sufficient accuracy, a simple model will work, then the deeper “reality” (whatever that might be) may be unimportant for practical applications, though still important for deeper understanding.


To wrap up, since I’m in a philosophical mood, Tegmark and others have written a paper on a concept started (I think) by Roger Penrose on the relationship between Mathematics, Matter and the Mind – a sort of Penrose triangle. A question here is whether one of these three is most fundamental or one most derived, or whether one or more is unrelated and simply an artefact of our attempt to model. Wigner’s position was that matter derives from mathematics. One of Hamming’s positions was that we create mathematics to model what we want to see – that Mind is fundamental, Mathematics derives from the Mind and perhaps our view of Matter is just our way to reduce the natural world into this framework. But for neural nets, who cares – it seems they may already have the power to model with the accuracy we need, at least for now.

The Wigner article can be found HERE, the Harvard/MIT article HERE and the Fortune article HERE. The mathematics, matter, mind paper can be found HERE.

More articles by Bernard…

Posted on

Free Copy of Mobile Unleashed: The History of ARM!

Free Copy of Mobile Unleashed: The History of ARM!
by Daniel Nenni on 10-04-2016 at 4:00 pm
Categories: Arm, IP, Mobile

As most of you know SemiWiki published a book which is a really nice history of ARM. We have received many compliments on it and we are very proud. As a thank you to all SemiWiki members I would like to offer a free electronic version of the book (PDF). You can access it via the attachment at the bottom of this wiki:

SemiWiki Book Download:Mobile Unleashed: The History of ARM

This is the origin story of technology super heroes: the creators and founders of ARM, the company that is responsible for the processors found inside 95% of the world’s mobile devices today. This is also the evolution story of how three companies – Apple, Samsung, and Qualcomm – put ARM technology in the hands of billions of people through smartphones, tablets, music players, and more.

It was anything but a straight line from idea to success for ARM. The story starts with the triumph of BBC Micro engineers Steve Furber and Sophie Wilson, who make the audacious decision to design their own microprocessor – and it works the first time. The question becomes, how to sell it? Part I follows ARM as its founders launch their own company, select a new leader, a new strategy, and find themselves partnered with Apple, TI, Nokia, and other companies just as digital technology starts to unleash mobile devices. ARM grows rapidly, even as other semiconductor firms struggle in the dot com meltdown, and establishes itself as a standard for embedded RISC processors.

Apple aficionados will find the opening of Part II of interest the moment Steve Jobs returns and changes the direction toward fulfilling consumer dreams. Samsung devotees will see how that firm evolved from its earliest days in consumer electronics and semiconductors through a philosophical shift to innovation. Qualcomm followers will learn much of their history as it plays out from satellite communications to development of a mobile phone standard and emergence as a leading fabless semiconductor company.

If ARM could be summarized in one word, it would be “collaboration.” Throughout this story, from Foreword to Epilogue, efforts to develop an ecosystem are highlighted. Familiar names such as Google, Intel, Mediatek, Microsoft, Motorola, TSMC, and others are interwoven throughout. The evolution of ARM’s first 25 years as a company wraps up with a shift to its next strategy: the Internet of Things, the ultimate connector for people and devices.

Research for this story is extensive, simplifying a complex mobile industry timeline and uncovering critical points where ARM and other companies made fateful and sometimes surprising decisions. Rare photos, summary diagrams and tables, and unique perspectives from insiders add insight to this important telling of technology history.

The forward by Sir Robin Saxby alone is worth the price of admission, not to mention the picture of Simon Segar as a young engineer when he first joined ARM… There is also a cameo by Wally Rhines from his TI days.

I truly believe you need to fully understand, as a semiconductor professional, how we got to where we are today to better understand where we are going tomorrow and that is what this book is all about. On a personal note, writing books like this is a lot like giving birth (although my wife may disagree). It was nine months of hard work but let me tell you one thing, Don Dingee made this whole process a lot easier. Don is the most dedicated, thorough, and hardworking researcher I have ever worked with, absolutely!

Posted on

"Rigid-Flex Design is Coming"

"Rigid-Flex Design is Coming"
by Tom Dillinger on 10-04-2016 at 12:00 pm
Categories: Cadence, EDA

Printed circuit boards that incorporate a combination of traditional PCB technology with flexible substrates, aka rigid-flex designs, have enabled an increasing variety of product designs, that leverage the unique physical form factor and lightweight options that rigid-flex technology offers. Yet, this technology requires unique CAD tool features and enhancements, when compared to traditional PCB design flows.

Cadence recently published a whitepaper and a corresponding site with a video demonstration that highlights the unique rigid-flex capabilities that have been incorporated into a recent release of the Allegro PCB design tool suite (Release 17.2, SPD17.2-2016). I had an opportunity to chat briefly with the author of that whitepaper, Ed Hickey, Product Engineering Director.

Ed described some of the features of this recent release, covering both design and verification requirements.

Stack-up definition for rigid-flex “zones”
The stack-up material definition is the fundamental fabrication technology description used by PCB placement, routing, and analysis tools. For rigid-flex designs, the stack-up support needs to be expanded to accommodate the various “zones” of the total design. The figure below illustrates how the traditional “rigid” FR-4 based layers, the (polyimide and copper) “flex” layers, and the transition “stiffener” zones are defined for stack-up identification.


Component placement
Component placement (and pin-attach padstack) rules are dramatically different on flex – moving a component across a rigid-flex boundary needs to automatically ensure a correct layer + padstack definition.

Routing
Signal routing on the flex layers presents very unique considerations. Ed highlighted, “The flex outline typically utilizes aggressive contours. Routing must support detailed arc definitions to the contour outline – this includes bus route(group mode) definitions. Routers need to be compliant to teardrop requirements at pins and vias, and tapering rules at trace width transitions. And, designers need editing support to be contour-aware, as well.”

The Cadence site corresponding to this whitepaper includes an illustrative demo, showing how a new signal inserted interactively leverages push-and-shove capabilities that are also fully compliant to the flex contour.

In-Design Checking
Rigid-flex technology has several unique verification requirements, enabled in Allegro PCB:

  • restrictions on component placement on the flex, relative to bend areas (“the bend line and bend radius”)
  • restrictions on multi-layer via placement on the flex
  • routes must cross perpendicularly to a flex bend line
  • signal routes on different flex layers need to be offset, to avoid a flex cross-section that is mechanically stiff (“the I-beam effect”, according to Ed)
  • unique rules are needed for vias and material dimensions in the transition zone

The Cadence Allegro release incorporates a new user-interface to create rules for rigid-flex design, as illustrated below for various layer-to-layer interfaces (including non-electrical surface and flex layers, such as the polyimide coverlay).


Rigid-flex electrical analysis requirements
“Cadence tools for electrical analysis also support the unique characteristics of rigid-flex designs.”, Ed indicated. “Specifically, there may be cross-hatched copper areas. Field-solver technology has been enhanced to provide accurate impedance modeling for non-solid geometries.”

MCAD-ECAD data interchange, manufacturing release
Ed emphasized the need for robust exchange of rigid-flex design data with mechanical CAD tools for product enclosure co-design and structural reliability analysis.

“Mechanical analysis requires accurate data on the material stackup in each zone, to evaluate the overall bend performance. The IDX standard data format is replacing the legacy IDF standard.”, Ed pointed out. “We have qualified the Allegro design export flow for rigid-flex with MCAD analysis tools.”

And, to be sure, the export of the rigid-flex design to fabricators requires exact representation. “There has been a tremendous amount of dollars and time wasted, due to issues with the lack of accuracy in design data provided to manufacturers. Cadence is committed to the new intelligent format standard for data exchange, known as IPC-2581.”

Ed summarized the emphasis that Cadence is putting into Allegro features for rigid-flex design in a succinct manner, stating, “The growth of this technology is accelerating. Traditional PCB designers should be aware that rigid-flex is coming.”

A link to the Cadence whitepaper is here.

A link to the Cadence site with additional detail (and video demo) is here.

-chipguy

Posted on

GloFo’s 12nm FD-SOI: why it makes headlines in China

GloFo’s 12nm FD-SOI: why it makes headlines in China
by Adele Hars on 10-04-2016 at 7:00 am
Categories: FD-SOI, Foundries, GlobalFoundries

As you’ve probably seen in (excellent!) recent semiwiki postings by Eric Esteve and Scotten Jones, 12nm FD-SOI has now officially joined the GlobalFoundries’ roadmap. Eric and Scotten did a great job of putting many things in perspective. But this is a big piece of news, so here I propose looking at it from yet another perspective, adding a few details from GloFo’s press releases, and showing some supporting slides from their presentations at the FD-SOI Forum in Shanghai last month. Why the italics? Read on.

Also read:GLOBALFOUNDRIES Extends the FDSOI Roadmap

Also read: GlobalFoundries Enhances FDSOI Roadmap with 12FDX

First, just to be clear, GloFo’s target with 12FDX, as it’s called, is intelligent, connected systems. They say it’s beating 14/16nm FinFET on performance, power consumption (by 50%) and cost. Add back bias andit beats 10nm FinFET. Customer product tape-outs are expected to begin in the first half of 2019. That should put them in a pretty sweet spot for the leading edge of their target customers doing those “intelligent, connected systems”.


(Courtesy: GlobalFoundries and SOI Consortium Shanghai FD-SOI Forum 2016)

Overall, the GloFo news turned heads worldwide (hundreds of publications immediately picked up the news) – but especially in China. In fact, two important names in China’s chip world figured amongst those quoted in the GloFo release.

“We are excited about the GlobalFoundries 12FDX offering and the value it can provide to customers in China,” said Dr. Xi Wang. He’s Director General and Academician of Chinese Academy of Sciences (a tremendously important institution in China, both historically, and now it would seem going forward), as well as the founder of the Shanghai Institute of Microsystem and Information Technology (aka SIMIT – you’ll be hearing a lot more about them, so stay tuned). So Dr. Xi Wang continued his supporting statement, saying, “Extending the FD-SOI roadmap will enable customers in markets such as mobile, IoT, and automotive to leverage the power efficiency and performance benefits of the FDX technologies to create competitive products.”

Another name to watch for is Wayne Dai, CEO of VeriSilicon (headquartered in Shanghai but designing for the world’s biggest names in the chip biz, taping out over 50 chips/year). His company has been doing FD-SOI design for years: they are clear fans. Dai said, “We look forward to extending our collaboration with GlobalFoundries on their 12FDX offering and providing high-quality, low-power and cost-effective solutions to our customers for the China market [note: italics are mine]. The unique benefits of FD-SOI technologies enable us to differentiate in the automotive, IoT, mobility, and consumer market segments.”

The ultra-thin FD-SOI wafers are where it all starts, and they’re ready to go in high volume, says Paul Boudre, CEO of SOI wafer leader Soitec (which, it so happens, recently welcomed a major new investor from China called NSIG — founded by Dr. Xi Wang). “We are very pleased to see a strong momentum and a very solid adoption from fabless customers in 22FDX offering,” he adds. “Now this new 12FDX offering will further expand FD-SOI market adoption. This is an amazing opportunity for our industry just in time to support a big wave of new mobile and connected applications.”

Isn’t FD-SOI a potential game-changer for China, enabling the country’s industry to leap ahead in key markets? Anyone see a pattern here?

About 12

GloFo’s 12FDXTM platform is building on the success of its 22FDXTM offering. And note that with 22, they’re hitting all their targets.


(Courtesy: GlobalFoundries and SOI Consortium Shanghai FD-SOI Forum 2016)

As such FDX is designed to enable the intelligent systems of tomorrow across a range of applications, from mobile computing and 5G connectivity to artificial intelligence and autonomous vehicles. Increased integration of intelligent components including wireless (RF) connectivity, non-volatile memory, and power management—all while driving ultra-low power consumption—are key selling points that FinFETs really can’t touch.

The technology also provides the industry’s widest range of dynamic voltage scaling and promises unmatched design flexibility via software-controlled transistors—capable of delivering peak performance when and where it is needed, while balancing static and dynamic power for the ultimate in energy efficiency.


(Courtesy: GlobalFoundries and SOI Consortium Shanghai FD-SOI Forum 2016)

So can we put the FD-SOI vs. FinFET battle to rest?

“Some applications require the unsurpassed performance of FinFET transistors, but the vast majority of connected devices need high levels of integration and more flexibility for performance and power consumption, at costs FinFET cannot achieve,” posits GloFo CEO Sanjay Jha. “Our 22FDX and 12FDX technologies fill a gap in the industry’s roadmap by providing an alternative path for the next generation of connected intelligent systems. And with our FDX platforms, the cost of design is significantly lower, reopening the door for advanced node migration and spurring increased innovation across the ecosystem.”

Notable kudos for 12FDX also came in from: G. Dan Hutcheson, CEO of VLSI Research; IBS CEO Handel Jones; Linley Group Founder Linley Gwennap; Dasaradha Gude, CEO of IP/design specialists INVECAS; Leti CEO Marie Semeria; and NXP VP Ron Martino (they’ve already started on 28nm FD-SOI for their i.MX line – read his superb explanations in semiwiki and in ASN here).

Also read: Why is NXP moving to FD-SOI? (part 1 of 2)

A steady stream of FD-SOI announcements from GloFo has followed – more on those soon. As Scotten Jone pointed out in a recent semiwiki piece on 12 FDX, “…FDSOI is finally positioned to take off in the market place.” And if the stars keep aligning, China could stack up to be a major player — and driver.

Posted on

SiFive execs share ideas on their RISC-V strategy

SiFive execs share ideas on their RISC-V strategy
by Don Dingee on 10-03-2016 at 4:00 pm
Categories: IoT, IP, RISC-V, Semiconductor Services, SiFive

Since its formation just last year, SiFive has been riding the RISC-V rocket from purely academic interest to first commercialization. In an exclusive discussion, I talked with CEO Stefan Dyckerhoff and VP of Product and Business Development Jack Kang about their progress so far and what may be coming next.


Previously, I covered the introduction of the SiFive Freedom E300 and U500 platforms of RISC-V IP cores. From the comments we got, I’m not sure people understood what the SiFive business model is, or what their ecosystem looks like. As Dyckerhoff put it, SiFive is at the tail end of its design process with its initial offering commercial cores – but there is a lot more to the strategy.

“We help solve compute problems benefitting from customization,” Dyckerhoff said. RISC-V is an open source instruction set giving implementers complete freedom to create silicon solutions. SiFive provides RISC-V expertise in two basic go-to-market strategies: selling IP, including support and customization; and complete turnkey system-centric chip projects. Dyckerhoff represents Sutter Hill Ventures and comes from Juniper Networks, and was also deeply involved with P.A. Semi prior to the Apple acquisition, and he gets this OEM-enablement model.

The first success story for SiFive was supporting Microsemi in a 2-month project for one of their end customers, delivering a customized E300 core in an FPGA. (My guess at who that customer might be – starts with an A, ends with ‘us’ – was unconfirmed. The cone of silence is working properly.) The Freedom E300 SF2+ FPGA Dev Kit available on the SiFive developer site is a by-product of that effort. It’s always good to have that satisfied lead customer in the bag. That has helped SiFive to grow to employee #18 so far.

Speed is the essence of this model. The tricky part of engagements is to find a way to translate a moderate up-front investment into medium revenue quickly at low risk. If there were huge revenue on the table, an OEM could choose to do an SoC themselves, but it’s a big leap. Even medium-sized projects can siphon off a lot of resources if teams aren’t careful, especially when it comes to custom silicon. “We want to radically drive down human involvement in design costs,” says Dyckerhoff. He says processor IP today is overvalued, while the hard part is implementing the SoC – and 80% of the stuff in that SoC doesn’t add value to the actual application.

Those are intriguing comments, given developments in September. One of the companies to jump on the RISC-V bandwagon is UltraSoC, with their universal SoC debug solution. Also on board is Fedora, releasing a complete RPM-built bootable disk image of Linux. Kang says the lead implementer for KVM has also reached out with questions, and there is the Apache MyNewt project for a deeply embedded RTOS.

Although SiFive isn’t targeting ARM specifically, Dyckerhoff says there was a definite uptick in developer registration activity after the SoftBank acquisition of ARM. I asked about what application segments they are seeing activity in – for instance, my barking chain says SSD providers are very interested since the flash controllers are heavily customized. Again, no specific confirmation, but it does fit the profile. Both Dyckerhoff and Kang commented that they are hoping to catch people heading from “classic MCU to IoT-ish” projects needing more customized silicon, something I’ve been saying is happening for a while.

There’s also a very big development on the horizon. One of ARM’s turning points was introduction of AMBA. Its motives were self-serving – to get chips designed faster, it had to be easy to connect in the processor IP, so they firmed up a specification. It ultimately had the opposite effect; as more ARM processor IP was fielded, other IP providers had to adopt AMBA if they hoped to get designed in.

In the RISC-V community, TileLink could provide that same type of turning point. It’s the cache coherent interconnect layer, and it does bridge into AXI4 via the NASTI interface. SiFive teams have stepped in to help edit the TileLink specification and formalize it for public consumption, and although the timeframe isn’t firm Dyckerhoff hinted we might be within a couple months of release. That could break loose an entire chain of RISC-V IP offerings.

I asked SiFive about China in particular. Their response was a bit surprising: it’s not currently a high-priority focus. Dyckerhoff has a lot of experience competing in China from his Juniper days (read: Huawei), and understands what would have to happen to succeed there. He did say with SoftBank in the picture as a Japanese firm, there have been rumblings about cultural rivalries, but nothing earth-shattering in the works yet. Possibly sandbagging, but given their size and ample opportunities I believe this.

The last comment may have been the most interesting. Dyckerhoff says yes, SiFive is for-profit, created to solve immediate business problems. He sees their mission as doing that in the most “extremely friendly to open source” way possible. I take that to mean that while they aren’t necessarily giving away all their RTL (not a requirement of the RISC-V Foundation, BTW), they are committed to get to open source interface specifications created and to have open source software ported. For instance, SiFive teams are maintaining the current “Rocket” open source core implementation.

There are a ton of parallels between the early days of ARM and where SiFive is headed. ARM was at a headcount of 70 in 1994 when they hired Warren East to run their consulting operation, where ARM engineers co-designed chips with customers. AMBA debuted in 1997 after the stunning success of ARM7TDMI. SiFive doesn’t have critical mass of high-profile design wins just yet, but is laying the necessary groundwork to reign in academic thinking around RISC-V.

The progress SiFive has made so far is substantial; granted they are bootstrapped on a couple years of predating RISC-V efforts. I do think there is more customer activity going on than people are willing to talk about. When the TileLink spec is published, that should free up critical resources for driving new customer engagements. I’d also look for what other open source software comes into the fold for hints on how application segments will develop.

Posted on

Microsoft, FPGAs and the Evolution of the Datacenter

Microsoft, FPGAs and the Evolution of the Datacenter
by Bernard Murphy on 10-03-2016 at 12:00 pm
Categories: FPGA

When we think of datacenters, we think of serried ranks of high-performance servers. Recent announcements from Google (on the Tensor Processing Unit), Facebook and others have opened our eyes to the role that specialized hardware and/or GPUs can play in support of deep/machine learning and big data analytics. But most of us would probably still consider those applications, while important, somewhat niche in their role in the datacenter.

Several years ago, motivated by what they knew was already happening at Google and Amazon, Microsoft started to build their own machine learning system to enhance the capabilities of Bing. But rather than develop a custom device, or build on a GPU platform, they decided to build on FPGAs. As we know, FPGA-based solutions can be significantly cheaper to build and deploy when you know you are going to be the sole customer. And of course FPGAs have the advantage of re-programmability. The Microsoft team built an FPGA-based platform they called Catapult and demonstrated this would significantly accelerate machine-learning algorithms in Bing (over previous software-only approaches, I assume).

Fast forward to 2015. Even the most starry-eyed Microsoft supporter would admit that Bing has a long way to go to catch up with the leader in search and is unlikely to drive significant revenue for Microsoft in the near future. What the company really wants are more ways to propel their major online services – Azure (the MS Cloud) and Office 365. Catapult was appealing to both of these applications, but not necessarily for machine-learning.

A major problem for Azure’s has been managing the high volume of PCIe network traffic to and from virtual machines through virtual network (VN) adapters. When this gets up to GB/sec for a VM, the the VN management load on the CPU becomes substantial. Obviously off-loading this to a system to support physical traffic and handle network virtualization can significantly improve throughput. Network cards would be one solution but the Azure team didn’t find this approach adaptable enough in supporting what they needed in a flexible VN fabric on the server side. After all, if you want maximum flexibility in VM management in the cloud, you need corresponding flexibility in VN management. The Azure team felt this could best be handled through FPGAs, particularly in support for programmability for load balancing and other rules.

All of this required a major rework of Catapult, but now the hardware is done and is being rolled out. And this is no longer a few specialized boxes to serve specialized needs. Azure needs a Catapult system per server (exact details are difficult to find – looks like one per server). And you can add to that the deep/machine learning requirements to support Bing and later encryption/compression and machine learning requirements to support Office 365.

This is a whole new ball-game for FPGA deployment. Since a large datacenter contains many hundreds of thousands of servers, Microsoft’s demand alone has apparently shifted FPGA worldwide volumes significantly. You should know by the way that Catapult is based on Altera FPGAs. Intel EVP Diane Bryant is on record as saying this is why Intel bought Altera last year. She also anticipates that for similar reasons, one third of all servers in datacenters will contain FPGAs (presumably optical connectivity sets the limit on volume, where FPGAs maybe can’t help – for now, but stay tuned since Intel was talking about both FPGAs and photonics at the OCP summit this year).

Of course you could argue that Microsoft and Intel have misread the market and the virtual networking functionality will be replaced by ASIC hardware solutions (especially optical). I’m not so sure, at least for the next few years. This is an area of critical differentiation for cloud services providers, so they’ll each want their own solutions. Of course the economics of ASIC may not be a big factor in those budgets, but adaptability could be a very big factor, especially as capabilities in cloud services are evolving quickly. Eventually differentiation always moves on to other factors, but it’s not clear that is going to happen here anytime soon.

You can read the Wired article on Catapult HERE and a slightly more detailed article on the Azure need for networking flexibility HERE.

More articles by Bernard…

Posted on

Could Machine Learning be Available for Mass Market?

Could Machine Learning be Available for Mass Market?
by Eric Esteve on 10-03-2016 at 7:00 am
Categories: Ceva, IP

Machine Learning is at the hype peak, according with Gartner’s August 2016 Hype Cycle for Emerging Technologies. The demand for vision processor IP is strong in smartphone, automotive and consumer electronics segments. ASSP based solutions can make the job, but how can OEM create differentiation, control their destiny and pricing if they select an ASSP? In mobile segment, integrating Mediatek or Qualcomm SoC supporting camera/vision will lead OEM to build a ‘me too’ smartphone. OEM developing ADAS or Autonomous for automotive are facing similar problem when integrating MobilEye or NVIDIA ASSP as they can’t add their own algorithms and differentiate.

It’s the right time to integrate DSP based vision processor IP complete solution, like new CEVA-XM6 DSP Core, Hardware Accelerators, Neural Network Software Framework, Software Libraries and Algorithms. The right time because the performance of deep learning technology, measured by the error rate on image recognition is, this year and for the first time, better than human performance! It’s also the right time because adopting CEVA Convolutional Deep Neural Network (CDNN) solution implemented on XM6 DSP core will enable embedded neural networks for mass market (low cost) vision application and allows delivery of deep learning solutions on (low power) embedded devices. This low cost, low power solution is not emerging by chance. The CEVA-XM6 based vision platform has been built on the strong foundation of XM4 counting 25 design-wins and the vast experience accumulated across multiple end markets and applications where neural network are being deployed.

We have explained the Convolutional Deep Neural Network (CDNN) theory and given some examples of proprietary networks in a previous blog in Semiwiki, we will focus today on the way to generate CDNN, thanks to S/W development tools and CEVA network generator, and describe the H/W implementation.

Before to run imaging and vision algorithms on CEVA-XM6 DSP, you can create your own CDNN, using neural network software framework, made of real-time libraries, Computer Vision libraries (CEVA-CV based on Open-CV), Vision Processing API (OpenVX, royalty free open standard API from Khronos, integrated into CEVA-VX) and 3[SUP]rd[/SUP] party S/W. At this point, any customer can create differentiation by inserting proprietary algorithms. Instead of using one CDNN fitting all application, CEVA Network Generator allows creating a unique CDNN, customer or application specific.

CEVA-XM6 is the 5[SUP]th[/SUP] generation Imaging & Vision Technology from CEVA and the IP vendor is bringing major improvements compared with the previous generation, CEVA-XM4. If you look at the right part of the Hardware box, you identify hardware accelerators (HWA), namely CDNN, De-Warp and 3[SUP]rd[/SUP] party HWA. Implementing in frozen hardware the well-known and repetitive tasks is a very good way to optimize performance, freeing the DSP which can be used to run other tasks, and reduce the power consumption as dedicated H/W will always be more power efficient that any processor to run the same task. For those who remember the digital signal processing implemented to run the wireless phone base-band, if the Viterbi decoding algorithm was initially running on (TI) DSP, the task has very quickly moved to an HWA. This is the same principle, applied to imaging and vision technology.

Scatter-gather capability: CEVA-XM6 enables load/store vector elements from/into multiple memory location in a single cycle. CEVA-XM6 is able to load values from 32 addresses per cycle. Scatter-gather not only boosts performance, but also allows minimizing access to/from memory, known to severely impact the power consumption.

If scatter-gather is a performance booster whatever is the application, Sliding-Window data processing mechanism is completely dedicated to imaging. The principle is to take advantage of pixel overlap in image processing by reusing same data to produce multiple outputs. If implementing Sliding-Window mechanism lead to significantly increase the DSP core processing capability, it also reduces power consumption and save external memory bandwidth. One of the challenges linked with machine learning on neural network is to reduce the amount of bandwidth consuming and computing bottleneck. That’s why implementing techniques like scatter-gather or sliding-window is crucial for bringing machine learning to mass market applications, as these require using low cost, low power solutions.

As of today, CEVA has implemented 512 MACs (16×16) as hardware accelerators, as well as many of the convolutional layers (Normalization, Pooling, etc.) required by the CDNN and plan to implement even more layers in the future. How efficient is CEVA-XM6 architecture? Just consider that the MAC utilization is greater than 95%, and you realize that CEVA-XM6 has been optimized to the maximum.

To answer the initial question, we can say yes, the machine learning technology has been made available to the mass market, targeting Autonomous Driving, Sense and Avoid Drones, Virtual and Augmented Reality, Smart Surveillance, Smartphones, Robotics and More.

By Eric Esteve from IPNEST

Posted on

Intel Altera FPGA at the heart of an autonomous Audi A8

Intel Altera FPGA at the heart of an autonomous Audi A8
by Claudio Avi Chami on 10-02-2016 at 4:00 pm
Categories: Automotive, Foundries, FPGA, Intel Foundry

Audi announced its piloted driving technology at CES 2015. The Audi Prologue includes the Advanced Driver Assistance System Platform (zFAS), co-developed with TTTech. The zFAS board is based on four devices: an Nvidia k1 processor and Infineon Aurix processor, Mobileye’s EyeQ3 for vision processing, and an Altera Cyclone V FPGA which provides sensor fusion, combining data from multiple sensors in the vehicle for highly reliable object detection and Deterministic Ethernet communications used to transport high bandwidth data within the vehicle.

The zFAS board receives and processes data from:

  • Ultrasonic sensors around the car
  • Front and rear radars
  • Top view camera
  • Front laser scanner
  • Wide angle front camera

The board has also actuators to control:

  • Steering wheel
  • Gear
  • Accelerator
  • Etc.

On ASDF-2015 (Altera SoC Developer Forum, now renamed ISDF since Altera was acquired by Intel), TTTech commented on various aspects of the Piloted Driving technology that would be available to the public during 2017.

Importance of Autonomous Driving

Autonomous driving will:

  • Improve safety – sensor information and processing could avoid up to 40% of today’s accidents
  • Liberate the driver from monotonous driving, i.e. commuting during rush hours
  • Provide new ways of mobility for people that cannot drive, deliveries, car pools, etc.

Key Technical aspects

The Piloted Driving must provide:

  • Fail-safe operation – Even if the system is an assistant, it cannot be guaranteed that the human driver can take control immediately. Upon a single component failure, the system must still be able to take the car to a secure stop.
  • Integration of safety devices with high performance devices. Processing devices share a Gigabit Ethernet backbone with real time messaging capabilities (TSN – Time Sensitive Network).
  • SW integration of applications and the operating systems running at the diverse platforms.
  • Fast deployment by usage of readily available Altera IPs and custom IPs.

Additional information:
TTTech announcement
Altera press release
Audi details piloted driving technology

My blog: FPGA Site

Other entries from me:
Soc FPGA for IoT Edge Computing
FPGAs at Deep Machine Learning