IPnest is launching the “Interface IP Survey” since 2009, and we did it last September again. To build the survey as accurately as possible, I have followed the “divide and conquer” strategy. Interface protocols are varied, ranging from PCI Express, USB, or Ethernet, to memory controller (DDR3, DDR4, LPDDR3, LPDDR4 and more) and HDMI, DisplayPort, SATA, SAS, or MIPI specifications (CSI, DSI, I3C, M-PHY, D-PHY, C-PHY…).
Some protocols are ubiquitous like USB or memory controller while certain protocols are application specific like SATA, HDMI or DisplayPort. In other words, for a specific protocol, the adoption dynamic and the related IP sales behavior will follow a certain model, and this model will be different for another protocol. In order to “conquer” (understand the adoption behavior, the sales evolution and build a forecast), you have to “divide” the overall interface IP market, or segment it by protocol. As a consequence, you have to define different values for the same parameter (like adoption rate, externalization rate, etc.) whether it will be used to model the PCI Express IP market or the HDMI IP market.
This approach is complex, but this is the price to pay to work accurately. The goal is to understand, by protocol, the IP market dynamics during the last five years (2010-2015 in this case), to evaluate the trends (based on the best knowledge of the semiconductor market behavior) and to build a five years forecast (2016-2020)… as good as possible (1). The consolidation of the different forecast of IP sales by protocol will give the final result, the interface IP market forecast. At this point, when you compare the global (wired) interface IP market weight with the other IP segments (CPU, GPU, DSP, RAM and NVM memory compiler, libraries, mixed-signal and so on) you realize this is the second largest segment in 2015 for up-front license revenues, just behind CPU IP core.
This report is the 8[SUP]th[/SUP] version made by IPnest, and we have now a pretty accurate view of this IP market evolution. We can compute the CAGR for the top 5 protocols: USB, PCIe, DDRn memory controller, Ethernet and MIPI. I let the reader review this self-explaining table.
Let’s focus on the two segments expected to bring the strongest growth in $ value, PCI express and Ethernet. The PCI Express protocol has been defined initially to support the enterprise market (PC, servers, networking, computing, etc.). The protocol is now pervading in applications like storage (NVM Express and SATA Express), mobile (Mobile-Express) and even automotive, with the emergence of MCU integrating PCIe links. The Ethernet IP segment is integrating the Very High Speed SerDes (28G or 56G) and the rational is that these SerDes are first integrated into Ethernet functions before to be adapted to support other protocols like PCIe 4 (16G) for example. The massive demand for more data bandwidth is the reason why the Ethernet market is growing, and will continue to grow. Let’s add that the Ethernet protocol has been adopted in the automotive segment as the preferred link between systems.
In average, the top 5 interface IP segments have grown by 112% between 2010 and 2015, or with a 13.3% CAGR. This growth is still solid, with 10% YoY in 2015, but not as impressive as in 2011 when the growth was 20%. IPnest forecast the interface IP market to grow every year up to 2020 with a 7% CAGR, masking disparities between the protocols. Some protocol will see related IP sales decrease with (-3%) CAGR, when other will grow with +13% CAGR. This overall growing behavior is that we call the “IP Paradox”.
If you take into account the SoC development cost, strongly increasing for technology nodes below 28 nm, and consider the semiconductor R&D global expenses, you realize that the design starts number is decreasing (if you are not convinced, I recommend you to read this blog and look at the graphic from Synopsys “The Relentless March of Moore Law”). But the IP market is still growing, and growing much more than the EDA expenses, almost flat. IPnest has analyzed this paradox, and I will be happy to share my views during IP-SoC 2016 conference (6-7 December, Grenoble, France)…
As of today, I would like to confirm that IPnest will extend the IP market analysis to the entire Design IP in 2017. The main reason is coming from IPnest customers, as they have expressed their need for an accurate IP market report. Gartner has decided to stop releasing the famous “Design IP Report”, but the semiconductor ecosystem, chip-makers, IP and EDA vendors, need such a barometer, especially if you consider that design IP, as a market, is growing, and will grow in the future.
I have made a simple research on the web and I found 3 reports dealing with IP forecast. Take a look at these 3 title, and you will realize that doing an accurate forecast is all but an easy task:
- (April 2012): Global Semiconductor IP Market Worth $5.7 Billion by 2017
- By the same analyst (!!) in March 2014: Semiconductor IP Market worth $5.63 Billion by 2020
- From another source in October 2016: Semiconductor IP Market to Exceed $8 Billion by 2020
Do you think that this analyst forecasting the same weight for the Design IP market ($5.7 Billion vs. $5.63 Billion), but in one case for 2017, then for 2020, should really be considered as a credible source?
If you want to appreciate the 3[SUP]rd[/SUP] forecast ($8 Billion in 2020), you have to recall the value for the Design IP market in 2010 ($1.7 Billion), and in 2013 ($2.5 Billion). At the beginning of the 2010, the IP market growth was strong, confirmed by the 14% CAGR for 2010 to 2013 evolution. Now, just calculate the CAGR for 2013 (actual = $2.5B) to 2020 (3[SUP]rd[/SUP] Forecast = $8B)… this CAGR is supposed to be 18% !!This is just unrealistic…
The Design IP market is a key component of the semiconductor ecosystem and that’s the reason why analysts are expected to provide a top quality work when building a report or a forecast. The first goal is to provide an accurate view of the past year results, and IPnest will do it in 2017 for the IP market weight in 2016. If this job is well done, it will be possible to build an accurate 5 years forecast, and we should be able to predict the accurate value of the IP market in 2020. Stay tune for the “Design IP Report” to be launched in April 2017 by IPnest, covering the IP market in 2016.
- Forecast: the various parameters used to compute the forecast are: Design starts including the protocol function at year N-1; Design starts evolution for Year N to N+4; Commercial design starts at year N-1 linked with the externalization rate at year N-1; IP license ASP (for the PHY IP and the controller IP when relevant) at year N-1; IP license ASP evolution for Year N to N+4; Externalization growth rate for Year N to N+4. Once all these parameters have been defined, you can use Excel, but the intelligence added by the analyst resides in the definition of these parameters… not in running Excel!This “Interface IP Survey 2010-2015 – Forecast 2016-2020” survey is applicable to:
- IP vendors
- Marketing, Strategy Planning
- Silicon Foundries, ASIC companies
- IP Marketing
- Ecosystem and IP Qualification Managers
- Chip Makers (IDM or Fabless)
- IP Purchasing Managers
- IP Outsourcing Managers
IPNEST is the leader on the IP dedicated surveys, enjoying this long customer list (including Top 2 EDA/IP vendors and Top 1 Semi as repeated customers, loyals year after year):
Silicon Creation, (US)
True Circuits, (US)
NW Logic, (US)
Analog Bits, (US)
Texas Instruments, (US)
HDL DH, (Serbia)
Inventure, (Japan) now Synopsys
- IP vendors