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CCIX Protocol Push PCI Express 4.0 up to 25G

CCIX Protocol Push PCI Express 4.0 up to 25G
by Eric Esteve on 06-08-2017 at 12:00 pm
Categories: IP, Synopsys

The CCIX consortium has developed the Cache Coherent Interconnect for Accelerators (X) protocol. The goal is to support cache coherency, allowing faster and more efficient sharing of memory between processors and accelerators, while utilizing PCIe 4.0 as transport layer. With Ethernet, PCI Express is certainly the most popular protocol in existing server ecosystems, in-memory database processing or networking, pushing to select PCIe 4.0 as transport layer for CCIX.

But PCIe 4.0 is defined by the PCI-SIG to run up to 16Gbps only, so the CCIX consortium has defined extended speed modes up to 25Gbps (2.5Gbps, 8Gbps, 16Gbps, 25Gbps). The goal is to allow multiple processor architectures with different instruction sets to seamlessly share data in a cache coherent manner with existing interconnects, boosted up to 25Gbps to fulfill the bandwidth needs of tomorrow applications, like big data analytics, search machine learning, network functions virtualizations (NFV), video analytics, wireless 4G/5G, and more.

How to implement cache coherency in an existing protocol like PCIe? By inserting two new packet based transaction layers, the CCIX Protocol Layer and the CCIX Link Layer (in green in the above picture). These two layers will process a set of commands/responses implementing the coherency protocol (think MESI: Modified, Exclusive, Shared, Invalid and the like). To be noticed, these layers will be user defined, Synopsys providing the PCIe 4.0 controller able to support up to 16 lanes running at 25Gbps. And the PCI Express set of command/responses will carry the coherency protocol command/responses, acting as a transport layer.

The internal SoC logic is expected to provide the implementing portion of the coherency, so the coherency protocol can be tightly tied to CPU, offering opportunities for innovation and differentiation. Synopsys consider that their customers are likely to separate data path for CCIX traffic vs “normal” PCIe traffic, and the PCI Express protocol offers Virtual Channels (VC), these can be used by CCIX.

The PHY associated with the CCIX protocol will have to support the classical PCIe 4.0 mode up to 16GBbps (2.5GT/s, 5GT/s, 8GT/s, 16GT/s) and also Extended Speed Modes (ESM), allowing Extended Data Rate (EDR) support. ESM Data Rate0 (8.0GT/s or 16.0 GT/s) and ESM Data Rate1, defined for 20.0 GT/s or 25.0 GT/s.

ESM can support four operations:
1PCIe compliant phase (the Physical Layer is fully compliant to PCIe spec

2Software discovery, the System Software (SW) probes configuration space to find CCIX transport DVSEC capability

3.Calibration: components optionally use this state to calibrate PHY logic for upcoming ESM data rate

4 Speed change: components execute Speed Change & Equalization according with the same rules as PCIe specification

The CCIX controller proposed by Synopsys gets all features of the PCIe controller, supporting all transfer speeds from 2.5G to 16G and ESM to 25G. The digital controller is highly configurable, supporting CCIX r2.0, PCIe 4.0 and Single Root I/O Virtualization (SR-IOV), being also backward compatible with PCIe 3.1, 2.1 and 1.1. The controller supports End Point (EP), Root Port (RP), Dual Mode (EP and RP) and Switch, with x1 to x16 lanes.

On the application side, the customer can select Native I/F or AMBA I/F, and dedicated CCIX Transmit and CCIX Receive application interfaces. The interface between the controller and the PHY is PIPE 4.4.1 compliant with CCIX extensions for ESM-capable PHYs. To support 25G, Synopsys proposes the multi-protocol PHY IP in 16nm and 7nm FinFET, compliant with Ethernet, PCI Express, SATA and the new CCIX and supporting for chip-to-chip, port side & backplane configurations.

Because CCIX/PCIe 4.0 solution targets key applications in the high-end storage, data server and networking segments, reliability is extremely important. The IP solution offers various features to guarantee high Reliability, availability and serviceability (RAS), increasing data protection, system availability and diagnosis, including memory ECC, error detection or statistics.

I am familiar with the PCI Express protocol since 2005, when I was marketing director for an IP vendor selling the controller (at that time PCIe 1.0 at 2.5 Gbps), and Synopsys was already the leader on the PCIe IP segment. Twelve years later, Synopsys is claiming 1500 PCie IP design-in!

If we restrict to the PCIe 4.0 specification, Synopsys is announcing 30 design-in in various applications, like enterprise (20 in Cloud Computing/Networking/Server), 3 in digital home/digital office, 5 in storage and 2 in automotive. Nobody would have forecasted the PCIe penetration in automotive 15 years ago, but it shouldn’t be surprising to see that after mobile (with Mobile Express) and Storage (NVM Express), the protocol is selected to support cache coherent interconnect for accelerator specification.

By Eric Esteve from IPnest

More about DesignWare CCIX: DesignWare CCIX IP Solutions

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Active Voice

Active Voice
by Bernard Murphy on 06-08-2017 at 7:00 am
Categories: Ceva, IoT, IP, Mobile

Voice activated control, search, entertainment and other capabilities are building momentum rapidly. This seems inevitable – short of Elon Musk’s direct brain links, the fastest path to communicate intent to a machine is through methods natural to us humans: speech and gestures. And since for most of us speech is a richer channel, there has been significant progress on voice recognition, witness Amazon Echo, Google Home and voice-based commands in your car.


Of course there’s a lot of significant technology behind that capability and CEVA is an important player in making that happen. As one example, when you say “OK Google” into your Galaxy S7, a CEVA DSP core inside a DSPG chip provides the platform to listen for and process that command. According to CEVA, the reason Samsung chose that solution over an implementation in the Snapdragon A20 ultra-low power island was that the CEVA/DSPG implementation is even lower power, allowing for always-on listening, even when the screen is off.

Always-on listening is one of several important factors in making voice-control ubiquitous. CEVA recently hosted a webinar, jointly with Alango Technologies, to provide insight into their solutions in this important space. In (acoustic) near-field applications such as in a smartphone, or even in smart microphones, ultra-low power is obviously important. CEVA promotes the CEVA-TL410 for ultra-low power in always-on near-field applications, such as the voice-sensing application used in the Galaxy S7.


The primary focus of this webinar was on high performance applications such as smart speakers / assistants. Here far-field performance become very important, contending with long distances (10 meters in one example), ambient noise, echoes, reverberation and potentially multiple voices. Here CEVA discussed application of the CEVA-X2. According to Eran Belaish (Product Marketing for audio, voice and sensing), building the speaker part of such a device is relatively straightforward. Complexity comes in building the smart part where there is a need to provide sophisticated processing for acoustic echo cancellation and noise reduction, and beamforming from an array of microphones to support intelligent voice processing.


Eran broke down the structure of the audio and sensing part of this solution first into voice activity detection (VAD), like the ultra-low power solution mentioned above. This is followed by PDM to PCM conversion, also in hardware, and then the real smarts for far-field support in a range of audio/voice functions running on the DSP. With a CEVA-based VAD, you still start with ultra-low standby power, which you’ll see later is an important advantage.


The company has an impressive slate of ecosystem partners to provide this functionality (together with their own software of course). Alango presented their software solution for acoustic echo cancellation, beamforming and noise reduction, in their voice enhancement package (VEP) running on the CEVA-X2 platform. All far-field solutions today use multiple microphones for 360[SUP]o[/SUP] coverage, from as few as two to as many as 8, and more can be supported, so this is where high quality voice processing must start. VEP manages echo cancellation for each microphone, then beamforms to produce as many beams as required from the set of microphones (perhaps 8 beams from 4 microphones) and then optionally performs noise suppression on each beam. These beams are then passed on to the automatic speech recognition (ASR) or keyword recognition (KWR) software.

Alango presented impressive results of experiments they ran to show improvements in voice trigger recognition rates (as detected by Sensory voice trigger technology for a trigger like “OK Google”) at varying distances and in the presence of noise as the number of microphones increased. Clearly adding more microphones, together with VEP, greatly improves detection accuracy at distance in noisy environments. That’s why the latest revs of Amazon Echo have 7 microphones.

Bu there’s a problem for existing implementations. Eran talked in the Q&A about the Amazon assistants. Many of these devices are wired – they must connect to a power outlet. This supports always-listening mode but isn’t friendly to portability. Amazon introduced the Tap to offer portability, but portable means battery powered, requiring low power when standing-by, which is why you must tap the device to turn it on before it will start listening. Still, the battery would last a few months in this usage. But tapping isn’t very convenient either, so Amazon released a software update which eliminated the need for a tap – the device was always listening. Unfortunately battery life dropped to 8 hours!

DSPG (whose ultra-low power solution is based on CEVA, see above), demonstrated together with another partner (Vesper) for microphones that they could replace the tap detector with the always-on KWR solution described above, running of course off the same device battery. Battery life shot back up to 3 months. This is impressive; in effect, always-on KWR using this technology consumes negligible power compared to power consumption during active use.

There’s a lot more you can learn about in the webinar. CEVA have a demo unit, there was discussion on voice isolation (differentiating between different speakers speaking at the same time but at different locations), voice biometrics / voice-printing and many other topics requiring more AI, natural language recognition, perhaps more sensor fusion to combine vision recognition with voice/speech recognition to refine inferences. Eran noted that advances here are being worked, at CEVA and other places, but aren’t commercially available today. Still, all of this points very much to Eran’s opening position about the future of voice in electronics – it’s very bright!

You can watch the webinar HERE, learn more on CEVA’s voice/speech solutions HERE and more on their sensor fusion capabilities HERE.

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EDA Powered by Machine Learning panel, 1-on-1 demos, and more!

EDA Powered by Machine Learning panel, 1-on-1 demos, and more!
by Daniel Nenni on 06-07-2017 at 12:00 pm
Categories: EDA, Solido

DAC is upon us again! The Design Automation Conference holds special meaning to me as it was the first technical conference I attended as a semiconductor professional, or professional anything for that matter. That was 33 years ago and I have not missed one since. This year my wife and I both will be walking the DAC floor and it would be a pleasure to meet you so be sure and say hi if you see us.


My good friends at Solido will again be giving out SemiWiki.com pens so if you were to catch me in a booth that would be the first place to look. Solido has a lot going on at DAC so be sure and get them on your schedule:

Join Solido at the 54th Design Automation Conference (DAC) (Booth #1113) in Austin, TX at the Austin Convention Center from June 19-21, 2017. DAC is the premier conference for design and automation of electronic systems, Solido will again be offering a panel discussion, networking opportunities, and 1-on-1 product demos at this year’s event.

Be sure to register to attend Solido’s panel discussion, “EDA Powered by Machine Learning” on Monday, June 19, 10:30am, Room 10AB, Austin Convention Center, Austin, TX.

Machine Learning is leaving its mark in a variety of fields, even EDA. This panel will focus on opportunities and examples of how this disruptive technology is addressing various challenges in semiconductor design. Discover how machine learning technologies are already providing disruptive runtime, resource, and productivity benefits in variation-aware design and characterization, and much more, with panelists Ting Ku (NVIDIA), Sorin Dobre (Qualcomm), Eric Hall (Broadcom), Jeff Dyck (Solido), and Amit Gupta (Solido) moderating.

Registration for the “EDA Powered by Machine Learning” panel can be found here: https://www.solidodesign.com/dac-2017-panel-registration/

At DAC, Solido will also be hosting 1-on-1 demonstrations showcasing Variation Designer and newly-launched ML Characterization Suite from Monday June 19 through Wednesday June 21. Variation Designer is the world’s leading technology in variation-aware design for standard cells, memory, and analog/RF, providing full design coverage in orders-of-magnitude fewer simulations, but with the accuracy of brute force techniques. Solido’s new ML Characterization Suite uses machine learning technologies to accelerate characterization of standard cells, memory, and I/O, reducing library characterization time without compromising accuracy.

Available demos include Variation Designer for Memory, Analog/RF, or Standard Cell Design and ML Characterization Suite Predictor or Statistical Characterizer. Registration for a 1-on-1 Solido Demo can be found here: https://www.solidodesign.com/dac-registration/

After Monday morning’s panel and exploring everything DAC has to offer, set aside time to join Solido at their first DAC Rooftop Party at Terrace59 @ Speakeasy (412 Congress Ave D. Austin, TX) on Monday, June 19, 7pm. Appetizers and host bar provided. Space is limited so make sure to RSVP here: http://www.solidodesign.com/dac-2017-rooftop-party/

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Webinar: How RTL Design Restructuring Helps Meet PPA

Webinar: How RTL Design Restructuring Helps Meet PPA
by Bernard Murphy on 06-07-2017 at 7:00 am
Categories: Defacto Technologies, EDA

To paraphrase an Austen line, it is a truth universally acknowledged that implementation, power intent and design hierarchy don’t always align very well. Hierarchy is an artifact of legacy structure, reuse and division of labor, perhaps well-structured piecewise for other designs but not necessarily so for the design you now face, which has a different power objectives and different physical constraints. Power and implementation want to be at least partly flat which doesn’t blend well with a rigid hierarchy.


REGISTER NOW for this webinar on Tuesday, Jun 13, 2017 10:00 AM – 11:00 AM PDT

You can see this in several examples. It often makes sense to merge common power islands to optimize power switching and PG routing, but the RTL hierarchy gets in the way. You could manually restructure the hierarchy, but that can be a lot of work, not just in making the changes but also in verifying you didn’t break anything. As another example, a classic trick in P&R is to run feedthrus through a block to optimize timing for long runs. This could be handled nicely purely within physical design before complex power strategies became common. Now if the blocks involved sit in different power domains, these changes must also be reflected in netlists for power verification. Or think about a timing critical I/O interface in a legacy design, now repurposed to a derivative. That interface perhaps sat deep in a hierarchy in the original design but must be moved to a different hierarchy to better suit floorplanning objectives in the derivative. But all connections to the rest of the logic must be preserved.

In this webinar, DeFacto will present their solution for RTL design restructuring, within their STAR platform, to automate this complex task. This appears so easy you might well consider restructuring as a new aid to further optimize power management and area in your design.

REGISTER NOW

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AI Being Used from Probing to Simulation

AI Being Used from Probing to Simulation
by Daniel Payne on 06-06-2017 at 12:00 pm
Categories: EDA, Platform Design Automation
4 Comments

The 54th annual DAC event is fast approaching, so I hope to see many of you in Austin on June 18-21. The phrases Machine Learning and AI are growing in all areas of software, so I’m glad to see it appearing in more EDA tool offerings over the past year or so. One company that I plan to visit at DAC is Platform Design Automation because they offer both hardware and software tools to engineers that need to characterize silicon and then create device models, PDK (Process Design Kits) and FDK (Foundry Design Kits). Here’s an overview of what to see from Platform DA at booth 1929:

  • A portable die prober for small dies
  • A fast semiconductor parameter (IV/CV) analyzer
  • The NC300 series 1/f noise characterization system
  • Device modeling that is AI-driven
  • An automatic PDK QA and signoff tool

Related blog –Noise, The Need for Speed and Machine Learning

These instruments and software can be shown in three groups:

Two new things that you will see at DAC include:

  • Advanced Semiconductor Education Kit
  • New Generation of Low Frequency Noise Modules

Related blog – Something New for Semiconductor Parametric Testing

The specifications for the low frequency noise modules look impressive with a 200V bias and 1A current range.

PDA has their headquarters in Beijing and branch offices in both Shanghai and Hsinchu, so if you’re from North America then it’s a much shorter flight to Austin, Texas to speak with these folks in person to better understand how they can help you in the process-design integration area.

Related blog – SPICE Model Generation using Machine Learning

If you need some services to quickly understand how to use the test instruments, device modeling, FDK and PDK as it applies to your specific manufacturing node then setup a DAC meeting and start the relationship. The benefits to your company are a higher design quality, improved IC product yields and better IC reliability. Engineers at PDA have many years of experience in this specialized realm and has already worked with many design houses and foundries.

Related blog – Is That PDK Safe to Use Yet?

At DAC you can see also see their latest presentation, “Low-Cost, High-Accuracy Variation Characterization for Nanoscale IC Technologies via Novel Learning-based Techniques.“

When you visit PDA at DAC be sure to ask for either Albert Li or Riko Radojcic.

Albert is President at PDA and has 15 years of experience. He founded the company and previously worked at Accelicon, then Agilent Technologies acquired Accelicon in 2012. On the education side Mr. Li earned a BS EECS at the Tsinghua University plus an MSEE from Vanderbilt University.

Riko Radojcic recently joined PDA and has been in the semiconductor industry for 30 years now in a variety of engineering, management and consulting roles. He has worked at companies like Qualcomm, PDF solutions, Cadence and Unisys.

Here’s where booth 1929is located for PDA at DAC this year.

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ClioSoft & DAC : Booth 613 – Collaborative Design, Design Data & IP Management and Design Reuse

ClioSoft & DAC : Booth 613 – Collaborative Design, Design Data & IP Management and Design Reuse
by Mitch Heins on 06-06-2017 at 7:00 am
Categories: Cliosoft


It’s time again to gather for the next Design Automation Conference (DAC). This will be the 54[SUP]th[/SUP] such meeting and this year it runs from June 19[SUP]th[/SUP] – 21[SUP]st[/SUP] in the Live Music Capital of the World, Austin Texas. Put on your best duds, boots and cowboy hat and make your way to Texas.

While you are there make sure to stop by the ClioSoft booth, #613, and learn about ground breaking advancements in System on-Chip (SoC) design and intellectual property (IP) management. ClioSoft will be giving demos and leading discussions on the challenges of SoC design and how their design data management software, SOS, is helping companies like Analog Devices, Google and TSMC to manage their projects.

State-of-the art SoCs can now be made of multiple billions of transistors with a multitude of different IPs (both 3[SUP]rd[/SUP] party and internally developed) being used from all over the world. Design teams continue to get bigger and include engineers from multiple disciplines including hardware, software, design verification, packaging, manufacturing testing and yield to name a few. All these disciplines have their part to play and companies are being challenged to bring these disparate groups together to form virtual teams to make successful products. ClioSoft’s products are used to enable this collaboration even when teams are dispersed across thousands of miles and multiple different time zones.

In addition to demonstrating their SOS and Visual Design Diff (a slick capability that enables chip designers to visualize and track changes between different versions of schematics and layouts) products, ClioSoft will also be showcasing their new designHUB software. The designHUB platform is a unique technology, which helps companies take design reuse to a whole new dimension. It provides an IP reuse ecosystem, which encompasses a knowledge base for both internal and 3[SUP]rd[/SUP] party IPs to help designers leverage the past experiences of designers.

In addition, by providing a dashboard for designers and projects alike, it brings another dimension to collaboration within a company. The designHUB platform enables the creation and sharing of IP meta-data that can be used by teams to search, view, qualify and select IP for their designs. it also tracks IP usage including 3[SUP]rd[/SUP] party IPs and mitigates unauthorized usage of the IPs within a company. When visiting be sure to have ClioSoft explain their use of crowdsourcing within designHUB to enable knowledge transfer between IP developers and design teams that use the IP.

While you are at DAC you may also want to check out the DAC panel discussion titled, ‘Have Third Party IPs Killed Internal IP Development?’. This panel will discuss the pros and cons of using third party IPs and their impact on internal IP development. Ranjit Adhikary, ClioSoft VP marketing, will be on this panel along with Rich Wawrzyniak of Semico Research Corp, Philippe Quinio of ST Microelectronics, Daniel Cooley of Silicon Labs and Andy Hawkins of Cypress Semiconductor. The panel will be held Wednesday June 21 from 3:30-5:00p in Ballroom G.

And what would DAC be without a little fun and relaxation? The ClioSoft team will be hosting a DAC party Tuesday evening, June 20[SUP]th[/SUP] starting at 7:00p. The party will be held at Micheladas in downtown Austin. This is one of Austin’s many venues made famous by the South-by-Southwest events that happen each year. There’s no admission fee and ClioSoft will be sponsoring complimentary beers, margaritas, wine and hors d’oeuvres. It’s a great opportunity to relax after a long day at the DAC show and network with friends and colleagues. Inquire now with ClioSoft as the party is by invitation only and will have limited invitations.


See also:

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Webinar: Achieving Very High Bandwidth Chip-to-Chip Communication with the Interlaken Interface Protocol

Webinar: Achieving Very High Bandwidth Chip-to-Chip Communication with the Interlaken Interface Protocol
by Eric Esteve on 06-05-2017 at 12:00 pm
Categories: Events, Open-Silicon, Semiconductor Services

Open Silicon will hold this webinar on June 13th at 8 am PDT (or 5 pm CE) to describe their Interlaken IP core, and how to achieve very high bandwidth C2C communication in various networking applications. To be more specific, the Interlaken protocol can be used to support Packet Processing/NPU, Traffic Management, Switch Fabric, Switch Fabric Interface, Framer/Mapper, TCAMs or Serial Memory (INLK-LA). Open Silicon is marketing the Interlaken IP core for ASIC, but the networking industry also loves FPGA technology, offering fast Time-to-Market (TTM) and, even more important, well-known advantage of flexibility, allowing to support protocol evolution in the field. The Interlaken protocol also supports FPGA implementation.

There are significant demands for performance and bandwidth in high-speed communications, and pressure to step up the pace on technological advancements. The panelists will outline the challenges that designers of advanced communication applications encounter with things like controller specification, latency, various SerDes architectures and implementation. They will outline use cases and discuss the key technical advantages that the Interlaken IP core offers, such as 1.2 Tbps high-bandwidth performance and up to 56 Gbps SerDes rates with Forward Error Correction (FEC), as well is its multiple user-data interface options. They will also discuss the architectural advantages of the core, such as its flexibility, configurability and scalability.

I am very honored as I have been asked by Open Silicon to be the moderator of this webinar. But you must deserve such honor and to some homework to be well prepared, and I will share with Semiwiki readers some bits of information about Interlaken, so you (the reader) will also be well prepared!

Meeting these requirements from the Interlaken Alliance will ensure interoperability for different implementations (don’t forget that Interlaken is a chip-to-chip communication protocol, so interoperability is key):

•Supports multiple parallel lanes for data transfer at physical level
•User interface packet based. With each packet consisting of multiple bursts
•Simple control word to delineate packet and bursts
•Protocol independence from the number of SerDes lanes and SerDes rates
•Ability to communicate per-channel backpressure
•Performance scales with the number of lanes

I think that most of the points in this list are clear enough, with probably the notable exception of per-channel backpressure. If you are (like me) not aware about this concept, you will have to dig to understand the meaning and implication of per-channel backpressure. Don’t worry, I did it, and found this definition:
In queueing theory, a discipline within the mathematical theory of probability, the backpressure routing algorithm is a method for directing traffic around a queueing network that achieves maximum network throughput which is established using concepts of Lyapunov drift. Backpressure routing considers the situation where each job can visit multiple service nodes in the network. It is an extension of max-weight scheduling where rather each job visits only a single service node.

To make it simple:

[LIST=|INDENT=1]

  • Max-weight routing: each job –> a single service node
  • per-channel backpressure: each job –> multiple service node

    Using the second allows to achieves maximum network throughput.

    To continue with the definitions, when looking at the features supported by Open Silicon Interlaken IP core, I found this one: “Supports Interlaken Look Aside protocol”. Look Aside?

    We can find the meaning of this look aside function, extensively used in packet based processing, with some examples of look-aside devices:

    • Search engines, which receive small portions of a packet header
    • Policing engines, which receive small portions of a packet header, or a simple command set
    • Value-add memories, which may perform mathematical operations or linked-list traversals in addition to reads and writes
    • Queuing and scheduling engines which dictate the packet transmission order to a packet buffer device

    The basic idea is to process only a small portion of a packet, aside from the data path. Looking at this chart, you immediately understand the benefit of this look-aside protocol: the smaller the message size (in abscissa), the higher will be the message rate.

    I am sure that you will learn a lot more about Interlaken if you attend this webinar from Open Silicon. Even if the Interlaken protocol is based on some complex concepts, don’t forget that the elegance of Interlaken is his simplicity and high flexibility, as the controller can interface with any SerDes with rates between 3.125 Gbps and 56 Gbps to support very high bandwidth chip-to-chip communication.

    To register to the webinar, click here

    Eric Esteve     from IPnest

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    Tools for Advanced Packaging Design Follow Moore’s Law, Too!

    Tools for Advanced Packaging Design Follow Moore’s Law, Too!
    by Tom Dillinger on 06-05-2017 at 9:00 am
    Categories: EDA, Siemens EDA

    There is an emerging set of advanced packaging technologies that enables unique product designs, with the capability to integrate multiple die, from potentially heterogeneous technologies. These “system-in-package” (SiP) offerings provide architects with the opportunity to optimize product performance, power, cost, and area/volume, with the capabilities to: merge processing with local memory (e.g., HBM); consolidate multiple die in rigid-substrate 2D (e.g., CoWoS) or 2.5D configurations (e.g., utilizing vertical vias through an interposer between layers); or, molding (multiple) die in a high pin count, low-cost module (e.g., FOWLP, with redistribution layers to package bumps).

    In many ways, the complexities of die and advanced package technology selection are analogous to the challenges faced when targeting an integrated design to the optimum process node with appropriate PPA (and available, qualified IP).

    As Moore’s Law has been consistent throughout the process generations, chip physical design methodologies have similarly evolved to help manage the increasing circuit capacity and diversity. Specifically, chip physical implementation tools transitioned from a “flat” approach to a methodology incorporating hierarchical floorplanning, interface pin constraint management, and detailed APR algorithms. Design team specializations developed, with architects working on floorplan prototypes and PD experts addressing the intricacies of routing design rules and DFM/DFY requirements.

    Advanced package design shares a similar evolution – architects developing prototypes, with implementation experts completing the (bond wire or bump) die attach topologies, the signal/power routes, and the unique manufacturing patterns. SiP development tools traditionally provided a single cockpit, targeting the physical design expert – Mentor has just announced an evolution to their Xpedition product family, to address the “Moore’s Law of advanced package design flow” requirements.

    I recently spoke with Keith Felton, Product Marketing Manager with the Advanced IC Packaging Solutions group at Mentor, a Siemens Business. “New tools and flows are required, to support the challenges of high-density advanced packaging, or HDAP. Mentor is introducing two new products – Xpedition Substrate Integrator and Xpedition Package Designer.”, Keith highlighted.


    Figure 1. Xpedition Substrate Integrator and Xpedition Package Designer product positioning


    Figure 2. Design domains and data flow for xSI and xPD

    “xSI is specifically targeted to support package design prototyping. The definition of the overall design connectivity is used to develop the substrate, die placement and stacking data, and preliminary bond/ball physical assignments. Architects can integrate their design concept with the PCB (using Xpedition PCB). The optimized prototype is then forwarded to the xPD flow, for final development.”, Keith explained. The figure below illustrates how a bump assignment in xSI is co-designed with the PCB, spanning the board and package domains.


    Figure 3. Data exchange between xSI and Xpedition PCB

    The xSI environment integrates with HyperLynx DRC, for rule checking appropriate for initial definition (for all but the most intricate manufacturing checks). As with the hierarchical chip design flow, the architect using xSI can pass rules/constraints to detailed design – e.g., routed net shielding requirements.

    Xpedition Package Designer, or xPD, is the corresponding detailed implementation tool in the new HDAP methodology. Physical design expertise finalized the attach data (bond or bump) and power/signal routes. xPD provides designers with both a 2D and (highly illustrative) 3D design view, as illustrated below.


    Figure 4. 2D and 3D design views in xPD

    If the prototype definition requires modification, xPD can send updates back to the xSI architect – see the double-sided flow arrow between the two tools in the flow diagram above.

    The detailed design will incorporate the data appropriate for package manufacture – e.g., complex metal route and mesh fill patterns required to accommodate degassing (absorbed moisture removal at high temperature during deposition) and to minimize mechanical stress gradients in the final package. The verification of the design data will link to Mentor’s Calibre 3DSTACK, with robust algorithms/checks for the non-Manhattan geometry used in package design.

    Mentor has addressed the Windows versus Linux operating system environment differences between xPD and Calibre 3DSTACK, seamlessly to designers – the correlation between Calibre and xPD data is illustrated in the figure below; full DRC and LVS checking support is provided.


    Figure 5. Xpedition Package Designer and Calibre 3DSTACK data correlation

    The xPD environment also links to Mentor’s HyperLynx Fast3D algorithm for package parasitic extraction and model generation for signal integrity analysis. Mentor’s FloTHERM interfaces to xPD, as well, enabling a detailed thermal analysis of the package. Given the varying switching activity among the die and the disparate materials used (with thermal expansion coefficient differences) within the package, a thermo-mechanical stress reliability analysis is mandatory.

    Chip design methodologies have evolved to support the complexities afforded by Moore’s Law, from hierarchical floorplanning to detailed DFM/DFY checks. High-density advanced packaging technology also now requires a set of tools and flows that addresses both the early design optimization space and the manufacturability/reliability requirements, leveraging the expertise of different team members. Mentor’s new Xpedition Substrate Integrator and and Xpedition Package Designer directly addresses this new package design methodology.

    For more information on the new Xpedition Substrate Integrator and Xpedition Package Designer, please follow this link.

    -chipguy

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    An InFormal Chat

    An InFormal Chat
    by Bernard Murphy on 06-05-2017 at 7:00 am
    Categories: EDA, Synopsys

    Any sufficiently advanced technology is indistinguishable from magic, as the saying goes. Which is all very well when the purpose is entertainment or serving the arcane skills of a select priesthood, but it’s not a good way to grow a market. Then you want to dispel the magic aura, make the basic mechanics more accessible to a wider audience and push usage/applications rather than the mystical spells of the inner circle. After all, few of us have a deep understanding of how our smartphones work but now they’re used by virtually everyone.


    Some of what this takes is usability – we engineers never met a problem we believed couldn’t be solved by yet more engineering, in this case through better user experiences, more attuned to the way we think and even the way we communicate (touch, gestures, speech, …). But in some cases, widespread adoption also depends heavily on socializing the domain. Or, back on the magic analogy, showing how the trick is done – not professional magician to professional magician in magician-speak, but simply explained to us non-experts who just need to make the trick work to get our jobs done, along with a basic understanding of what happened behind the curtain (or inside the hat).

    Formal verification fits this description all too well. We know it does incredible things, providing complete proofs inaccessible to dynamic verification, but much of what is written about the domain today is expert to expert, full of math and strange terms like witness and bounded model-checking. Usage in some areas has been simplified but we still wonder how those kinds of verification fit into our overall test and coverage objectives. And other areas still look inaccessible to anyone but PhD experts who must understand bounded proofs, BDD versus ATPG versus SAT and how to mutter all the right incantations to sufficiently constrain (but not over-constrain) their proofs.

    All of which makes it very timely that Synopsys is launching a blog today called InFormal Chat, written by verification engineers for verification engineers. I’ve read some of the initial blogs. They’re informal and short, each a quick read to pull back the curtain on some aspect of formal verification. They don’t worry much about polished delivery – this is engineers talking to engineers with little marketing interference.

    Synopsys is clearly proud of the expertise they have built up in the VC Formal team, and in the product, and want to get the message out that they are a leading contender in this area. They’ll talk certainly about tool capabilities but they also want to help users and potential users better understand the magic. Some of the discussion will be on the mechanics of getting though formal analysis, like how to handle incomplete proofs and where to watch out for pitfalls. They’ll talk sometimes about advanced topics, such as how to build proofs for cache-coherency. And they are committed to providing thought leadership in the domain, in emerging problem domains and suggested solution approaches.

    This is a worthy direction to socialize formal verification and to convert more of us to being at least passable formal magicians. I’m told new posts should appear every couple of weeks. Together with a good search mechanism, this should be a valuable resource for all of us formal wannabees. You can find the link HERE.