SemiWiki – Page 546 – The Open Forum for Semiconductor Professionals

October 4, 2017December 27, 2023

Semiconductor IP on Fortune’s 2017 100 Fastest-Growing Companies List!

Semiconductor IP on Fortune’s 2017 100 Fastest-Growing Companies List!
by Daniel Nenni on 10-04-2017 at 7:00 am
Categories: AI, Automotive, Ceva, IoT, IP, Mobile

The Semiconductor IP market has always been a big draw for SemiWiki readership and I expect that to continue. One of the more interesting companies we have covered over the past 6+ years is CEVA, who is now on Fortune’s 2017 100 Fastest-Growing Companies List. In fact, CEVA is the ONLY semiconductor IP company on the list and they join semiconductor companies: Silicon Motion, NVIDIA, Cirrus Logic, Micro Semi, Skyworks, and IDT.

Gideon Wertheizer, CEO of CEVA commented: “Fortune’s acknowledgment of CEVA as one of the fastest growing public companies over the past three years is a testament to our successful expansion strategy which has enabled us to become a technology leader. Our platform IPs for 5G, deep learning, computer vision, voice assistants, Bluetooth and Wi-Fi are critical building blocks for all smart and connected devices. We are very proud to feature on this list alongside some of the world’s most prominent companies.”

We are at the intersection of three trends that are making Semiconductor IP even more interesting moving forward: The advent of systems companies making their own chips (systems companies now dominate the fabless semiconductor ecosystem and I expect that trend to continue), Artificial Intelligence is a boom to Semiconductor IP (deep learning and computer vision for example), and M&A – the mega acquisition of ARM by Softbank last year followed by the Chinese acquisition of Imagination Technologies this year.

CEVA stock, by the way, was around $15 when we started covering them and today it is over $40.

For the record, CEVA is the leading licensor of signal processing IP that is used for: Image and Computer Vision, Deep Learning, Audio, Voice, Speech, and Sensor Fusion. CEVA also provides Wireless Communication, and connectivity IP. The target markets include: Mobile, Wearable, Automotive, Industrial and Consumer IoT, which just about covers every topic on SemiWiki.com, absolutely.

CEVA is also a very well run company with more than 300 employees in the US, Israel, Europe and Asia. To date more than 8 billion CEVA-powered chips have been shipped worldwide. Given the exploding silicon growth in IoT, Automotive, Robotics, Drones, Mobile, Wearables, and dozens of other vertical markets, we should hit a trillion CEVA-powered chips in the not too distant future.

Bottom line: Semiconductor IP is a critical enabler of the fabless semiconductor ecosystem.

About CEVA, Inc.
CEVA is the leading licensor of signal processing IP for a smarter, connected world. We partner with semiconductor companies and OEMs worldwide to create power-efficient, intelligent and connected devices for a range of end markets, including mobile, consumer, automotive, industrial and IoT. Our ultra-low-power IPs for vision, audio, communications and connectivity include comprehensive DSP-based platforms for LTE/LTE-A/5G baseband processing in handsets, infrastructure and machine-to-machine devices, advanced imaging, computer vision and deep learning for any camera-enabled device, audio/voice/speech and ultra-low power always-on/sensing applications for multiple IoT markets. For connectivity, we offer the industry’s most widely adopted IPs for Bluetooth (low energy and dual mode), Wi-Fi (802.11 a/b/g/n/ac up to 4×4) and serial storage (SATA and SAS). Visit us at www.ceva-dsp.com and follow us onTwitter,YouTube andLinkedIn.

October 3, 2017June 14, 2019

Photonics Summit Delivers High-Bandwidth Discussion on State of Silicon Photonics

Photonics Summit Delivers High-Bandwidth Discussion on State of Silicon Photonics
by Mitch Heins on 10-03-2017 at 12:00 pm
Categories: Cadence, EDA, Silicon Photonics

On September 6, 2017, Cadence Design Systems, Lumerical Solutions and PhoeniX Software hosted their second Photonics Summit. As with last year’s summit, this was a two-day event, with the first day including in a myriad of photonics presentations and the second day being a hands-on workshop. The hands-on workshop taught attendees how to use the Cadence, Lumerical and PhoeniX EPDA (electronic/photonic design automation) flow to put together a photonic system comprised of a photonic integrated circuit (PIC), a CMOS ASIC and a laser light source, all within a system-in-package (SiP) configuration using a silicon-based interposer.

While the hands-on day was very interesting I want to focus on the first day’s presentations. To paint with a broad brush, the overarching theme of the presentations seemed to be that there is an explosion in the breadth of photonics applications and the technology being applied across the entire photonic manufacturing ecosystem. Read on and you’ll see that integrated photonics is opening up applications that up till now have not been feasible with standard electronics.

In the past, I’ve told people that working on photonics is sort of like going back in time to the early IC days of the 1980’s. I now amend that premise. Instead, it’s like watching history repeat itself but on fast-forward. The progress shown and the number of people working the technology challenges is simply astounding. The collection of presenters at this year’s summit reflected this as they had presentations covering systems applications, wafer manufacturing and process design kits, packaging, automation for assembly and test and new design characterization Figures-of-Merit being applied to keep up with the dramatically increasing bandwidths made available through integrated photonics.

The first presentation was given by Andrew Wheeler of Hewlett Packard Enterprise (HPE) Labs, entitled ‘Photonics: the fabric of our (future) lives’. That’ a pretty bold statement when you think about it but Andrew unfolded a scenario that we are watching come true even as I post this article. Per Andrew, the amount of data we are processing is changing dramatically.

As a few examples, in 2016, Facebook members were posting an average of 4 Petabytes (PB) of data a day. That’s the equivalent of 4,000 Terabytes or 4,000,000 Gigabytes. In 2017, Walmart’s daily transaction database reached 40 PB and, in the not too far away future of 2020, it is estimated that automobiles employing driver assistance capabilities will generate around 40,000 PB daily! The advent of the internet-of-things (IoT) will exacerbate this further as we will have around 8 billion people on the planet using roughly 20 billion mobile devices to generate over 100 billion social infrastructure interactions per day using over 1 trillion apps.

HPE predicts that this data explosion will precipitate a massive change in the way we process data, moving from a processor-centric compute model to one that is a memory-driven compute model. Up till now, this has not been feasible due to bandwidth and latency limitations of electronics technology between processors and memory. Integrated photonics will change this as photonics interconnects eliminate the distance factor between processors and memory, facilitating entirely new compute topologies. It doesn’t stop there though. HPE also envisions photonic-based computing as opposed to simply using photonics as an interconnect fabric.

Along a similar vein, Darius Bunandar of MIT took photonic computing to a new level with a discussion how photonics enables Quantum computing. Photonics enables the creation of single photon sources and single-photon detectors which are the basic building blocks of Quantum computing. There is still much work to be done but the introduction of integrated photonics has already spawned more than a couple new startups in this space. Darius also gave another example of advanced photonic computing showing the realization of photonic-based deep neural networks (DNNs). These DNNs are the starting point of some very exciting work in artificial intelligence including image recognition and inferencing, running at the speed of light.

While this all sounds a little like science fiction, the rest of the speakers filled in the gaps for how these PICs will be manufactured, packaged, assembled and tested. Michael Rakowski from imec in Belgium gave an update on their silicon photonic processes that can now readily enable 50G NRZ photonic modulation and detection including how they are now tightly integrating CMOS ICs with PICs using 3D assembly techniques. These are the same techniques that were part of the Summit’s 2[SUP]nd[/SUP] day hands-on training session.

Paul Fortier of IBM followed with an excellent overview of automated high-throughput integrated photonics assembly capabilities. This presentation was especially interesting to see as one of the drawbacks for integrated photonics so far has been the cost of the PICs. Unlike electronic ICs, the packaging and assembly of photonics onto boards actually represents up to 80% of the overall cost of the PIC solution (just the inverse of electronics). Per Paul’s presentation, one of the key items now being developed is the ability to use existing electronic pick and place technology to assemble PICs on the boards. The tricky part here is that alignment must be precise for photonics to work correctly. IBM sees progress on three fronts, passive alignment of fiber arrays using v-groove technology, the use of self-aligning structures for polymer ribbon connectors and the use of flip-chip technologies that use solder-induced self-alignment. The common component in all of these is the idea of automated (hands-off) alignment of off-chip connections to the PIC.

Lastly, there were presentations from Dan Neugroschl of Chiral Photonics who work on photonics packaging and test and Pavel Zivny of Tektronix who works on tester and measurement equipment used for photonic testing. Not to beat a dead horse, but both Dan’s and Pavel’s presentations again showed how much infrastructural work has been going on to support integrated photonics. There’s probably two articles worth of information to share from those presentations that will need to wait for another day.

Suffice it to say, this summit turned out to be a very high-bandwidth presentation on the state of integrated silicon photonics. It was time well spent and I can’t wait to see what will transpire between now and the next summit.

If you are interested to learn more about what all of these gentlemen presented you can find their presentations at the link below.

October 3, 2017

Adoption, Architecture and Origami

Adoption, Architecture and Origami
by Bernard Murphy on 10-03-2017 at 7:00 am
Categories: Arm, Arteris, EDA, Events, IP, Oski Technology, Semiconductor Services

Last week I sat in on Oski’s latest in a series of “Decoding Formal” sessions. Judging by my first experience, they plan and manage these events very well. Not too long (~3 hours of talks), good food (DishDash), good customer content, a good forward-looking topic and a very entertaining wrap-up talk.

Continue reading “Adoption, Architecture and Origami”

October 2, 2017March 7, 2022

TSMC Teamwork Translates to Technical Triumph

TSMC Teamwork Translates to Technical Triumph
by Tom Simon on 10-02-2017 at 12:00 pm
Categories: IP, Semiconductor, Siemens EDA, Silicon Creations, TSMC

Most people think that designing successful high speed analog circuits requires a mixture of magic, skill and lots of hard work. While this might be true, in reality it also requires a large dose of collaboration among each of the members of the design, tool and fabrication panoply. This point was recently made abundantly clear at the TSMC Open Innovation Platform (OIP) Forum held in Santa Clara on September 13th. Indeed, the entire OIP ecosystem was established by TSMC to encourage this kind of collaboration. Over the years it has enabled significant advances in electronic product design and delivery.
Continue reading “TSMC Teamwork Translates to Technical Triumph”

October 2, 2017October 5, 2021

eFabless and Silego $15,000 Go Configure Design Challenge Series!

eFabless and Silego $15,000 Go Configure Design Challenge Series!
by Daniel Nenni on 10-02-2017 at 7:00 am
Categories: Semiconductor Services

The eFabless and Silego “Go Configure Design Challenge Series” is the first of its kind to allow a global community of designers to implement widely used functions using GreenPAK™ Configurable Mixed-signal ICs (“CMICs”) and its intuitive drag-and-drop software GUI. The efabless platform will serve as the crowd source design platform on which the CMIC hardware designs will be submitted. This design challenge is intended to be the first step in establishing a future marketplace for innovators and their designs.

For more information here is a CEO interview with John Teegen of Silego Technology and Mike Wishart of efabless. John and Mike discuss community design of Silego Configurable ICs and the Go-Configure Design Challenge.

Hi John and Mike. John, tell our readers a bit about Silego.
JT: Dan, we may be one of the more impactful under-the radar companies that you will ever see. In fact, Semico called Silego the “best kept secret in Silicon Valley”. We pioneered and are the market leader in Configurable Mixed-signal ICs, or CMICs, and we have shipped over 3 billion devices since their introduction. You can think of CMICs as bringing the convenience of FPGA’s to mixed-signal. Each device contains analog components, discrete digital logic, and power components that can be integrated through software into highly configurable, small, easy to use, low cost ICs. Customers get faster time to market, reduced system parts count, lower power consumption, less board space and reduced BOM costs.

Six generations of CMICs have been introduced, with increasing functionality and design tool enhancements. The design process of a CMIC is now extremely intuitive and very comparable to designing circuits on PCBs. With minimal training, a wide variety of designers can now design their own CMIC with no NRE or production commitment.

That is why we are excited about the Go Configure Design Challenge Series and partnership with efabless. This was the brainchild of Mike Noonen, Silego’s Vice President of Sales and Business Development, in collaboration with Mike Wishart and Mohamed Kassem, co-founder of efabless. The objective is to educate and enable an engaged community on the efabless platform that can respond to design requests from customers of all sizes and open the IoT market to the power of Silego mixed-signal-on-demand. We see it as a key step in growing our business and introducing a better way to design to thousands of designers worldwide.

Mike, bring us current on efabless.
MW: As you recall, efabless.com is the world’s first community engineering platform for electronics solutions. We connect a global community of mixed-signal designers with customers and enable them with processes and a unique community-centric marketplace to develop, share and commercialize products. We introduced our solution for community created IP with a design challenge for X-FAB, our foundry partner, last November. We released our community created IC platform in June. With Silego we now offer community development of programs, we call “soft designs”, for configurable IC parts. The Challenge Series is the first step in our support of Silego and configurable ICs. We will also provide the marketplace to connect designers with opportunities and to showcase their designs.

How doesthe Silego partnership fit into your model?
MW: We are very excited about our relationship with Silego. This is a strong validation of the principle of community design and the Go Configure Design Challenge is a first of its kind for the sector. Remember, we founded efabless on the principle that a connected and a collaborative community of highly skilled innovators is a catalyst for IoT and smart hardware to reach its fullest potential. IoT and smart hardware products are often created by companies that do not have the internal core expertise in electronics development or expertise in a very specific area of hardware design. An example would be a shoe company making a Bluetooth connected running sneaker. This new class of innovators needs a broad community with the time and resources to turn an idea into a product. And, in particular, they need analog and mixed-signal to connect the digital “smarts” of their products with the physical world. That’s where Silego-on-efabless comes in.

JT: The Silego GreenPAKs are a terrific solution for community design. They are easy to learn and easy to use. With our devices, the efabless community can offer Configurable Mixed-signal IC solutions with incredibly fast time to market for a wide range of applications.

MW: Silego also greatly expands the community of designers beyond the universe of analog and mixed-signal IC designers to PCB and other system level engineers.

Tell us about the Go Configure Design Challenge
JT: The Go Configure Challenge is obviously a play on words – effectively who would have thought that designers from around the world could learn our platform, create designs and get global recognition for doing so. Oh, yes, and win prizes. In the Challenge Series, we will be tasking the community with designing various industry standard functions and the designs will be judged by Silego on the quality of the design and the documentation. We have chosen 10 separate industry standard functions at three levels of complexity: easy, moderate and difficult.

We will present the Go Configure Design Challenge Series on efabless in five pairs of two challenges each, beginning on October 2[SUP]nd[/SUP] and continuing until mid-December. Each Challenge will be open for two weeks. We will offer prizes like smartwatches and Bluetooth speakers for the highest quality designs for each separate challenge. Each separate challenge will also pay out Time-To-Market cash awards for the first three entries that meet a high, commercially acceptable, standard of quality – we recognize that successful community design requires both speed and quality. Finally, we will keep a running tabulation of scores across all challenges and present a grand prize to the overall challenge winner.

How do people register and compete?
MW: It all works very easily. Designers come to efabless and check out the “Go Configure Design Challenge Series” page. This will provide access to all the details on the Challenge Series as well as links to information on each separate challenge in the series. To participate, the designer registers on efabless and then reviews and selects a challenge or challenges. We also provide access to training videos authored by Silego engineers. We think participants will be pleased to see how easy it is to learn the GreenPAK development environment and become effective.

What happens after the Challenge? How can this new-found design talent be utilized?
MW: We are very excited about making Silego GreenPAKs available to our community as a key capability on the efabless platform. Community members will be able to create personal profiles that include their GreenPAK accomplishments and are searchable by customers and other community members. Potential customers will be able to search for GreenPAK talent or request designs. Community members will also be able to create their own unique designs and present them in a very protected way, with application notes and data sheets, in our marketplace.

We look forward to seeing community innovation on Silego GreenPAKs and encourage your readers to sign up and get started with the Go Configure Challenge.

October 1, 2017

Deal Struck for Sale of Toshiba NAND to Bain Apple and Others

Deal Struck for Sale of Toshiba NAND to Bain Apple and Others
by Robert Maire on 10-01-2017 at 12:00 pm
Categories: Semiconductor Advisors, Semiconductor Services

What does it mean for the skyrocketing memory sector? In a last minute plot twist, Bain capital appears to be the winner in the auction of the Toshiba memory unit. The Bain consortium includes a strange cast of characters including Apple, Dell, Seagate, Kingston Technology, Innovation Network Corp of Japan and Development Bank of Japan.
Continue reading “Deal Struck for Sale of Toshiba NAND to Bain Apple and Others”

October 1, 2017

2017 Semiconductor Growth Approaching 20 Percent!

2017 Semiconductor Growth Approaching 20 Percent!
by Bill Jewell on 10-01-2017 at 7:00 am
Categories: Semiconductor Intelligence, Semiconductor Services

The 2017 semiconductor market is shaping up as the strongest since 2010 – when the market grew 32% as it bounced back from the 2008-2009 downturn. According to World Semiconductor Trades Statistics (WSTS), the second quarter 2017 semiconductor market was up 5.8% from 1Q 2017 and up 23.7% from a year ago. Much of the market vitality is due to memory – specifically DRAM and NAND flash. This is illustrated by quarter-to-quarter revenue change of the major memory companies. Samsung revenues (in Korean won) were up 12.3% in 2Q17 versus 1Q17. Micron Technology revenues were up 19.8%. SK Hynix revenues (in Korean won) were up 6.4% in 2Q17, following 17.4% growth in 1Q17. Company guidance for 3Q17 shows continued strength in memory. Micron guided for 6.0% growth in 3Q17, with high-end guidance of 9.9%. Samsung and SK Hynix did not provide 3Q17 guidance, but both companies expect continued strong demand for DRAM and NAND flash. Micron expects healthy memory demand to continue into 2018.

A good sign of the health of the overall semiconductor market is the 3Q17 outlook for non-memory companies. Most of the major non-memory companies expect 3Q17 revenue to increase in the range of 5.6% to 9.0%. The exception is Infineon, which guided for 3Q17 revenue to be about the same as 2Q17. The high end of guidance from the non-memory companies shows the potential for close to double-digit growth. Excluding Infineon, the high end guidance ranges from 9.1% from Broadcom to 15.4% from Qualcomm.

Recent forecasts for the semiconductor market reflect this strength. WSTS’s June projection was 11.5% growth in 2017. In August, WSTS revised its forecast based on final 2Q 2017 data to 17.0%. Other recent forecasts range from 16% (for the IC market) from IC Insights to our Semiconductor Intelligence updated projection of 18.5%.

The available forecasts for 2018 generally call for a significant slowdown in the semiconductor market. WSTS expects 4.3% change and Mike Cowan’s latest projection is for 3.2% change. Our updated outlook at Semiconductor Intelligence is 10.0% growth in 2018. Our higher number is based on several key assumptions:

1. No crash in the memory market. The current boom in the DRAM and NAND flash markets is largely driven by increasing prices. This is not sustainable. Eventually supply and demand will move toward a balance – through an increase in supply as more capacity is added; through a decrease in demand as end equipment markets slow; or through a combination of the two. The memory market has seen major downturns in the past when demand from end equipment makers has declined significantly. As demand fell off, memory companies cut prices in an effort to keep fabs running. We do not expect any falloff in demand in 2018. The DRAM and NAND flash markets should experience a moderate correction, but not a significant decline.

2. Strong quarterly pattern set in 2017. The semiconductor market grew 5.8% in 2Q17 and should experience similar or stronger growth in 3Q17. Thus even moderate quarter-to-quarter growth in 2018 can lead to an annual increase close to double digits.

3. Continued electronic equipment growth. The major drivers of semiconductor demand have been PCs, tablets and mobile phones. Although these markets have been sluggish in the last few years, Gartner expects 2018 to improve over 2017. Automotive is becoming a significant market for semiconductors. Gartner projects growth in this market will pick up from 6% in 2017 to 7% in 2018. Semiconductors for Internet of Things (IoT) applications is an emerging market. IC Insights forecasts healthy IoT SC growth of 16% in 2017 and 15% in 2018. The global economy should see a slight pickup from 3.5% growth in 2017 to 3.6% in 2018, according to the International Monetary Fund (IMF).

September 29, 2017August 22, 2024

GLOBALFOUNDRIES is Hitting on all Cylinders

GLOBALFOUNDRIES is Hitting on all Cylinders
by Scotten Jones on 09-29-2017 at 2:00 pm
Categories: FD-SOI, FinFET, GlobalFoundries, Semiconductor

On September 20th GLOBALFOUNDRIES (GF) held their annual technology conference. The conference presented an opportunity to hear the latest on the fascinating journey GF has been on.
Continue reading “GLOBALFOUNDRIES is Hitting on all Cylinders”

September 29, 2017April 14, 2025

What’s New with the I3C Standard

What’s New with the I3C Standard
by Daniel Payne on 09-29-2017 at 12:00 pm
Categories: Automotive, IoT, Mobile

This month we’ve seen both Apple and Samsung announce their newest, flagship smart phones, and they each have an incredible number of sensors and components included like: Continue reading “What’s New with the I3C Standard”

September 29, 2017June 14, 2019

Design for Manufacturability Analysis for PCB’s

Design for Manufacturability Analysis for PCB’s
by Tom Dillinger on 09-29-2017 at 7:00 am
Categories: Cadence, EDA

Chip designers are familiar with the additional physical design checking requirements that were incorporated into flows at advanced process nodes. With the introduction of optical correction and inverse lithography technology applied during mask data generation, and with the extension of a 193nm exposure source to finer resolution dimensions, the traditional design rule checking (DRC) step was augmented with EDA tools that analyzed layout data to assess the fidelity of the final wafer-level structures to the original design. These algorithms were incorporated into checking tools described as providing Design for Manufacturability (DFM) support. (Parenthetically, EDA tools have also been developed to actively modify layout design data to reduce the “critical areas” that could contribute to yield loss, known as Design for Yield (DFY) modifications.)

DFM analysis has become increasingly important in the printed circuit board (PCB) design domain, as well. The scope of DFM analysis is significantly different for PCB design than chip design — PCB manufacture involves both bare board fabrication/test and subsequent component assembly. As a result, the DFM analysis for PCB design is an intricate interaction between Design for Fabrication (DFF) and Design for Assembly (DFA) requirements.

Examples of DFM checks for PCB design are illustrated below. The first depicts an “acid etch trap”, an area that may retain etchant longer than intended, resulting in open connections. The second figure highlights a design “sliver”, which is susceptible to detaching during the overall assembly flow, with the possibility of re-depositing and shorting distinct connections. Other examples include a trace routed through a solder mask opening created for a test point, or an analysis of the board stack-up thickness to via size aspect ratio to evaluate the drilling requirements and costs. These layout topologies are DRC clean, but represent additional risks during volume PCB manufacturing.

I recently had the opportunity to chat with Hemant Shah, Product Management Group Director for the Allegro PCB products at Cadence, about the expanding role of DFM for PCB design. Hemant impressed upon me the unique nature of this checking flow, as compared to IC design:

PCB project development schedules are extremely aggressive

As a result, DFM analysis for PCB design needs to be an integral part of the design environment, with interactive results available for review.

DFM analysis for PCBs requires access to the full board stack-up, layout, and component database.

Traditionally, multiple file formats have been used to represent the fabrication and assembly release data — e.g., Gerber drawings, CNC drill instructions, test specifications. The suite of DFM checks requires visibility into all PCB data, again necessitating integration with the design platform. (Hemant noted that the emerging IPC 2581 standard will be the comprehensive PCB release-to-manufacturing format for final analysis — please refer to www.IPC2581.com for more info.)

PCB assembly introduces unique DFM analysis checks, beyond the IC realm.

The PCB Bill of Materials (BoM) is represented by a component library database, reflecting the schematic symbol, pad footprint, logical-to-physical correspondence, and 3D dimensional models. This library data is fundamental to DFA checking. For example, the automated optical inspection (AOI) head requires unobstructed visibility for (post-reflow) analysis of component placement/attach and detection of solder quality defects.

Hemant indicated that Cadence has addressed DFM analysis for PCBs with a new technology – the DesignTrue DFM – that is integrated into the Allegro Printed Circuit Design platform to provide real-time in-design DFM checks as the design is created.

“PCB layout designers routinely apply interactive DRC checking within Allegro. We have expanded that capability with DesignTrue DFM analysis, which incorporates over 2000 manufacturing rules. Layout designers can quickly get DFM results directly in Allegro, and evaluate them in the DRC Viewer.”, Hemant said.

Unlike the pass/fail nature of DRC rules, viewer support for DFM rules requires additional features. In addition to simply fixing DFM rule violations, layout designers can flag DFM results, assign a severity, and generate reports for broader review by the engineering team.

“How are these DFM rules developed, as part of design enablement?”, I asked.

Hemant replied, “The enablement team uses the familiar Allegro Constraints Manager interface to manage DFM rules. The rule values are commonly a combination of data from the PCB fabrication/OSAT and a customer-defined ruleset. Customers seeking multiple sourcing options may wish to establish their own encompassing rules. There is also the capability to define additional rules, beyond the 2000+ currently built into DesignTrue DFM.”

“Are DFM rules computationally expensive, especially for interactive checking?”, I inquired.

“There are seven different rule categories in DesignTrue DFM.”, Hemant indicated. Examples include: surface versus inner layer rules, rigid versus flex rules, stack-up and drill specifications, trace + via + soldermask + silkscreen rules,.

Hemant continued, “Layout designers can optimize their performance throughput by selecting specific checking tasks and/or restricting the analysis to specific regions.”

Design for Manufacturability analysis is no longer strictly part of the release handoff to the PCB fabricator, but has become a critical step in the PCB design phase. The interactive DRC checks in the PCB platform are expanding to include DFM checks, as well. The Cadence Allegro PCB DesignTrue DFM technology feature is indicative of this PCB design methodology trend — for more information on DesignTrue DFM, please follow this link.

-chipguy