SemiWiki – Page 520 – The Open Forum for Semiconductor Professionals

January 16, 2018July 3, 2021

A Golden Age for Semiconductor Growth at ISS 2018

A Golden Age for Semiconductor Growth at ISS 2018
by Daniel Nenni on 01-16-2018 at 4:00 pm
Categories: Events, Semiconductor Services
5 Comments

The SEMI Industry Strategy Symposium (ISS 2018) started today with session one on economic trends. Daniel Niles (Alpha One Capital Partners) started it off with “A Golden Age for Global Growth – Semiconductor revenues up over 20% y/y (The Good News is Also the Bad News)”. The good news of course is that semiconductors continue to play a critical role in commercial “quality of life” products and infrastructure (cloud) and defense products (HPC/AI). The bad news of course is that it may not last.

Daniel presented 41 slides covering a wide variety of economic indicators which point to a possible cooling down period. Daniel’s predictions for the short and long term were summarized in his ending slides:

Semiconductor Industry Near Term:

Semi revs tracking up +21% y/y for CY17 with units up 15% ex-discretes. This would be the best growth since 2010 when the world was still recovering from the financial crisis. But in 2010 PC units grew 14% (-2% in 2017), cellular phone units grew 32% (4% in 2017), and autos grew 14% (2% in 2017).
Y/Y growth of +23% in Nov; +22% in Oct and +20% in September with high of +25% in August
Ex-memory, IC sales were +7% Y/Y in September, down from +11% in August, +10% in July, & +15% in May.
C17E WFE spend of $45B (up 30% y/y) is growing even faster than semi revs. Excess supply in ’18/19?
How much Apple inventory, +128% y/y in Q3, will need to be burned in Q1 given revs were up only 12% y/y?
Cisco inventory up 44% y/y; HPQ up 29% y/y; (strategic memory buys) but Samsung Elec +41%; Hynix +23%
Auto not large end-market for memory: Volkswagen, Toyota & Ford inventories are up 9-18% y/y; revs 1-11%
Lead-times stretched out in the spring and have driven the build in inventories. Even if sell-through is strong during the holiday season, the March qtr is seasonally down in demand and inventory burn could be ugly.
Most semi companies: “content gains are driving the stronger demand, there is no double ordering or inventory buildup.” Unit shipments were 5% in 2016 but 15% in 2017 and does not make sense at a high level. We believe a semi correction is coming by early 2018. The only question is severity given the big disconnect between end-market unit growth, inventory on balance sheets and semiconductor unit growth.

Predictions for Semi Industry over the Long-Term:

Positives:

Cloud Computing still has a long way to go with even more data created in the future from driverless cars n Artificial Intelligence will require immense computing power to replicate the 100B neurons in one human brain n A computer beat a GO Master for the first time this past year n Augmented Reality market supercharged with the launch of the iPhone X & ~$10 of content per phone
3D sensing will be one of the fastest semi growth markets with penetration of 1.5B phones per year n Fully autonomous cars expected by 2020/2021 will require an immense increase in semiconductor content n Nearly 1.3 million people die in road crashes worldwide every year
UK & France prohibit production of diesel and petrol cars by 2040- China looking at timeline for similar action
Volkswagen to invest €20B for electric versions of all models by 2030
Industrial robot market $12B in 2016 to nearly $35B by 2025. Robots should be taxed according to Bill Gates
5B connected devices in 2015 w/ ~20% growth through 2020.1T cumulative IoT devices shipped by 2035. n Voice and camera as the control input for computing/phones requires a large increase in computing power
Smartphone growth should continue at GDP plus as onramp of choice to the internet
PC growth likely to be GDP minus for many years as the smartphone continues as device of choice
Potential Risks:
China is a blessing/curse with 70% IC self sufficiency goal by 2025. Japan in 80s, Korea/Taiwan in the 1990s
Semiconductor debt levels have increased post mergers and interest rates are probably headed higher
Semiconductor mergers are slowing so investments will be needed to drive future earnings growth
A $500B trade deficit is a lot to fix even for a $18 trillion economy & border taxes will be disruptive

The full presentations are online for attendees and SEMI members. There is a LOT of information here and I’m a big fan of Daniel Niles so if you want to discuss this in more detail let me know in the comments section or on SemiWiki.com private email. Personally however, I see no barriers to double digit semiconductor growth for 2018 and am very optimistic in regards to the continued success of the fabless semiconductor ecosystem, absolutely.

January 16, 2018January 10, 2020

Scoreboard and Issues Management Tools for PCB Projects

Scoreboard and Issues Management Tools for PCB Projects
by Tom Dillinger on 01-16-2018 at 12:00 pm
Categories: Cadence, EDA

The complexity of an SoC design necessitates that the project managers have accurate visibility into the overall design status, spanning the entire range of tasks – from functional simulation error triage, to physical layout verification errors, to electrical analysis results. Flow scripts used by SoC teams parse the log file data generated by the underlying EDA tools invoked, to capture the status of each design block. These output results are stored in a database, from which a project scoreboard application pulls information for a view into the complete project snapshot (and history).

Given the variety of flows and the disparate nature of EDA vendor tool log file data for each flow, scoreboard development (and maintenance) for an SoC project requires significant CAD team resources. The scoreboard application includes detailed design revision and methodology dependency checking, as well – as project version updates are applied to ongoing design releases, the scoreboard database needs to ensure flows are re-executed and old results invalidated. The CAD and methodology teams collaborate to capture the flow dependency criteria. In return for the CAD team resource investment, the scoreboard information is extremely valuable, as it provides insights into SoC project schedule milestone risks and areas where design engineering resource re-balancing may be needed.

Another key SoC application is issues management, often simply referred to as the bug tracking tool. The issues application utilizes another database, with a rich and diverse set of information to be stored and queried – e.g., text, graphics, issue priority, issue owner, reviewers, approvals required to close, date opened, target close date, design block(s) impacted, related specifications, model build configuration (with all version tags), etc. This information evolves over time, as the investigation of the issue results in comments, proposals, dependencies on other issues, and a resolution recommendation that will need to be reviewed/approved/implemented/verified.

Both commercial and open-source issues management applications are available, and have been adopted by SoC teams. Often, a tool developed for software defect management will be adapted by the CAD team for the specific requirements of an SoC design.

Scoreboard and issues tracking tools are a fundamental aspect of any SoC design project management activity. PCB design projects have comparable tracking requirements, and some unique characteristics. The PCB project involves a broad cross-section of teams involved in design reviews – especially, component qualification engineering and component procurement. And, there is typically not a great deal of CAD resource available to develop and maintain scoreboard and issues applications for the PCB team. (Fortunately, there is less diversity in the EDA tool platform(s) used to capture, design, verify, and release the PCB data for manufacture.)

I recently had the opportunity to chat with Mark Hepburn, Product Management Director, System/Package/Board, in the Custom IC & PCB Group at Cadence, about project management tools for PCB designs. Mark highlighted, “We recognized the need for a broad set of users to obtain project metrics and analytics from the Allegro PCB platform. The users may not be actively working with Allegro, such as the project manager of a PCB design, or the Supply Chain Management organization overseeing multiple designs. We recently introduced Allegro Pulse, an enterprise-grade server database environment, with web portal views into different project tracking applications.”

Mark shared a few screen shots from Allegro Pulse, for examples of the analytic data available. The figure below illustrates the Bill-of-Materials parts management view, which provides the supply chain group early visibility into the project BoM, with comparisons to preferred parts list libraries.

The screen shot below provides an example of a PCB project scoreboard view. (The full scoreboard web portal page is customizable.) The view may include metrics built-in to Pulse and custom metrics defined by users. The built-in metrics include the status of Allegro PCB checking tools – e.g., component placement and connectivity checking, electrical rules checks. The scoreboard view may also incorporate detailed analytics – e.g., pin complexity calculations.

The figure below illustrates the issues management application in Pulse, directly accessible by users from an Allegro toolbar pull down menu. The issues app includes features for database search, e-mail list notification, and a summary rollup into the scoreboard.

A general project management application is also provided in Pulse – the status of project tasks, schedule, progress toward schedule milestones, etc., is coordinated with the other apps.

The complexity of current PCB designs requires comparable project management tool support that SoC designs have employed. Allegro Pulse addresses that need with a suite of integrated, customizable PM applications.

For more information on Allegro Pulse, here are two links that may be of interest – the first link is the general product landing page (with a video), while the second link is an overview product description (.pdf file).

-chipguy

January 16, 2018

Better than CNN

Better than CNN
by Bernard Murphy on 01-16-2018 at 7:00 am
Categories: AI
2 Comments

No, not the news network though I confess I am curious to see how many initial hits that title attracts. Then I clarify that I’m talking about convolutional neural nets, and my would-be social media fame evaporates. Oh well – for those few of you still with me, CNNs in all their many forms are the technology behind image, voice and other types of recognition. Taking an image as an example, a pixel array of that image is passed through a series of layers of neuron-like computations – convolution, activation, pooling (the details vary), potentially many layers – to produce an output. Initially the system is trained using labeled images (this is a robot, in this case) through an iterative process across many examples, this unlikely structure adjusts to being able to recognize in any image the thing for which it was trained.

CNNs are so amazingly effective that they have become true media stars, at least under the general heading of AI, able to recognize dogs, tumors, pedestrians in front of cars and many more high-value (and not so high-value) tricks. They’re even better than us mere humans. Which makes you wonder if CNNs are pretty much the last word in recognition, give or take a little polishing. Happily no, at least for those of us always craving the next big thing. CNNs are great, but they have their flaws.

In fact trained CNNs can be surprisingly brittle. Hacking images for misidentification has become a sport. This seems to be remarkably easy, sometimes requiring changes to only a few pixels. After a spectacularly inept and un-gamed blunder, Google acknowledged that “We still don’t know in a very concrete way what these machine learning models are learning,”.

It’s fun to speculate on the mystery of how these systems are already becoming so deep and capable that we can no longer understand how they work, but that lack of understanding is a problem when they don’t work correctly. Even within the bounds of what they can do, while CNNs are good at translational invariance (doesn’t matter if the cat is on the left or the right of the image), they’re not so good at aspect / rotational invariance (cat turned to the left or the right or standing on its head), unless in the training you include many more labeled examples covering these variants. Which doesn’t sound very intelligent; we mere humans don’t need to see objects from every possible aspect to be able to generalize.

Geoffrey Hinton (U Toronto and Google and a towering figure in neural nets) has been concerned for a long time about weaknesses in the CNN approach and thinks a different method is needed, still using neural nets but in a quite different way. He argues that the way we render computer graphics is a clue. We start with a hierarchical representation of the data, small pieces which are placed and oriented relative to other nearby pieces, forming together larger pieces, which are placed and oriented relative to other large pieces, and so on. He believes that our brains effectively do the inverse of this. We recognize small pieces along with their placement and orientation relative to other small pieces, recursively up through the hierarchy. He calls these sub-components capsules.

You might argue that this is just what CNNs do, recognizing edges, which are then composed into larger features, again recursively through the network. But there are a few important differences as I understand this. CNNs use pooling to simplify regions of an image, sending forward only the strongest signal per pool. Hinton thinks this is a major weakness; the strongest signal from a pool may not be the most relevant signal (at any given layer) if you’re not yet sure what you are going to recognize. Moreover, pooling weakens spatial and aspect relationships between parts of the image.

Additionally, CNNs have only a 2D understanding of images. Capsules build rotation + translation pose matrices for what they are seeing (remember again 3D graphics rendering). This becomes important in recognition in subsequent capsules. Recognition depends on relative poses between capsules; some will correlate with certain trained objects, others will have no correlation. Capsule-based networks consequently need little training on aspects/poses.

Another difference between the CNN approach and the capsule approach is how information is propagated forward. In a CNN, connections between layers are effectively hard-wired. Each element (neuron) in a layer can only communicate with a limited set of elements in the next layer, since being able to connect to all would be massively costly (in much smaller final layers, full connectivity is allowed). In capsule-based networks routing is dynamic, a capsule will send its output to whichever capsule most strongly ‘agrees’ with it; in effect capsules build a voting consensus on what they are seeing, which it appears gives CapNets a huge advantage in accuracy. They can learn on training sets of hundreds of examples rather than tens of thousands of examples.

At least that’s the theory. CapNets are already beating CNNs in recognizing hand-written digits but I haven’t seen coverage of application to more complex image recognition (yeah, not exactly stressing the 3D strength yet). And CapNets are currently quite slow. But they do run on the same hardware, in the same frameworks in which CNNs are trained (see some of the links below). No need to worry that your investment in special hardware or learning TensorFlow will be obsolete any time soon. But you might want to start brushing up on this domain for when they do start moving into production.

Here is a nice summary of the evolution of CNNs and what capsule networks bring to the part. This is taken from this YouTube video. Also another not quite complete explanation.

January 15, 2018November 22, 2019

Moving from FPGA’s to Embedded FPGA Fabric – How it’s Done

Moving from FPGA’s to Embedded FPGA Fabric – How it’s Done
by Tom Simon on 01-15-2018 at 12:00 pm
Categories: Achronix, eFPGA, FPGA, IP

Buying IP is just a little bit more complicated than buying a pair of shoes. A lot of IP is configurable and requires attention to various design and configuration parameters. We live in an age where commercial soft IP is used pretty often in designs, so people have developed increasing comfort in the process that is required to achieve integration. Hard IP definitely takes it up a level – there are more process specific details that require attention. Nevertheless, it seems that commercial hard IP has become viable and is being used frequently as well. So, the industry is making both hard and soft commercial IP work. But there is a new twist in the IP market, embeddable field programmable gate arrays, or eFPGA as Achronix likes to call their offering.

There are huge and easily grasped advantages to embedding FPGA fabrics inside of SOC’s. Off chip communication is costly from a power, BOM and throughput perspective. Bringing a system’s FPGA onto the SOC is a big win, and though it requires some extra thought, it seems the business and technical model that Achronix uses to onboard customers is well thought out and highly effective. Achronix has put together a white paper explaining the process for evaluating and implementing their embeddable FPGA fabric for use in SOC’s.

In many ways, embedding an FPGA fabric is a lot like embedding a processor, so the evaluation has to look at the target RTL for the FPGA and the resources it will optimally utilize. The elegant part of this is, of course, that the FPGA core can be precisely configured to meet the power, performance and area requirements of the final system. The Achronix white paper goes through this step by step. The first step is a technical discussion with the customer regarding requirements. This is usually done after an NDA so the appropriate level of technical detail can be covered.

The customer can also download the ACE design tools that are optimized for the Achronix eFPGA target. It includes an Achronix-optimized version of Synopsys Synplify Pro that fully supports Achronix Speedcore. The ACE toolkit can provide area, power timing and resource utilization information. It also supports debug and static timing analysis for both functional and timing-annotated simulation.

Achronix supplies two preconfigured Speedcore eFPGA instances for use as targets to help customers understand utilization and optimization. Customers can take their RTL and synthesize it with the ACE toolkit and then evaluate the results to determine what the optimal configuration would be for their customized instance. Of course, there will probably be some changes required to adapt from an existing discrete FPGA architecture to the Speedcore eFPGA. Achronix offers LRAM in addition to BRAM. This LRAM comes as a 4,096 bit configuration that is 128 x 32 and is suitable for buffering tasks. Another difference is that Speedcore uses a 4 input LUT, rather than the more common 6 input LUT in other architectures. Achronix has found that empirical data shows this is more efficient for a majority of programmable logic applications.

There is more information in their white paper about how Achronix works with their customers to evaluate the use of embeddable Speedcore eFPGA in their designs. Because Achronix has enjoyed increasing success with their discrete Speedster 22i FPGA, the evaluation and development steps are well understood, and they have ample experience to make the entire process go smoothly. Achronix also seems to place proper significance on technical dialog with their customers to ensure silicon and design success. The full white paper is available for reading on their website. It’s good to see, despite the additional complexity, that SOC designers who want to take advantage of the benefits of embedded FPGA fabric can fully understand the considerations and benefits before committing.

January 15, 2018July 3, 2021

Broadcom Versus Qualcomm Update

Broadcom Versus Qualcomm Update
by Daniel Nenni on 01-15-2018 at 7:00 am
Categories: Foundries
12 Comments

The Broadcom acquiring Qualcomm drama is still dominating the fabless semiconductor back channel. This week I will be at the SEMI ISS Conference with Scott Jones and several hundred high level semiconductor professionals so it will be interesting to hear the hallway chatter. When it was first announced I was in the minority in thinking it will happen and be for the greater good of the semiconductor industry. Now I would say popular opinion is in my favor based on the SemiWiki Poll where more than 10,000 people voted 58-42% in support and the dozens of people I have spoken privately to inside and outside (Wall Street) the ecosystem.

For me this story started at the TSMC 30[SUP]th[/SUP] Anniversary celebration in Taipei last October. The keynotes were by Nvidia CEO Jensen Huang, Qualcomm CEO Steve Mollenkopf, ADI CEO Vincent Roche, ARM CEO Simon Segars, Broadcom CEO Hock Tan, ASML CEO Peter Wennink, and Apple COO Jeff Williams. Next was a panel discussion led by Chairman Morris Chang (you can see the full video HERE). My takeaway from the event is that Apple, TSMC, and Broadcom are very close partners while Steve Mallenkopf and Qualcomm are on the outside looking in.

Next I see a picture of Hock Tan in the Oval Office with Donald Trump saying, “We are making America home again” after moving the Broadcom HQ back to the United States. Shortly thereafter Broadcom announces a $70 per share acquisition bid for Qualcomm. Qualcomm then issued the standard negative response that was déjà vu of the Avago bid for Broadcom which ended in a record $37B acquisition in 2015. Most financial people I spoke with disagree that $70 (a 33% premium) is not a fair bid but we all know it can and will go higher.

Then Hock goes after the QCOM board by nominating new board members to be voted on in March. QCOM rejected them of course but it really is up to the investors and Hock is speaking to them directly. My guess is that Hock will up the bid before the board meeting by at least $10 per share.

After being part of the fabless semiconductor industry for 30+ years I am seeing a trend that is in full support of the Hock Tan acquisition strategy. Non-traditional chip companies are beginning to dominate some very large market segments. Apple started it all which is documented in our book “Mobile Unleashed” chapter 8. Now the top three smartphone companies (Samsung, Apple, and Huawei) are packing their phones with custom silicon and more are sure to follow.

Tesla is another example of the fabless disruption. The Tesla domain came to SemiWiki in 2016 and now we have an onslaught of automotive content attracting the top car maker domains around the world. The SemiWiki IoT and Artificial Intelligence traffic is also dominated by non-traditional chip makers so the trend continues.

So where does this leave old school fabless semiconductor companies who now compete with their former customers? Can they really compete with rich systems companies on a comparatively low margin fabless chip budget?

Sometimes I post things on SemiWiki just to see the analytics. The Broadcom poll for example. I recently posted notices in the SemiWiki jobs forum for both Broadcom and Qualcomm to gauge the level of interest. Thus far it is running at 2:1 in favor of Broadcom. It is early but it is still an interesting data point to consider.

The one thing I have learned about Hock Tan over the years is that he is a very smart and determined man and I will never bet against him. Hock definitely runs a tight ship but look the investor value he has created over the years with AVGO and compare that to QCOM. I would argue that Hock’s management style is just what the semiconductor doctor ordered and combining Qualcomm and Broadcom (while keeping the Qualcomm name) and creating the third largest semiconductor company (Samsung and Intel are first and second) would in fact be for the greater good, absolutely.

January 12, 2018

Mentor Investigates Using Neural Networks for CMP Modeling

Mentor Investigates Using Neural Networks for CMP Modeling
by Mitch Heins on 01-12-2018 at 12:00 pm
Categories: EDA, Siemens EDA

I recently read a new white paper release by Mentor, a Siemens Business, that delved into the intricacies of Chemical Mechanical Polishing (CMP) and I got a sense of Déjà vu. My professional career in the IC industry started at Texas instruments and the white paper made me think of a conversation I had with one of my colleagues over lunch. We were experiencing some yield issues and he told a story of getting home late and trying to explain to his spouse the problems we were encountering. We often take for granted the miracle that the manufacturing of ICs is, and my friend’s wife brought that fact into perspective when she quipped, “Forget about yield, you should be happy any of them work at all!”.

One of the true innovations that helped make the IC industry what it is, has been the use CMP. CMP is responsible for the “leveling” of the wafer layers that makes for a good planar process. The CMP process is fascinating as it’s roughly akin to running a disc sander with a chemical slurry over the wafer to “polish” it smooth. This polishing is highly dependent upon the materials being polished and the density and shapes of the materials in any given location of the chip. To get consistent (and therefore flat) polishing, it’s important to maintain a constant density balance across the chip to prevent bumps and dishing that can cause shorts and opens.

With the introduction of softer copper interconnect at the 130nm node (vs harder aluminum), and then the introduction of high-k metal-gate technologies with costlier lithographic patterning schemes, it has become increasingly important to have higher accuracy CMP models that can be used to identify possible design “CMP hot-spots” before going to manufacturing. As mentioned, Mentor recently released a new white paper with a novel approach that uses machine learning and neural networks to accelerate the generation of good post-deposition (pre-CMP) profiles to be used with CMP manufacturing simulation models.

The main concept for building a CMP model is to extract geometric pattern properties of the chip layout, generate a pre-CMP surface profile after numerous etch and deposition steps and then use that data to simulate the post-CMP surface profile for different patterns on the layout. For high-quality modeling, it’s important to have a set of models corresponding to the deposition processes used by manufacturers to generate the correct input profile for CMP equipment simulations.

Generation of a high-quality pre-CMP surface profile is crucial for accurate CMP modeling and is complicated due to the convolving of geometric data, different materials and both short and long-range effects. Building physics-based models for different types of depositions processes such as high-density plasma CVD (HDP-CVD) and spin-on dielectric (SOD), is challenging and isn’t practical for more exotic deposition flows such as flowable CVD (FCVD) and enhanced high-aspect-ratio processes (eHARP). The key here is that if the pre-CMP profile isn’t accurate then neither will be the results of the CMP simulations for the post-CMP profile.

To attack this problem, researchers at Mentor recently had the idea of using machine learning (ML) algorithms to do a sensitivity analysis of measurement data on post-deposition (pre-CMP) surface profiles and found that the profile dependency was primarily influenced by the underlying pattern geometries while long-range effects look to be more secondary. Armed with this information they proposed the idea of using neural network (NN) regression calculations to model the pre-CMP surface profile using as input the geometric characteristics of the underlying patterns. The output of the NN would be the estimate of the pre-CMP profile that would then be used as input for the CMP equipment modeling.

Mentor already has algorithms to extract local geometric pattern characteristics from their Calibre CMP ModelBuilder and Calibre CMPAnalyzer products. They used these tools to extract pattern information such as width, space, pattern density and geometry perimeter and fed this into a multi-layer NN to generate post-deposition surface profile height data predictions. To test the practicality and accuracy of using ML and NNs to generate CMP models, Mentor took measured profile data from CMP test chips for four different deposition processes, HDP-CVD, SOD, FCVD and eHARP. Data was normalized and split into training and validation data sets and then used to train and validate NNs for each different process.

Mentor’s white paper goes into lots of details about the types of NNs used, the number of hidden layers in the NNs, numbers of neurons etc. All very interesting, but the best part was that the resulting models showed some very nice correlation, 95%, against the HDP-CVD and SOD processes for which compact models were already available in the Mentor Calibre CMP ModelBuilder tool. Mentor also applied this to modeling for the more complex FCVD and eHARP processes. Recall that these processes are too complicated for creating physics-based models with a reasonable runtime and accuracy. Using the NNs, they were again able to show good correlation with small errors per site. In summary, their approach looks to be a promising new way to build the post-deposition models for use by the CMP equipment simulators.

This is still early work and Mentor points out a few challenges of using NNs. One of them is that because the NN-based models are not physics-based, they can sometimes produce data that doesn’t physically make sense (e.g. small negative dishing as an example). They are hopeful that these issues can be handled either by some post-processing or more complete training data sets. None-the-less, this is quite promising work that could quickly become the norm for more advanced modeling in the future. One more level of complexity added to the miracle of manufacturing ICs!

January 12, 2018July 18, 2025

Achieving ISO 26262 Certification with ASIL Ready IP

Achieving ISO 26262 Certification with ASIL Ready IP
by Eric Esteve on 01-12-2018 at 7:00 am
Categories: Automotive, IP, Security, Synopsys

According with McKinsey, “analysts predict revenue growth for advanced driver assistance systems (ADAS) to be up to 29 percent, giving the segment one of the highest growth rates in the automotive and related industries.” Design cycle in automotive segment is much longer than in segments like mobile, PC or consumer. If you expect to see ADAS powered or autonomous cars in the street in 2025, you need to start designing now, in 2018. That’s why rapid progress in the development of advanced driver assistance systems (ADAS) and autonomous driving technology is challenging the semiconductor industry to bring the rigorous safety standards used in the automotive industry to its design process.

ADAS SoCs have to process increasing volumes of sensor data from many types of automotive sensors, driving the adoption of 64bit processing. Other trends in automotive semiconductor design include the use of:·Ethernet for managing large amounts of time-sensitive data traffic, and reducing point-to-point wiring

·LPDDR4/4x, with data rates of at least 3.2Gbit/s, for faster DRAM operations

·MIPI standards such MIPI Camera Serial Interface (CSI-2) and Display Serial Interface (DSI) for imaging and display applications

·PCI Express for high-reliability chip-to-chip connectivity for 4G radios, future 5G radios, and external SSDs

·5G and IEEE standards such as 802.11p for real-time updates of maps and images to and from the Cloud, and vehicle-to-vehicle or vehicle-to-infrastructure communications

·A shift from traditional 90nm, 65nm and 40nm processes to16nm, 14nm and even 7nm FinFET processes

The above listed features could apply to various type of applications, but for the automotive segment, electronic system, integrated circuits and intellectual property functions (or design IP) must comply with specific safety, quality and reliability requirements. A failure mode effect and diagnosis analysis (FMEDA) report is generated by development teams to provide all the information about their adherence to ISO 26262 from a functional safety perspective.

The ISO 26262 certification process must start from the very beginning of development process, and include multiple steps to complete the certification process, the Safety Plan.

Safety Planmanages and guide execution of safety activities. At first, the designer must define a strategy to achieve functional safety and define work packages. Key milestones will be specified and mapped to safety life cycle. The required resources will be identified and planned, as well as specific roles and personal assignments. Functional safety should be verified as well as compliance with standards and standard processes. Procedures, methods and tools have to be defined and mapped to various project phases.

FMEDAforms a critical part of the safety plan, providing a detailed report encompassing various steps and analysis, as shown in the above figure. It must include a fault injection analysis for both permanent and transient faults, so their impact can be assessed. FMEDA also considers all the possible failure and distribution modes to understand how the product will behave if a failure occurs and what sort of diagnostics the product implements to identify and communicate such failures to the system.

Now the impact of the designated safety features can be defined in the FMEDA report. Safety features fall into three categories:

Protection mechanisms, such as protecting the interface between the various components, such as IP, in the SoC architecture; parity protection on the data path and configuration registers; and ECC protection for both writes and reads.
Replication mechanisms, which include duplicating or triplicating key modules and using voting logic to ensure redundancy.
Various, which includes parity checks for all the state registers, single-cycle pulse validity, various dedicated interrupts, and hot-state machine protection for bad states.

In addition to meeting ISO 26262 functional safety requirements, automotive SoC development teams and the rest of the supply chain must adhere to automotive reliability and quality requirements.

Any product, including IP, for an automotive application must meet the automotive reliability requirements defined by AEC-Q100. IP providers must make sure their IP meets the reliability targets of the application, which means exploring how a transistor or electromigration analysis might be affected by the defined temperature profile. IP providers must work with foundries to ensure that any special automotive rules are applied to their design.

Any product development in the automotive supply chain must also meet automotive quality management requirements. In addition to having quality manuals and compliance reports, developers also need to create a design failure mode and effect analysis report that says that the SoC and its components meet the automotive quality management requirements.

You can find a brochure about Synopsys DesignWare IP for automotive and the original article “Achieving ISO 26262 Certification with ASIL Ready IP” from Ron DiGiuseppe on Synopsys web site.

By Eric Esteve from IPnest

January 11, 2018

Is there anything in VLSI layout other than “pushing polygons”? (5)

Is there anything in VLSI layout other than “pushing polygons”? (5)
by Dan Clein on 01-11-2018 at 12:00 pm
Categories: EDA, Siemens EDA
3 Comments

Being new in Ottawa and trying to get some momentum towards automation in full custom layout I was telling industry people that I am interested to work with everybody to move this agenda forward. My Director of Engineering at that time, Peter Gillingham, took me to visit Carleton University in Ottawa. One of his professor friends, Martin Lefebvre, had one PhD student building a silicon compiler for standard cells. Theoretically they knew “everything” but somebody from the “real world” was needed to say what make sense and what not, what is quality in layout (!) and what rules are important to follow. David Skoll, who was the architect, the implementation and the AE for it became an instant friend. It was very exiting to share my layout knowledge with him and continued to see over the years most of their roadmap and advanced alpha demos. Like any other beginning it was a bunch of scripts and some free tools from all over the map and David called it Machiavelli.

In the following years the name evolved into a full-size company that most of you will remember as Cadabra. In my opinion it was a very powerful idea and a solid implementation but had a limited usage. At that time ASIC flows started to pop-up from all over the map and every design house was buying or getting free libraries from fabs and ASIC vendors instead of developing themselves. They tried to implement a 2 level cells generation and process migration but with little success so the tool died a few years ago under Synopsys roof. What did I get from this? We learnt a lot about the power of “coins” or “basic bricks” and will Karl help MOSAID layout team had generated a lot of “basic” cells. From devices to via arrays, coding the decoders, etc. Later in PMC Sierra we had very advanced coins as part of our flow specifically enhanced for POWER connections and capacitors on power supplies.

One of the most time consuming and errors prone tasks for a Layout Designer is was (and still is) verifying DRC and LVS. MOSAID was using Dracula for verification but the preparation of data was tedious as the flat verification was not possible. As DRAM chips had a memory cell repeated, in our case 4-16 million times, we had to create “work structures”. To reduce the number of devices in a block we created doughnuts empty in the middle with only 1 cell on the boundary for interface checks. In top os size issues in DRAM we had 3 different sets of design rules, CORE, Memory and Periphery. Now we had to run verification on partial neighbouring. We also had to create schematics for each of these “working structures”. How many errors humans can introduce when ripping off full hierarchies to create this cells in layout and well as in schematic? Any 4M DRAM or above was taking about 1 week for one 1 DRC verification or LVS and 3-5 people in layout and circuit design. When all was clean any ECO will restart the creation and the full verification with many potential new errors.

We were very motivated to find a better solution. First, we evaluated the new Dracula (II) which was a 2 levels hierarchy verification versus Checkmate, the new advertised Mentor Graphics tool. About the same time Cadence started to talk about Vampire and ISS came with Hercules, advertised as the first hierarchical verification. I went to DAC in 1995 and had advance and private demos for each but I was not convinced that any has the “revolutionary” solution a memory needed. Most of their effort were toward ASIC which had at that time 1-3 levels of hierarchy but very few devices at any level as they used the standard cells as a stepping stone for hierarchy. Back from DAC we decided to bring Hercules for an evaluation but before doing that I called Mentor, as we had most of our platforms coming from them. We told them that unless they have something “cooking” worth waiting for, we will go for Hercules. Suddenly somebody wanted to talk to us and we got Michael McSherry, the technical marketing manager. Together with Gregg Shimokura, the coauthor of my book, we flew to Wilsonville, Oregon with our database on a tape.

After about a week of hiccups Gregg came back with great news, 1-hour LVS on a 16M DRAM. We had a clean data and a dirty one to be sure they actually find the same number of errors we found through our old Dracula flow. We started to see the light at the end of the tunnel. We agreed to work with them to make the tool ‘industry ready” and by 1996 was the official release. Mentor was so motivated to make this tool successful that they brought from China MingYong Yu, an experienced AE to learn everything we did and coordinate factory development. He was physically inside MOSAID for his first year in Canada. The biggest thing for a memory design was the reduction in the “potential errors” between our working structures as Calibre was the first real Hierarchical verification. In 1996 after a few successful tapeouts, I wrote a press release with Mentor about Calibre capabilities. For the following 2 years I personally helped Sundaram Natarajan, Mentor California sales guy, explaining customers why this solution is superior to all others offered at that time. Sundaram sold so much Calibre in these 2 years that he wanted to reward me somehow. I wanted the layout team to feel proud of their achievements so I convinced him to use this “reward” by subsidizing 220 t-shirts (one for each MOSAID employee) with the design attached in this article! Yes, another not “layout task” …

We solved the duration and errors issues but working with a new tool meant that the fabs, specifically the memory ones, did not have a Calibre PDK ready, we had to invent something else to make our life easier. We called it Process Independent Setup (PIS). We got from Germany a CAD expert, Britta Krueger, and together with the layout team prepared the specifications of this PIS. What we wanted first was the DRC. We built in layout all the possible design rules test cases in one chosen process and we wrote the code to verify them, obviously by different people. In parallel Britta and some helpers wrote all the Design Rules in a parameterized fashion in witch the numbers are actually parameters.

When a process comes in, one person takes the manual and inserts the values in the parameters page. When done just compiles the parameterized DECK and obtains the real values in Calibre command file. If a value is “0” this rule will not exist in the compile DECK. We knew that with this flow we can cover 80-85% of all design rules for any new process. We planned to add every time there are new design rules new test structures and their rules, in the original PDK and follow the flow. The intention was to reduce the new process setup from 100% new to 15% new. After a few months of work, we reduced any new process DECK generation from 3 weeks to 1 week when the processes were very different and to 1-day whey they were close. Then we started to enhance the PIS to get into LVS, Device generators, router setup, etc.

More about productivity enhancements next month!

Webinar: ISO 26262 and DO-254: Achieving Compliance to Both

Webinar: ISO 26262 and DO-254: Achieving Compliance to Both
by Bernard Murphy on 01-11-2018 at 7:00 am
Categories: Aldec, Automotive, EDA, FPGA

It’s near-impossible to read anything today about electronic design for cars without running into the ISO 26262 standard. If you design airborne electronic hardware, you’re likely very familiar with the DO-254 standard. But what do you do if you want to design a product to serve both markets? It looks like aircraft makers are increasingly turning to standard products, no doubt for reliability and cost, but they still need to hold those products to the DO-254 expectations they have embedded over many years. This presents both an opportunity and a challenge for chip and system designers – expanding demand but now required to comply with both standards.

Does this mean you have to run two separate compliance teams? Hopefully it isn’t that bad. Aldec have helpfully put together a webinar, hosted by an expert in these domains, to help understand where requirements are similar and where they differ between the standards. The speaker will wrap up with suggestions on how to effectively deliver compliance to both.

Abstract:
Increasingly, the DO-254 industry is turning to general purpose computing platforms to implement functionality with safety of life implications. This is creating opportunities for electronics to be developed that can be used to support both avionics and automotive applications. These two domains employ somewhat similar design assurance guidelines for electronic hardware found in ISO 26262 and DO-254. Each guideline addresses safety-requirements, design activities, verification and validation, and configuration management. In addition, specific attention is paid to proving the correctness of tool operations, as well as dealing with COTS.

This webinar will provide a high-level introduction to both ISO 26262 and DO-254 (along with the associated regulatory considerations). Guideline similarities and differences will be addressed when complying with the various life cycle activities and objectives. Data requirements of the two guidelines will be reviewed. The guidelines’ approaches to dealing with complexity, safety requirement verification, tools, and COTS, both components and intellectual property will be highlighted. The webinar will conclude with the speaker’s thoughts on how dual compliance can be achieved.

Agenda:

Quick Overview of the Automotive and Aviation Regulatory Domains
Structure and Overview of ISO 26262
Structure and Overview of DO-254
DO-254 Interpretation and Application (by FAA and EASA)
Similarities between ISO 26262 and DO-254
Differences between ISO 26262 and DO-254
Planning for Dual Compliance
Q&A

Presenter Bio:
Tom Ferrell is a software and airborne electronic hardware Designated Engineering Representative (DER) for the US Federal Aviation Administration. Tom is a co-founder of Ferrell and Associates Consulting, Inc. a certification and aviation safety consultancy. Previously, Tom has held senior technical positions at Science Application International Corporation (SAIC), Iridium LLC, and the Boeing Commercial Airplane Group. Tom holds a bachelor’s degree in Electrical Engineering from Northern Illinois University, a Master’s degree in Information Technology Management from Rensselaer PolyTechnic Institute, and a Master’s degree in History from George Mason University. Tom is one of the technical editors for the third edition of the Digital Avionics Handbook, published in 2014 by CRC Press.

January 10, 2018

Bicycles, Electronics and CES 2018

Bicycles, Electronics and CES 2018
by Daniel Payne on 01-10-2018 at 12:00 pm
Categories: EDA, Events, General
3 Comments

I’m an avid road bike enthusiast having just completed my 2017 goal of 13,000 miles, so follow me on Strava if you want to see the routes and photo adventures I have in Oregon. In the photo below I’m the guy in the middle with the Portland Velojersey on and we’re in a parking lot just 2 blocks away from Intel’s Ronler Acres site in Hillsboro.
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