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56th DAC – In Depth Look at Analog IP Migration from MunEDA

56th DAC – In Depth Look at Analog IP Migration from MunEDA
by Tom Simon on 07-31-2019 at 10:00 am
Categories: EDA, Events, MunEDA

Every year at DAC, in addition to the hubbub of the exhibit floor and the relatively short technical sessions, there are a number of tutorials that dive in depth into interesting topics. At the 56th DAC in Las Vegas this year, MunEDA offered an interesting tutorial on Analog IP migration and optimization. This is a key issue for large and small companies. Digital IP migration is a fairly well bounded problem, making digital IP reuse a common activity. Though no less important, analog IP has been more difficult to adapt to new processes and new foundries. The 4 hour MunEDA tutorial was rich with technical content and real life case studies from Fraunhofer, inPlay Technologies, Rohm and STMicroelectronics. As always it is way more interesting to hear about design tool experiences from customers.

Michael Pronath from MunEDA started off the tutorial by discussing tools and methodologies for analog IP migration. MunEDA addresses issues in full custom design, which includes memories, custom cells, RF, and of course, analog. There are many challenges in this domain, including difficult design trade-offs, and design for yield & aging. Their migration flow includes SPT, for schematic porting. It handles many of the tedious and error prone steps involved in moving a design. The ported schematic can then be sized and tuned for the new technology with MunEDA’s WiCkeD sizing and tuning tools. WiCkeD stands for their Worst Case Distance optimization and analysis techniques. The final step is applying the WiCkeD based analysis and verification tools to ensure proper operation and performance of the finished design. This can include accounting for processes parameters, global and mismatch variation, reliability and more.

I found the portion of the tutorial given by Rohm’s Hidekazu Kojima particularly interesting. Rohm is a company that has been innovating semiconductor products since the late 1950’s. Their IP group uses MunEDA products to tailor their IP to the individual product group needs. They rely heavily on MunEDA WiCkeD tools for this. Hidekazu compared the flow they use to a traditional optimization flow. The main problem he highlighted with other flows is that there can be many iterations, where each small change requires reverification of all the performance specifications. MunEDA’s WiCkeD Deterministc Nominal Optimizer (DNO) pretty much handles the whole process and only required a few automatic iterations to reach closure.

Hidekazu then talked about finding the worst-case operating condition and corner. The WiCkeD tools can detect a worst operating condition between a min and max range. He also mentioned the easy to understand output graphs produced by the tools. The next part of his presentation was discussion of several case studies, including an AMP circuit, memory circuit, a comparator, and a logic circuit. For the AMP circuit, the optimization time went from 160h to ~6h. The area was also reduced by 60% compared to the original circuit with improved operating characteristics.

He closed with an overview of what he felt were the most useful features. Naturally the schematic porting features were included. He said it made it easy to replace devices with the new ones from the target PDK. It also automates any necessary rewiring. The Worst Case Analysis (WCA) algorithm significantly reduced the number of simulations needed for high sigma verification. This is useful for designs intended for automotive applications. WCA was also very useful for helping improve robustness for process variation and mismatch, with higher accuracy in fewer simulations.  Lastly, they were easily able to produce corner models based on PCM data from typical models. They came to within 1% of their target in only ~15 minutes.

Over time companies develop an array of design IP, which comes to represent significant value. Having the ability easily and predictably migrate this IP means that this value can be effectively leveraged for future projects. MunEDA tools make this a reality. The tutorial was filled with a rich variety of applications for MunEDA WiCkeD tools. If you were not able to attend the tutorial, the comprehensive slides are available are available on the MunEDA website. I expect that, just as I did, you will find the contents very informative.

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IP Provider Vidatronic Embraces the ClioSoft Design Management Platform

IP Provider Vidatronic Embraces the ClioSoft Design Management Platform
by Randy Smith on 07-31-2019 at 6:00 am
Categories: Cliosoft, EDA
2 Comments

Having worked at several semiconductor intellectual property (SIP) companies, I know how important it is to have a strong design data management platform for tracking the development and distribution of SIP products. Everyone doing semiconductor design should care about design data management. But for an IP company, it is imperative. Life gets complex quickly when you start giving your customers different versions of the same IP. So, it got my attention when Vidatronic, a provider of energy-efficient analog and power management unit (PMU) IP, said they were willing to talk about their use of ClioSoft’s SOS Design Platform to develop their IPs.

First, a bit about Vidatronic. They have been around since 2010 and have a couple of interesting outside board members amongst some of the biggest names in semiconductors, including Hector Ruiz, Ph.D. (former CEO of AMD) and Mike Bartlett, M.S.E.E. (former Texas Instruments VP). Recently, Vidatronic announced that they will provide PMU and analog IP cores to ARM for use in their solutions and have also teamed up with Samsung Foundry to provide analog IP core designs for licensing through SAFE™, Samsung Advanced Foundry Ecosystem. They sport two primary engineering locations, one in Austin, Texas and one in Egypt. Their analog SoC IP portfolio includes power-management solutions including LDO linear voltage regulators, DC-DC switching converters, bandgap voltage references, and other support circuitry. They also provide radio-frequency solutions, including CMOS transmitters.

Based on this basic description of Vidatronic, we can see that they need to support many SIPs across a large number of design process nodes, where they also need to develop customized versions for certain customer/process node combinations. But when diving in deeper with Vidatronic, we find even stronger reasons to deploy ClioSoft’s SOS Design Platform:

  1. Reduced complexity and efficiency while supporting multiple sites
    1. Used in Texas and Egypt
    2. Supports real-time sharing of design data between the sites
    3. Performance needs for auto-synchronization and secure, efficient data transfer
    4. Easy to control/restrict design access
    5. Optimized disk usage using SOS smart caching (with links to cache work areas to optimize network storage)
    6. Read-only local copy work areas with exclusive or concurrent locking
  2. Support for Cadence Virtuoso platform
    1. Ability to manage complex hierarchical cell views
    2. Integrates well with Cadence Virtuoso
  3. Critical features for tracking multiple versions of each IP
    1. Easy to take and label design snapshots of the designs which helps in efficient collaboration between the teams
    2. “Revert back” feature for recovering to a stable version of the design data, if necessary
    3. Design teams can record important milestones, plus review and track open issues
    4. Use “visual design diff” to identify differences between two revisions of the schematic or layout of an IP

That is a lot of strong reasons for Vidatronic to utilize ClioSoft’s SOS Design Platform.

When I asked Moises Robinson, President and Co-Founder of Vidatronic about his company’s experience with ClioSoft, he told me “We selected ClioSoft’s SOS Design and IP Management Platform for our design needs about four years ago and we have been extremely happy with it ever since. The number one reason we chose ClioSoft was for its design collaboration features. Operating on a global scale is not without its challenges, but ClioSoft allows our engineers across the world to work seamlessly together on the same projects while maintaining tight control over revision histories so we never lose any of our work. Effective management of the different versions of our IP and efficient collaboration among our designers is integral to our success, and ClioSoft plays an important role in us ultimately delivering the highest quality IP to our customers.”

That is an impressive endorsement. Indeed, ClioSoft’s SOS Design Platform seems like a perfect tool for companies developing IPs over multiple sites worldwide.

Also Read

56thDAC ClioSoft Excitement

A Brief History of IP Management

Three things you should know about designHUB!

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Semicon West 2019 – Day 3 – Global Foundries

Semicon West 2019 – Day 3 – Global Foundries
by Scotten Jones on 07-30-2019 at 10:00 am
Categories: Events, Foundries, GlobalFoundries
3 Comments

On Wednesday, July 10th I got to sit down with Gary Patton, CTO and SVP of worldwide research and development of Global Foundries and get an update on how the company is doing.

We started with a discussion of Global Foundries (GF) general business health. Revenue for the year is expected to be around $6 billion dollars. They are focused on profitability and will generate over $600 million dollars in free cash flow after $700 million dollars of capital expenditure and $600 million dollars of R&D spending not including any transactions. In the past GF was cash flow negative and this is a huge accomplishment making the company self-funding.

The first key decision in achieving this was pivoting away from 7nm. 7nm is fine for TSMC and Samsung but is messy with EUV, etc. and the R&D and IP investments are very high. According to a graphic they showed me from Gartner, 7nm and smaller nodes are only expected to represent about 20% of the total available market in 2023 so GF is not missing out on a lot of opportunity.

A second key decision has been rationalizing their fabs. GF had 3 – 200mm fabs, with large fabs in Burlington and Singapore and a small fab doing MEMS (Singapore Fab 3E). They have now sold Fab 3E. They also had 4 – 300mm fabs with large fabs in Malta. Dresden and Singapore and a small fab in Fishkill. They have now sold the Fishkill fab to On Semiconductor. On’s product have a lot fewer masks than GF’s making Fishkill a more appropriate scale fab for them. Fishkill will transition to On over three years with 45RFSOI and Silicon Photonics transitioning to Malta and 130nm RFSOI going to Singapore, Dresden has 22FDX and 40nm RF SOI. Even after the fab sales GF still has plenty of space available for growth. Dresden is only about 50% full, Fab 7 in Singapore has some space and after moving out 7nm from Malta there is about 40% available space there. GF can grow revenue by 40% with current cleanroom space.

GF has also sold their ASIC business to Marvell making them a clean provider of foundry services. They are focusing on being a manufacturing service provider, not a product provider.

GF wants to focus on key market segments that are growing, mobile, automotive and IOT (smart devices). In mobile the BOM is switching to more FEM (Front End Module) where GF is strong (I have previously written about GF’s broad portfolio of RF solutions here) and they are the only foundry with turn-key RF.

Some examples of applications for GF technologies are shown in the following slides.

Figure 1 illustrates GF technologies in wireless base stations.

Figure 1. Wireless infrastructure applications.

Figure 2 illustrates GF technologies in smart phones.

Figure 2. Smartphone applications.

Figure 3 illustrates GF technologies in automotive.

Figure 3. Automotive applications.

22FDX will have double the design wins this year and GF has restarted work on 12FDX. 12FDX is being developed in Malta on a slow ramp, they aren’t being pressured by customers for 12FDX yet. They have two new $1 billion-dollar opportunities in the last year for 45RFSOI in Dresden. They think their embedded MRAM solution is more flexible than other suppliers and they have started to get design wins on MRAM and also mmWave.

After years of questions about GF’s long-term survival they appear to be carving out a sustainable position in some key markets.

 

 

 

 

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Mentor Highlights HLS Customer Use in Automotive Applications

Mentor Highlights HLS Customer Use in Automotive Applications
by Bernard Murphy on 07-30-2019 at 6:00 am
Categories: AI, Automotive, EDA, Siemens EDA

Catapult HLS

I’ve talked before about Mentor’s work in high-level synthesis (HLS) and machine learning (ML). An important advantage of HLS in these applications is its ability to very quickly adapt and optimize architecture and verify an implementation to an objective in a highly dynamic domain. Design for automotive applications – for example in an intelligent imaging pipeline such as you might find for object detection in a forward-facing sensor – present all of these challenges.

Evolving Demands in Automotive Design

Certainly they can be on very tight deadlines; one example mentioned below required a team to develop three designs in a year. But two other constraints are even more challenging. First, verification suites are naturally based on images, often at 4K resolution, with 8-12-bit color depth and 30 frames per second. On top of this ML inference testing suites using images of this complexity can be huge, since correct detection in these applications needs to be near-foolproof.

Finally, the ecosystem from SoC developer to module maker to auto OEM has become much more tightly coupled, especially to meet the tighter requirements of ISO26262 Part 2 and now also SOTIF (safety of the intended function, another emerging ISO standard). Part 2 and SOTIF demands have placed more burden on the value chain as a whole, from IP suppliers through SoC integrators to Tier1s and the automotive OEMs, to ensure that the final product can meet safety requirements. For example Part 2 now requires a confirmation review to “provide sufficient and convincing evidence … to the achievement of functional safety”. This is a matter of judgment, not just meeting metrics; a tier 1 or a chip maker can require additional support from lower levels to meet that objective, which means that design specs can continue to iterate until quite late in the design schedule.

Under these constraints RTL-based design flows would be impossibly challenging; there simply wouldn’t be enough time to experiment with enough architecture variations, verify over huge reference image databases and respond to and re-characterize and re-verify late-stage changes from Tier1s or OEMs.

This is where HLS shines. You can develop code in C/C++ and experiment with architectures at least an order of magnitude more efficiently than you can at RTL since these are algorithmic problems most easily represented in that format (or in MATLAB or the common ML frameworks, to which the Mentor HLS solutions can connect). You can also run verification of those giant datasets at this level, multiple orders of magnitude faster than RTL-based verification. (I believe this should even be faster than emulation since C-modeling is close to virtual prototyping which runs at near-real time performance.) And in response to late changes, you can incorporate those changes at the C-level and re-verify and re-synthesize pretty much hands-free, limiting impact on your schedule.

Case Studies

Mentor recently released a white-paper (see below) on outcomes for three of their customers using their Catapult flow for designs in the automotive imaging pipeline. Bosch, a well-known mobility Tier1, are finding it valuable to enhance their own differentiation by building their own IPs and ICs for image recognition. This was the example where a design team had to produce three designs in a year. Using the Mentor flow they were able to pull this off and deliver a 30% power reduction because they were could easily experiment with and refine the architecture for power. They also commented that it will be much easier to migrate the C-based model to new designs and evolving standards than it would have been with an RTL model.

Chips and Media, a company providing hardware IP for video codec, image processing and computer vision (CV), also used the Mentor flow to develop a new CV IP. This was their first time using the HLS flow and they ran an interesting experiment with two teams, one developing with HLS, the other with hand-coded Verilog. The Verilog team took 5 months to complete their work, with little experimentation on architecture, whereas the HLS took 2.5 months. This was from a cold-start – they had to train on the tools first, then develop the C code, synthesize and so on. Apparently they were also able to experiment quite a bit in this period.

Finally, ST are well-known for their image signal processing (ISP) products, commonly used in automotive sensors. They have seen comparable improvements in throughput for such designs, delivering (and this is pretty awe-inspiring) more than 50 different ISP designs in two years, ranging in size from 10K gates to 2 million gates. Try doing that with an RTL-based flow!

You can learn more about these user examples and more detail on the Catapult HLS flow HERE.

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Virtuoso Adapts to Address Cyber Physical Systems

Virtuoso Adapts to Address Cyber Physical Systems
by Tom Simon on 07-29-2019 at 2:00 pm
Categories: Automotive, Cadence, EDA

LIDAR is a controversial topic, with even Elon Musk weighing in on whether it will ever be feasible for use in self driving cars. His contention is that the sensors will remain too expensive and potentially be unreliable because of their mechanical complexity. However, each of the sensors available for autonomous driving have their strengths and weaknesses. LIDAR offers many of the advantages of camera based sensors, plus it can work in the dark. The other advantage it has over cameras is that it can provide object speed detection.

At DAC I had a chance to talk to Ian Dennison, Senior Group Director at Cadence about innovations occurring sensor technology and their integration into cyber physical systems. For instance, there are potential developments in LIDAR technology that could eliminate the need for mechanical elements, replacing them with a transmitter optical phase array. According to Ian a major roadblock for this kind of development was the difficulty combining optical and electronic design and analysis into a single integrated platform.

Beyond the elimination of mechanical elements, electro-optical design can help expand the application areas of a given technology.  It is well understood that LIDAR is not suitable for close range sensing. For automotive applications an accuracy 10 cm is fine. However, for industrial robotics this will not suffice. Ian believes that with more accurate laser modulation this resolution could be improved. One method could be adding additional electro-optical elements to create a PLL.

Cadence has been working hard on developing a photonics solution that extend design capabilities to solve problems that are holding back what Ian describes a gold rush in cost reductions for sensor systems. Cadence has established partnerships with Lumerical, Coventor and Mathworks to develop Virtuoso integrations that can accelerate design and integration of these systems.

Cadence has developed features and products to facilitate these integrations. An excellent example of this is their CurvyCore for creating curvilinear structures in Virtuoso. They have a SKILL API that allow symbolic curvilinear layout and discretization. It enables waveguide creation and model property calculation. Other useful tools can be added through SKILL IPC calls.

LIDAR is not the only application that is benefiting from Cadence’s enhanced Virtuoso solutions. In the RF space Cadence has announced Spectre X which offers up to a 10X speed improvement coupled with up to 5X capacity while maintaining Spectre’s golden accuracy. At high frequencies, such as 122 GHz, it is possible to include the antenna on the chip with the LNA and PA. Designs such as this need EM simulation for transmission like accuracy. Cadence has recently announced new EM solver solutions that can address all elements of a 122 GHz FMCW radar system.

From my conversation with Ian, it is pretty clear that Cadence is attacking the design issues in sensor design across the board. Indeed, there was a lot to digest. Nevertheless, as designers pick and use these new features, it is sure to change the landscape in autonomous vehicles, robotics, etc. While I am often a big fan of Elon Musk, I would not bet on LIDAR remaining unfeasible for automotive applications. History is full of examples of unforeseen advances due to improving technology. If anything, the rate of change is accelerating. A full description of the many developments in the Cadence solutions for sensor system development is available on their website.

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IP Lifecycle Management and Permissions

IP Lifecycle Management and Permissions
by Daniel Payne on 07-29-2019 at 10:00 am
Categories: EDA, Perforce

Percipient IPLM

My first professional experience with computers and file permissions was at Intel in the late 1970s, where we used big iron IBM mainframes located far away in another state, and each user could edit their own files along with browse shared files from co-workers in the same department. I saw this same file permission concept when using computers from DEC, Wang, Apollo, Sun, Solbourne, HP and others. Even my MacBook Pro computer has an OS based upon Mach OS, derived from BSD UNIX, so it’s very familiar to me when using the command line. SoC designers today are using Linux and UNIX-based computers either on their desktop, network, private cloud or public clouds, and they all have file permissions to help organize how teams share files while the IT group can administer policies.

For an IP-based SoC we need something to help us manage access and track usage of all of those IP blocks, thus the concept of IP Lifecycle Management (IPLM) tools arose and is served by enterprise solutions vendors like Methodics. Using an IPLM approach means that there is one, centralized repository for an SoC design, so that users can get a Bill of Materials (BOM) and know where each IP block is being used. Just like files have permission, each IP block has permissions with IPLM as a way to bring order and allow the IT group to assign roles like Read access or Write access to trusted engineers on a team.

An ideal IPLM system should be a single source of truth, managing IP, related databases, corporate PLMs, requirement managers and even bug trackers. It turns out that Methodics does have an IPLM tool called Percipient that aims to fulfill these ideals.  Let’s take a quick look at how the Percipient IPLM approach connects to low-level files, requirements manager, Data Management (DM) systems and PLM tools:

Percipient

Just like UNIX allows you to set individual file permission of Read, Write, Execute and Owner; with Percipient you can decide to assign Read, Write or Owner permissions to users or groups of users for each IP block within the company. In Unix you’ve already defined the concepts of Users and Groups, so that info can be re-used within Percipient to enable permissions for each IP block.

Percipient also has the concept of hierarchy, meaning that one IP block may itself contain one or many lower-level IP blocks, so you get to define the IP permissions per user and group. If your team has contractors, then it makes sense that you restrict their access to any sensitive IP block details. An admin using Percipient can also grant permissions to all IP hierarchy using a single command, so managing IP access can be quickly updated as your project dynamically changes.

IP permissions are set by knowing who is working on a project, and also which IPs are being used on a project. Engineers that are working on a project will be part of the same UNIX group, so Percipient synchs with your LDAP/AD system to know which engineers belong to each group. To add a new engineer to your project or remove an engineer just update their UNIX group.

Once Percipient knows each UNIX group that are being used, then you can define which IP  blocks are assigned as Read, Write or Ownership permission. The IP hierarchy permissions are also defined by an admin either all at once, or by hierarchy level. You define group membership using UNIX and it gets synced within Percipient, so it’s always up to date.

Each IP block with multiple users in different project hierarchies can have multiple permissions with different project groups, so it’s quite flexible to meet your unique project needs.

With Percipient there’s a convenient, centralized place to to view both project and file permissions. Percipient consistently applies permissions into the underlying DM system, whether that is a Perforce IP or another DM. Engineers only see and can modify the specific IP blocks that permission has been granted for.

IP blocks that are changed or re-used in different contexts have their file permissions always in-sync with the DM tool.

Permission management for bug tracking tools like Jira, or a Wiki manager such as Confluence can both be performed by Percipient, extending the utility of a centralized approach.

Let’s say that you wanted to find out the project BOM along with all permissions attached to each IP contained in the BOM. With the Percipient tool there’s a RESTful public API, and here’s an example using the command line, along with the output results:

Results of using the RESTful API

The results tell us that the users of group “proj_yosemite” have Read permission to the IP, and that user “sasha” has Read, Write and Owner permissions to the IP.  Using this API makes it straight-forward for CAD engineerings to integrate Percipient with other software tools that use permissions.

Summary

Both operating systems and IPLM systems have come a long way over the years, making the life of SoC engineers a bit easier by using automation to help manage hierarchy in IP blocks, along with synching up with DM, project requirements and bug tracking tools. Your BOM can now be maintained in a single tool, along with managing all of the permissions to each IP. For more details there’s a 10 page White Paper available at Methodics web site.

Related Blogs

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Real Men Have Fabs Jerry Sanders, TJ Rodgers, and AMD

Real Men Have Fabs Jerry Sanders, TJ Rodgers, and AMD
by John East on 07-29-2019 at 6:00 am
Categories: John East
7 Comments

In 1977 I made a job change:  I took a job at Raytheon Semiconductor.  Raytheon was on Ellis Street next door to the Fairchild “Rust Bucket”.  In the early days, they shared the same parking lot so my commute didn’t change much, but my outlook on life changed a bunch.  I had mostly enjoyed my days at Fairchild, but I hated every single day I spent at Raytheon.

Then, in 1979,  I got a break!  Gene Conner (a great boss and AMD’s first product engineer)  offered me a job as product manager of AMD’s Interface product line.  I jumped on it!!!  Wow.  It was like dying and going to heaven.  Within a few days Gene taught me the most important thing that you had to understand if you were going to be a manager at AMD.

People first.  Products and profits will follow.

Jerry Sanders was definitely a flamboyant guy. Some of the stories you may have heard are probably overstated,  but he was flamboyant!  He was also very sensitive to the needs and feelings of the people who worked there.  Jerry hated the idea of layoffs.  Layoffs are very different from firings.  Someone gets fired if they don’t do their job well.  It seems harsh, but sometimes that has to happen.  With layoffs,  though, people who are doing their job well get let go.  We all hate that.  Jerry particularly hated it. Layoffs were a common part of the Silicon Valley culture at the time (See my week #7.  Layoffs Ala Fairchild). Jerry didn’t want AMD to be like that.  He instituted a no-layoff policy at AMD.  At first it was an informal policy.  Later, he had it written in the company’s policy manual.  For 17 years he stuck to it.  If things weren’t going well temporarily, Jerry’s view was  – hold on to the people and let the earnings suffer.  Not the other way around. That was unheard of in Silicon Valley semiconductor companies.  It made people want to work at AMD. The great recession of 1984 came.  We dropped into a loss position.  Our spending was too high. Our sales too low.  The cash balance wasn’t strong.  At an executive staff meeting we were hashing out what we could do about it.  The subject of a layoff came up.  Several execs were pushing for a layoff.  Jerry went apoplectic. He banged on the table yelling,  “I’m not going to preside over the dismantling of my life’s work.”  Jerry was always a good “quote machine”,  but that one in particular will stick with me forever.

(Unfortunately, by the time 1986 rolled around we were still in a loss position and the cash balance was running dangerously low.  We were forced to abandon the policy.)

In 1980 we had a very good year. Jerry wanted to spread the wealth.  He decided to hold a raffle.  The winner of the raffle was to get a house!   Yes.  The title to a real house here in Silicon Valley! Even back in 1980, production workers generally couldn’t afford their own houses.  The raffle was held, as I recall, on a Saturday night.  Early Sunday morning Jerry, accompanied by a Channel 7 TV crew, went to the home of the winner (A Fab worker named Jocelyn Lleno who didn’t have any idea that she had won) and knocked on the door.  When she answered the door wearing her bathrobe,  he told her,  “Hi.  I’m Jerry Sanders.  I came here to tell you that you won the raffle.  You’ve won a house here in Silicon Valley.”  She was blown away!!!  (Actually, the prize was $1000/month for 25 years.  Hard to believe, but in those days that was enough to buy a very nice house)

Once at a black tie dinner event for AMD executives and their wives,  I was assigned to sit next to Jerry at dinner.  My wife Pam sat directly to his right.  Jerry knew that Pam owned a dance studio (she still does).  He asked her how the studio was going.  It happened that Pam was about to take a contingent of dancers to Russia, Poland, and the Ukraine for three weeks as part of an exchange program – a cadre of Russian dancers had just visited Silicon Valley.  It was expensive to take all those dancers to Russia and nobody had figured out how they were doing to pay for it.  So Pam  — extrovert that she is – responded with something like, “Well.  I’ve got a problem.  I don’t know how I’m going to pay for this Russian exchange.  Can you help?”  As I crawled out from under the table, I saw Jerry reach into his jacket pocket.  He pulled out a check book and wrote out a personal check for $1000.

I first met TJ Rodgers in 1982 when he worked at AMD.  Shortly after that,  he left AMD to found Cypress Semiconductor.  In 1992 plus or minus a year or two Valerie Rice, a writer for the San Jose Mercury News, was interviewing TJ.  The fabless concept hadn’t yet taken over the world,  but it was making inroads.  Valerie asked TJ what he thought about the fabless model.  I love TJ Rodgers!  He was one of the old guard CEOs (As I was).  He believed in Fabs,  device physics, and transistor level circuit design (Things have changed.  See my upcoming week #15.  The Decade that changed the industry.)  Valerie tried to help by summarizing what he had said.  “So, you’re essentially saying that real men have fabs,  right?”  That was a play on the title of a book that was very popular back in the day.  Real Men Don’t Eat Quiche.  TJ jumped on it.  “Exactly!!!”  Jerry Sanders read that line and loved it!  Later that year he was the lunch speaker at the Instat Conference (Jack Beedle’s annual semiconductor conference that was attended by virtually all the big brass in the business).  The high point of his talk?  In his very strongest “take charge of the room and lay down the law” style:  “Now hear me and hear me well.  Real Men Have Fabs!!!!”  Most of the speakers that afternoon were fabless company CEOs.  I was one of them.  Jerry’s talk sent us all scurrying back to our power points to make the necessary changes.  The Instat Conference was always fun, but that was the best one ever!!

There was something about the AMD environment that spawned CEOs.  Was it the collegial environment?  In total,  83 former AMDers have gone on to become CEOs of other tech companies.  The two who impress me the most, though, are two CEOs who were just starting their careers at AMD during the days when I was a VP there.  Jayshree Ullal and Jensen Huang.  Jayshree  (the CEO at Arista Networks)  took Arista from a fledgling company to one now valued at twenty billion dollars!  There’s a great article about her in Forbes Magazine.   Jensen (the CEO of Nvidea) has built a juggernaut, but I think of him as the best public speaker I have ever listened to.  (Actually – he’s tied with Jerry Sanders who is the greatest orator in the history of High Tech!!!).   At the typical dinner event, most of us can’t wait until the keynote speaker shuts up so that we can eat.  In the case of Jensen, though, you don’t want him to stop.  He’s just plain fun to listen to.

There was a terrific amount of camaraderie and love for the company in the early days of AMD.  A terrific spirit!  It seemed to me that it waned a bit, though, when Jerry left.  This May 8th I was invited to attend the AMD 50th birthday celebration in their new offices in Santa Clara.  It was a really well planned event.  I talked briefly with Lisa Su (The new CEO) and with a dozen or so of the present-day rank and file employees.  My takeaway?  Lisa Su is great and the spirit is back.

Jerry Sanders was CEO of AMD for 33 years.  TJ Rodgers was CEO of Cypress for 33 years.  The industry lost a lot when they retired!  I miss them!!!

Next week:  The IBM PC

See the entire John East series HERE.

Pictured:  Jerry Sanders

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Taking the Pain out of UVM

Taking the Pain out of UVM
by Daniel Nenni on 07-29-2019 at 5:00 am
Categories: Breker Verification Systems, EDA, Events

If you are interested in gaining a deeper understanding of the many ways you can leverage the Universal Verification Methodology (UVM), Breker Verification Systems has gone to a lot of effort to put that information at your fingertips.

A technical subcommittee of Accellera voted to establish the UVM in December 2009. UVM was based on the Open Verification Methodology (OVM-2.1.1), a verification methodology that had been developed jointly in 2007 by Cadence Design Systems and Mentor Graphics. In February 2011, Accellera (a non-profit organization) formally approved a Reference Guide, a SystemVerilog class library, and a User Guide. UVM was, to a large part, based on the eRM (e Reuse Methodology) for the e Verification Language developed by Verisity Design in 2001. Accellera was likewise was based on a merger of previous standards organizations. Most standards are adopted after the fact by a dominant format already in use; standard organization share that trait as well. Accellera’s stated mission is to provide a platform in which the electronics industry can collaborate to innovate and deliver global standards that improve design and verification productivity for electronics products. And they have been at it for a while. If you have been to a DVCon event, that is run by Accellera.

The Universal Verification Methodology (UVM) has proven to be highly effective in establishing common testbench coding methods, enabling reuse and improving the comprehension of tests. However, the methodology still has limitations that particularly impact complex block verification. The Accellera Portable Stimulus Standard (PSS) allows for many of these limitations to be eliminated, while still leveraging existing test benches, thereby not wasting legacy effort. PSS, through the Breker tools, enables a white-­‐box approach to test authoring, allows complex multi-­‐threaded, synchronized sequences to be generated from single scenarios, automatically provides scoreboard checks and coverage models, and generally improves test reuse and verification use models. The paper they have developed demonstrates how PSS may be leveraged in UVM environments to realize these and other advantages.

This thorough 24-page white paper will be given to attendees for Breker’s upcoming webinar, Eliminating Hybrid Verification Barriers Through Test Suite Synthesis. This webinar is the second the SemiWiki Webinar Series will be held at 10:00 am (PDT) on August 24, 2019. The primary speaker will be Aileen Honess. Aileen has more than 20 years of experience teaching, mentoring, and leading hardware verification projects across a variety of disciplines, companies, and continents. She is an expert in UVM and has recently been assisting those who are modernizing their verification methodology by adopting portable stimulus and portable specifications. To register for the event, click here, and be sure to register using your work email address.

As a special bonus, Breker intends to also give attendees a new white paper that is still in development. The working title for that white paper is ‘Finally, Thorough SoC Verification – Leveraging PSS Test Suite Synthesis for High-Coverage SoC Testing.’ This paper takes a deep dive into many of the topics that will be discussed at the webinar, so sign-up today.

About Breker Verification Systems
Breker Verification Systems is the leading provider of Portable Stimulus solutions, a standard means to specify verification intent and behaviors reusable across target platforms. It is the first company to introduce graph-based verification and the synthesis of powerful test sets from abstract scenario models. Its Portable Stimulus suite of tools is Graph-based to make complex scenarios comprehensible, Portable, eliminating test redundancy across the verification process, and Shareable to foster team communication and reuse. Breker’s Intelligent Testbench suite of tools and apps allows the synthesis of high-coverage, powerful test cases for deployment into a variety of UVM to SoC verification environments. Breker is privately held and works with leading semiconductor companies worldwide. Visit www.brekersystems.com to learn more.

Also Read

WEBINAR: Eliminating Hybrid Verification Barriers Through Test Suite Synthesis

Breker on PSS and UVM

Verification 3.0 Holds it First Innovation Summit

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SiFive Fosters RISC-V Collaboration and Education in India and Bangladesh Via Symposiums, Tutorials and Workshops

SiFive Fosters RISC-V Collaboration and Education in India and Bangladesh Via Symposiums, Tutorials and Workshops
by Swamy Irrinki on 07-27-2019 at 4:00 am
Categories: Events, India, IP, RISC-V, SiFive

Last year we hosted several SiFive Tech Symposiums in India to help promulgate the RISC-V ecosystem in the region. The enthusiastic reception from those in industry as well as students and faculty at India’s most esteemed universities was inspiring. This July and August, we’re bringing the SiFive Tech Symposium back to India, and also visiting Bangladesh. Our goal remains to foster the RISC-V ecosystem and to help prepare university students for entry into a workforce where RISC-V is heavily utilized. We have industry-centric symposiums planned in New Delhi/Noida, Pune, Bangalore and Hyderabad; and university-centric tutorials and workshops planned for Chennai, and Dhaka in Bangladesh. Attendance at all events is free, but registration is required. Here is a glimpse of what’s happening in each city. You can also visit the https://sifivetechsymposium.com to learn more about these and other SiFive Tech Symposiums being held throughout the world.

New Delhi/Noida Symposium – Monday, July 29

With Western Digital as our co-host, this event will feature presentations by Krste Asanovic, chairman of the RISC-V Foundation and co-founder and chief architect at SiFive; Western Digital; Ministry of Electronics & Information Technology, government of India; Silicon Catalyst; CircuitSutra Technologies; Computer Science and Engineering Department at IIT Delhi; and many more. There will also be a tutorial on SiFive’s Core Designer, which will demonstrate the ease and speed at which a customized CPU core can be built. To view the full agenda and to register to attend, please visit https://sifivetechsymposium.com/agenda-delhi-noida/

Pune Symposium – Wednesday, July 31

With Western Digital as our co-host, this event will feature presentations by Krste Asanovic, chairman of the RISC-V Foundation and co-founder and chief architect at SiFive; Western Digital; Hardware Design Group at the Center for Development of Advanced Computing (C-DAC, India); Silicon Catalyst; IoTIoT.in; and many more. There will also be a tutorial on SiFive’s Core Designer, which will demonstrate the ease and speed at which a customized CPU core can be built. To view the full agenda and to register to attend, please visit https://sifivetechsymposium.com/agenda-pune/

Bangalore Symposium – Thursday, August 1

With Microchip and Western Digital as our co-hosts, this event will feature presentations by Krste Asanovic, chairman of the RISC-V Foundation and co-founder and chief architect at SiFive; Microchip; Western Digital; QuickLogic; Silicon Catalyst; Morphing Machines; and many more. There will also be a tutorial on SiFive’s Core Designer, which will demonstrate the ease and speed at which a customized CPU core can be built. To view the full agenda and to register to attend, please visit https://sifivetechsymposium.com/agenda-bangalore/

Chennai Tutorial/Workshop – Saturday, August 3

With IIT Madras as our co-host, this academic-centric event will feature a presentation by Krste Asanovic, chairman of the board of the RISC-V Foundation and co-founder and chief architect at SiFive, and other industry veterans. There will be a tutorial on RISC-V cores and software, and a hands-on workshop where attendees will configure their own custom RISC-V core. This event presents a unique opportunity to network with RISC-V luminaries and solution providers. To view the full agenda and to register to attend, please visit https://sifivetechsymposium.com/agenda-chennai/

Hyderabad Symposium – Monday, August 5

With Western Digital as our co-host, this event will feature presentations by Western Digital; SRiX; CircuitSutra Technologies; and many more. There will also be a tutorial on SiFive’s Core Designer, which will demonstrate the ease and speed at which a customized CPU core can be built. To view the full agenda and to register to attend, please visit https://sifivetechsymposium.com/agenda-hyderabad/

Dhaka, Bangladesh Tutorial/Workshop – Aug 26

With the University of Dhaka and Ulkasemi as our co-hosts, this academic-centric event will feature presentations by executives at SiFive, a talk by a faculty member at the University of Dhaka, a tutorial on RISC-V cores and software, and a hands-on workshop where attendees will configure their own custom RISC-V core. This event presents a unique opportunity to network with RISC-V luminaries and solution providers. To view the full agenda and to register to attend, please visit https://sifivetechsymposium.com/agenda-dhaka/

We look forward to seeing you!

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SemiWiki Webinar Series: Who Wants to do a Webinar?

SemiWiki Webinar Series: Who Wants to do a Webinar?
by Daniel Nenni on 07-26-2019 at 10:00 am
Categories: Events

Webinars have been a popular form of communication since even before SemiWiki existed and they are a mainstay in today’s fast-moving semiconductor ecosystem.

In the past, SemiWiki has assisted with more than a hundred webinars. Today SemiWiki can do a complete webinar from start to finish using the GotoWebinar software. SemiWiki bloggers can assist with content creation and promotion, plus we have more than 8 years experience perfecting the webinar recipe. This brings us to the upcoming SemiWiki Webinar Series.

Thus far we have more than a dozen webinars in process. When the registration page goes live it will appear on the front page SemiWiki Webinar Series widget, which is also included in the weekly SemiWiki newsletter. More detailed information about the webinar will be available via blogs before the webinar goes live and after the webinar replay is available so stay tuned.

Here is what we have scheduled thus far:

 

GPU-Powered SPICE: The Way Forward for Analog Simulation

Eliminating Hybrid Verification Barriers Through Test Suite Synthesis

Avoiding CDM (Charged Device Model) ESD Failures

Fabless: The Transformation of the Semiconductor Industry

eFPGA – “What a great idea! But I have no idea how I’d use it!”

Ensuring System-level Security Through Hardware/Software Security Verification

Flexible, Multiprotocol IO’s in 7nm FinFets

The Brave New World of Customized Memory

VLSI Design Methodology Development

Enabling Efficient Engineering Infrastructure: Streamline your development resources and increase engineering productivity

Desinging Complex SoCs and Dealing with Multiple File Formats?

Please notice this is a mix of company sponsored and blogger specific webinars. For example, Paul McLellan and I will do a webinar on our 2019 updated version of  “Fabless: The Transformation of the Semiconductor Industry”. People who attend the webinar will be able to download a PDF copy of the book. Tom Dillinger will also be doing a webinar on his new book “VLSI Design Methodology Development” published by Prentice Hall. Other SemiWiki bloggers will be joining in the SemiWiki Webinar Series later this year as well.

One thing I wanted to consider is opening up the webinar series to SemiWiki members who have something personal to promote or something semiconductor to say for the greater good of the industry that we all know and love. Or if you have a topic that you would like us to cover in a webinar we can consider that as well. Please leave comments here or email me directly on SemiWiki.

Back to the scheduled webinars, participating companies are (in order on the widget): Empryean, Breker, Magwel, Flex Logix, Tortuga Logic, Concept Engineering, sureCore, Methodics, and Analog Bits with many more to come.

In the past 8 years and 7 months SemiWiki.com has attracted more than 3,094,662 users from 24,725 unique domains. We have published more than 6,530 blogs that have garnered more than 19,054 comments.  SemiWiki has also published 7 books (with 2 more coming this year) and dozens of white papers and reports.

SemiWiki is called a boutique media channel since we are semiconductor professionals who can write versus journalists. Our audience is worldwide with the top ten viewing countries: United States, India, Taiwan, Germany, United Kingdom, France, South Korea, Canada, China, and Japan.

While this was my initial concept, SemiWiki has developed and succeeded beyond all expectations as a collaboration between semiconductor professionals around the world, absolutely.

Thank you all again for being part of SemWiki’s amazing success and I hope to see you on a webinar real soon.