Bronco Webinar 800x100 1
Semiconductor Expert Forum

Posted on

Mentor-Tanner Illuminate MEMS Sensing, Fusion

Mentor-Tanner Illuminate MEMS Sensing, Fusion
by Bernard Murphy on 08-14-2019 at 6:00 am
Categories: AI, Automotive, EDA, Siemens EDA
2 Comments

I enjoy learning and writing about new technologies closely connected to our personal and working lives (the kind you could explain to your Mom or a neighbor). So naturally I’m interested in AI, communication and security as applied to the home automation, transportation, virtual, augmented and mixed reality, industry and so on – the burgeoning electronification of our world.

But there’s been a glaring gap in my coverage. All of this clever technology would have little or no value if it couldn’t sense key environmental factors – our orientation, acceleration, temperature, pressure, sound – the list is endless. This is a rich universe of innovation that, so far, I have only looked at peripherally. Now I’m getting more interested in this domain, and I’m starting with how Mentor/Tanner supports the design of the key elements at the heart of these sensors – microelectromechanical systems or MEMS – and the circuits that connect those systems to the rest of the electronics.

Take microphones. Not karaoke mics, but the ones you’ll find in smartphones, Amazon Echo speakers and the latest generation earbuds and hearing aids, supporting “Siri” and similar commands. Many of these are made by Knowles (about who I’ve written recently). The mic is a MEMS design, fabricated on silicon, but it doesn’t look much like conventional silicon circuits.

One basic structure might be a couple of membranes separated by a layer of air; as sound waves hit one of the membranes it flexes, changing the capacitance between the membranes. A different structure depends on sound waves flexing piezo-electric mechanical structures, generating electrical signals. Either way, analog circuitry next to the device detects the response. Then all that’s left is a little signal conditioning, converting the analog signal to digital for better noise immunity and you have yourself a microphone.

OK, gross oversimplification but that’s the general principal and it highlights one key aspect of MEMS: they are (at minimum) micromechanical devices with gaps between layers, cantilevered beams or host of other possibilities, all designed to respond to targeted ambient influences in a way that can be converted into electrical signals and passed on for analysis. Another big difference from conventional semiconductor lithography is that shapes of elements in these devices can be pretty much anything (Knowles microphones use circular membranes for example), where more conventional lithography at these dimensions is rectlinear.

As you might imagine, while manufacturing techniques for MEMS may start with the same techniques used for conventional semiconductors, these must be augmented with specialized micro-machining processes. Designing these systems is also challenging. If you thought analog + digital was hard, here you have to design and verify mechanical + analog + digital systems. Tanner is well-known for its expertise in this domain and certainly seems to be widely used. They cite Knowles and MEMSIC as customers; I’m sure there are more they haven’t chosen to share.

The tool-suite supports an interesting parallel flow – for MEMS, for analog and for digital circuitry (these may or may not be on the same die). I won’t bore you with the analog and digital flows except to mention that Mentor/Tanner have tools to support each step of design/analysis and implementation. For MEMS system design and simulation Tanner provides MEMS PRO. System simulation uses the Tanner circuit sim tools together with a behavioral model of the MEMS, derivable directly from your design when you start design from their library of composable models. And of course you can run full mixed-level simulation for all three domains.

For implementation, again Mentor Tanner provide tools for analog and digital flows. They don’t mention compatibility with 3rd-party flows though I’d guess they make some allowance for this, since the MEMS layout is unlikely to intermix with circuit layout. The MEMS implementation is of course Tanner-based, including evolving the design to 3D-solid modeling based on the target foundry and process. This model can then be taken into detailed finite-element analysis for mechanical, thermal, electromagnetic and fluidics analysis. And for layout verification, the Tanner tools include DRC checking which checks for the special features unique to MEMS layouts. (I’m assuming you’ll still use Calibre for the rest of the circuitry.)

The economics behind delivering sensors as packaged parts is also interesting. Expected unit prices for individual sensors are very low (<$1) so sensor-makers are motivated to combine multiple sensor functions. Combining a 3-axis gyroscope, 3-axis accelerometer and 3-axis compass in one device gives you a 9-axis sensor, especially important in VR and similar functions.

Taking this further, smart sensors are becoming routine in ADAS, combining one or more sensing functions with a controller to locally process and reduce data along with a communication interface. This may be more to reduce traffic on auto ethernets than to improve vendor ASPs, but the outcome is the same. Sensor fusion is a hot topic and that means more sensors and more functionality around those sensors must be integrated into a package.

Of course the Tanner tools are not only valuable for sensors. You can also build actuators, pumps, whatever you might need. Maybe that will be another blog. Meantime you can learn more about how Tanner/Mentor enable building these sensors from these two white papers: Sensors are Fundamental to New Intelligent Systems and Autonomous Drive Requires Smart Sensor Systems.

 

Posted on

eSilicon Brings a New Software Interface to its 7nm neuASIC Machine Learning Platform at Hot Chips

eSilicon Brings a New Software Interface to its 7nm neuASIC Machine Learning Platform at Hot Chips
by Randy Smith on 08-13-2019 at 10:00 am
Categories: eSilicon, Semiconductor Services

Figure 1: NeuASIC Platform Architecture

In early May of this year, eSilicon announced the tape-out of a test chip which included the latest additions to its neuASIC™ IP platform. At the upcoming Hot Chips Symposium to be held at Stanford on August 19 and 20, 2019, eSilicon will be demonstrating the software component of this AI-enabling IP platform. At the event, eSilicon will be giving live demonstrations of its AI Accelerator tool.  Late registration is still available for the event. The day before the symposium, various tutorials will be available at the same location. For more information on attending the Hot Chips, check the event website.

I learned first-hand of eSilicon’s ASIC design expertise more than 17 years ago when 2Wire, which had licensed the TriMedia VLIW core from me, asked me to find them help in designing their chip. I made the introduction to Jack Harding, eSilicon’s CEO, so I felt responsible for the success of that chip. eSilicon came through wonderfully and the chip, which became the engine inside AT&T’s initial UVerse residential gateway device, became enormously successful. Nearly two decades later, TriMedia has spun back into Philips Semiconductor (who then got acquired), 2Wire is now part of Pace, and AT&T is still a substantial player in the residential internet market – while eSilicon has continued to grow and is now much more than just a fabless ASIC company. Their capabilities and expertise now extend into 2.5D packaging, high-value IP (see my recent blog on their PAM4 SerDes IP) and more.

The neuASIC platform seeks to fill a void in the ASIC market for machine learning. Some of the reasons given for the challenges of an ASIC solution for this segment is that AI/ML algorithms are seemingly in near-constant flux. This uncertainty has made it difficult to design an ASIC chip and know that it will still be appropriate by the time the final product is to be shipped.

The neuASIC platform, available in 7nm FinFET technology, addresses this challenge with a modular design methodology. The solution provided utilizes a library of AI-specific tiles (i.e., macroblocks) that are quickly and easily configured to support the designer’s AI algorithm. These blocks, which are from eSilicon and other IP providers, can be configured using eSilicon’s AI Accelerator. This software will map high-level AI workloads expressed in languages such as TensorFlow to the neuASIC platform and do a quick PPA estimate for the algorithm in the resultant silicon implementation. Having this platform, including the software, allows design exploration of candidate architectures to ensure the design will be within the target specifications. While this architecture is quite flexible, the approach also supports algorithm changes that result in minor chip modifications such as tile changes or modifications to the 2.5D package used to accommodate changes in memory components. More details of the neuASIC platform are available here.

Following are some screenshots of a beta release of AI Accelerator. This will give you a feeling for the tool UI and flow.

Figure 2: AI Accelerator user interface
Figure 3: Graphical output of AI Accelerator
Figure 4: Parametric output of AI Accelerator

eSilicon has made a smart move in providing this software for configuring their neuASIC platform. Increasingly, designers are expecting software interfaces to aid them in configuring IP. Asking someone to code RTL with the correct parameters, or to follow instructions in a manual or user guide ignores the sometimes-complex interactions between the various options. The software approach is easier to use and less error-prone.

The AI Accelerator is part of eSilicon’s online Navigator environment for browsing its IP. Visit eSilicon’s STAR login page to access Navigator, or to sign up for a new account. It’s free. AI Accelerator will be available online when Hot Chips begins. In addition to pbtxt (TensorFlow), the software supports prototxt (Caffe) and json or yaml (Keras), used for machine learning applications such as neural networks.

As eSilicon is a Silver sponsor of Hot Chips, they will be providing a demonstration of the AI Accelerator at a tabletop in the main lobby of the event (there are no booths at Hot Chips). In addition to the demo of AI Accelerator, eSilicon will be discussing the content of a new white paper on Chiplets.

Posted on

Accelerate Your Early Design Recon

Accelerate Your Early Design Recon
by Alex Tan on 08-13-2019 at 6:00 am
Categories: Siemens EDA

A product launch nowadays demands shorter runway. SoC designers challenges are not so much in facing the unavailability of proven design capture methodologies or IP’s that could satisfy their product requirements, but more so in orchestrating the integration of all those components to deliver the targeted functionalities and performances.

While facilities for performing faster exploration by means of advanced modeling and prototyping during system architecture inception are widely accessible, shortening product development time requires scrutiny of long implementation processes. For example, high-level synthesis (HLS) has become mainstream and has provided a facility for exploration of system architecture configuration, power consumption, and design footprint versus feature tradeoffs. On the other hand, both functional and physical verification –which frequently dictate the success of the product launch, incur a late start due to the immaturity of most design blocks.

The motivation for early integration
With the plethora of AI and IoT oriented designs, the SoC integration efforts need to have an early start to align with a shorter product launch cycle. This translates to the need for having design methodology and point tools capable of providing early exploration and access to baseline metrics that highlight potential design integration issues.

A common chip design approach is to have concurrent chip integration and block development to minimize the number of DRC iterations as illustrated in figure 1. The main challenge to early chip-level physical verification includes an artificially high number of reported DRC violations of the unfinished design blocks –which in major part attributed to the widespread occurrences of systematic issues such as off-grid placement; incorrect via type on a clock net; incorrect routing layer and orientation of IPs.

 

Additionally, it is also a complex task to segregate between block-level and top-level routing violations as topological changes (block-level pin to the top-level net), physical constraints (routing resources) and its associated DRC rules might introduce variants in the generated violations. Likewise, to use the default settings in foundry rule decks for initial DRC runs also leads to long runtimes, a massive number of DRC errors and large database.

To enable design teams to start an early integration exploration while performing physical verification of their full-chip design layout, Mentor recently introduced Calibre™ Reconnaissance (in short, Calibre Recon). The tool is designated to effectively identify potential integration issues and generate quick feedback for corrective actions to the design teams, that eventually lead to lowering the DRC iterations and reducing physical verification time for tapeout closure.

In order to assess Calibre Recon effectiveness, we look into several areas: How it tackles with myriads of design rules while dealing with dirty designs?  What about runtime? Physical verification notoriously incurs long turnaround time.  How is it compared with the existing approach across designs?

Reduction in Rule Checks and Violations
Selecting relevant design rules is a daunting task as some rules may be important but may have long runtime in the presence of error. How does the designer know which ones to activate or to exclude? Which ones that will trigger advanced analysis? Indiscriminate selection of more categories such as antenna checks or all connectivity checks may also irrelevant for the current development phase and eventually produced sub-optimal results.

Calibre Recon automates the deselection process and decides based on the check type and the number of operations executed for the check. It aims for optimal coverage with quick runtime and less memory footprint. On average it cut the number of checks by half across various process nodes. The resulting deselection checks and categories are captured in the transcript for further reference. It honors the user’s manually pre-filtered checks/categories. As shown in figure 3, the total reports violations are reduced by as much as 70% of the original count and they facilitate the analysis and debugging of real systematic issues.

Runtime, Gray Boxing and nmDRC
Calibre Recon supports both early block-level verification and chip-level validation as these two types of efforts are usually done in parallel by design teams. Having top-level context feedback from Calibre Recon allows block designer to fix systematic reported issues and provides more productive time for block designers to concurrently focus on cleaning up the remaining rules violations internal to their blocks. As shown in figure 4, running the Calibre Recon tool on blocks (tiles) during initial routing resulted in up to 8x runtime improvement at 4x less memory.

Another critical part of the integration work involves checking the consistencies of interfaces across design blocks and IP’s. An unfinished design block can be fitted into the top-level scope as a grey box to allow the designer to focus on interface and top-level routing checks while ignoring some internal block details. It allows topology-accurate inclusion of all design blocks or IPs at the top-level view and permits a more meaningful top-level floorplanning and timing assessment.

The gray box approach may optionally be used in conjunction with Calibre Auto-Waivers functionality. It helps in preventing new DRC violations due to removing geometries from the affected cells. This is achieved by waiving any violations introduced by excluding regions from the specified cells and all waived violations are saved to a waiver results database files for later review. The grey box solution isolates integration and routing violations associated with the assembly from the immature block violations.

Mentor Calibre Recon tool was proven to reduce the overall DRC runtime by up to 14x, while covers about 50% of the total DRC set. Its application during early integration accelerates the overall design recon and provides early design integration metrics for successful tapeout.  For more details and chart of its application across a variety of chips, please check HERE.

Posted on

Webinar: Designing Complex SoCs and Dealing with Multiple File Formats

Webinar: Designing Complex SoCs and Dealing with Multiple File Formats
by Daniel Payne on 08-12-2019 at 10:00 am
Categories: Concept Engineering, EDA, Events

StarVision Pro

In SoC design it’s all about managing complexity through modeling, and the models that make up IC designs come in a wide range of file formats like:

  • Transistor-level , SPICE
  • Interconnect parasitics, SPEF
  • Gate and RTL, Verilog, VHDL

Even with standard file formats, designers still have to traverse the hierarchy to find out how everything is connected. IP reuse is here to stay, yet the challenge with using hundreds of IP blocks is finding out how they are all connected and to ensure consistency of signal naming conventions, and making sure that no pins are un-connected or misconnected. The debug process alone is time consuming and tedious, especially if you don’t have a specialized tool designed for the task.

Fortunately there is hope, because Concept Engineering has been in the forefront of providing engineers with a visualizing and debugging tool called StarVision Pro. There’s a webinar scheduled for Thursday, September 12th at 10AM PDT that will help engineers debug quicker by:

  • VISUALIZE: Render schematics on the fly for VHDL/Verilog/Spice level netlists to understand the function of design easily.
  • PRUNE: Extract, navigate and save critical timing paths/fragments of design as Verilog/Spice/SPEF netlists for reuse as IP or external use in partial simulation
  • CLOCK DOMAIN ANALYZER: Visualize and detect different clock domains in the design.
  • CROSS-PROBE: Drag & drop selected components/nets between all design views to cross probe and shorten debug time, especially during tape-out for full-chip debug. Also the ability to cross-probe analog and digital simulation data on the netlist.
  • PARASITIC: Visualize and analyze parasitic networks and create SPICE netlists for critical path simulation.
  • NETLIST REDUCTION: Instantly turn off/on parasitic structures in SPICE circuits for better comprehension of CMOS function
  • SKILL EXPORT: Export schematics and schematic fragments into Cadence Virtuoso.
  • SOC OR MIXED SIGNAL DESIGN: Visualize, Debug and Analyze the RTL, GATE, and SPICE Design in one cockpit!
  • DOCUMENT: Generate design statistics & reports: Instance & primitive counts
  • TCL API: Extend the functionality of StarVision to match project needs by interfacing with the open database through TCL scripts and in batch mode
  • IDENTIFY DIFFERENCES IN SCHEMATICS: Extend the capabilities of the tool to identify differences between designs.

At my last EDA company we used StarVision Pro to inspect SPICE netlists with extracted parasitics in order to understand connectivity and debug circuit simulation results, and this tool saved us hours of effort versus manually tracing and creating a schematic from a netlist. Why worker harder when you can work smarter?

Register online here.

Related Blogs

Posted on

Steve Jobs, NeXT Computer, and Apple

Steve Jobs, NeXT Computer, and Apple
by John East on 08-12-2019 at 6:00 am
Categories: John East

From time to time I give presentations to various audiences:  Silicon Valley the Way I Saw It.  I always enjoy doing that.  One particular section always makes me stop and think.  “Who was this guy? How did he do what he did? Why didn’t I do that?  “What made him so special?” It’s the Steve Jobs section. I met twice with Steve Jobs when I was working at AMD.  He was a fascinating human being. But, the stories about my meetings with him pale compared to the stories about Steve himself.  So – let’s spend some time going through a little bit of Apple / Steve Jobs history. Apple was formed in 1976 by Steve Jobs and Steve Wozniak.  They both went to high school a couple of miles from where I live, but we didn’t cross paths until much later in life. Their first real product, the Apple 2, did very well — particularly in the educational market.  They went public in 1980. Jobs made two hundred million dollars at the IPO. They kept growing and by 1984 their annual sales were approaching one billion dollars. What a success story!!

In 1983 the Apple board decided that they wanted an experienced CEO.  The view was that selling computers should not be a high tech sell — it should be a consumer sell    — more like selling refrigerators than selling mainframe computers. They wanted someone with those skills.  They also wanted someone more mature than Steve who was still under 30, had no previous experience at managing anything or anybody before Apple,  and was known to be a difficult person to work with. After an extensive search, they found John Scully, the VP of marketing at Pepsi Cola Company. Jobs loved Scully.  Scully loved Jobs. Apple really wanted Scully to join them. At first he was hesitant, but eventually Jobs convinced him to take the job using the famous line, “Do you want a chance to change the world, or do you want to spend the rest of your life selling sugared water to kids?”

In 1983, of course, DOS based personal computers (IBM PCs and their clones) were a lot closer to mainframe computers than they were to refrigerators.  In order to use them, you had to talk to the computer using DOS. You had to memorize a cumbersome set of instructions that were part and parcel of DOS.  A few examples of talking to a DOS machine:

DISKCOPY [drive1: [drive2:]] [/1] [/V] [/M]

move stats.doc, morestats.doc c:\statistics

type hope.txt | more

What the heck did those mean?  Who would want to learn that language?  And, of course, the syntax demands were exacting.  Any misspelling, extra space or incorrect punctuation would confuse the system.  Jobs had an answer for this. The mouse. The point and click, drag and drop interface that he had seen at Xerox PARC.  That interface was the critical feature of the soon to be announced MAC. Jobs didn’t invent point and click, but he recognized its beauty.  At his funeral in 2011 his wife Laurene said, “Steve had the ability to see what wasn’t there and what was possible.” The mouse was a perfect example of that.  She also reminded the room of something that Steve had told her. “If a customer is too stupid to use an Apple product, then it’s not the customer that’s stupid. It’s Apple that’s stupid!”.  Again — the mouse was a perfect example of how Steve thought.

Scully came aboard, of course, and at first he and Jobs worked together well.  They announced the first MAC in January of 1984 during the Super Bowl. (The 49ers beat the Miami Dolphins 38 – 16.  The game was at Stanford Stadium. I was there!!). The MAC used a mouse. The mouse made the MAC much, much easier for the layman to use than an IBM or IBM clone. The TV commercial that ran during the Super Bowl, which featured a lady javelin thrower in the days of George Orwell’s “Big Brother”, won any number of awards. Even today it’s viewed by many as the best commercial ever made.  The relationship between Jobs and Sculley was great! But then it started to fall apart. Soon it got to the point where the board had to choose between Jobs and Sculley. They chose Sculley. Jobs wasn’t fired, but he was demoted to a position he wasn’t willing to accept. He left shortly afterward in 1985.

When he resigned, he told the Apple board not only that he was leaving, but also,    “I’m taking five people with me” The big problem with that? He hadn’t told the five people he was going to do that.  They hadn’t yet agreed to join him. One of the five was Rich Page. Rich was one of four Apple fellows (“fellow” is the highest rank that an engineer can attain.  Steve Wozniak was also an Apple fellow.). Rich is still active in the Valley today doing angel investing and board work. He (Rich) told me that the five were absolutely shocked when they found out what Steve had done.  But — Steve really had the power of persuasion! Eventually all five signed up and left with Steve to form NeXT Computer. Steve had a concept in his mind that would lead to what he thought would be the perfect computer for schools.  The right feature set, the right price point, the right introduction date. It was going to be perfect!! 

“The ability to see what wasn’t there and what was possible.”  —– At NeXT he saw “what wasn’t there”, but he missed on the “what was possible” part.  He envisioned a great feature set, a great looking package, and a great GUI …… But those didn’t mesh at all with the great schedule and the great cost point that he had in mind.  Steve once said that creativity came from saying no 1000 times. He did that at NeXT, but it didn’t pay off. The machine came out late and with an unacceptably high price. Nobody wanted it.

NeXT was failing.

Next week:  My meetings with Jobs

See the entire John East series HERE.

Posted on

Webinar – Fabless: The Transformation of the Semiconductor Industry 2019 Update!

Webinar – Fabless: The Transformation of the Semiconductor Industry 2019 Update!
by Daniel Nenni on 08-10-2019 at 6:00 am
Categories: Events

As more than 343 people (and counting) know, we will be releasing the 2019 updated PDF version of our first book “Fabless: The Transformation of the Semiconductor Industry” via handout at a live webinar. The response has been overwhelming and I want to personally thank you. The webinar will be a brief overview of the book with a question and answer session. Co-Author Paul McLellan will make a brief video cameo as well. You can register for the webinar replay here. I hope to see you there, absolutely.

REPLAY: Fabless: The Transformation of the Semiconductor Industry Thursday August 22nd 7pm PDT.

The last 9 years really has been a personal and professional journey. It started in the summer of 2010 after my oldest son finished his undergraduate degree. He had 6 months before his graduate program so we spent that time in our living room creating SemiWiki.com which officially went online January 1st, 2011.  The rest as they say is history (in the making).

Here is the introduction to the book:

Paul McLellan, Daniel Payne, and I have more than 100 years of combined experience in the semiconductor industry. We started sharing our observations, opinions, and experiences when semiconductor blogging was just getting started. Many semiconductor bloggers followed, peaking at more than 200 in 2010. We literally brought blogging to the semiconductor industry, which was very disruptive at the time. Blogging is hard work and only the company (employee) bloggers would survive without independent blogger compensation. In 2011 Paul, Daniel, and I joined our blogs together to create a crowdsourcing platform (SemiWiki.com) to not only appeal to a wider audience, but to also get compensated for our efforts.

At first we were chastised for pretending to be journalists, in fact we were not allowed press passes or access to press rooms at conferences. The tide turned, of course, and now blogging is the media mainstay for all industries including semiconductors. Don’t be fooled by fancy executive editor titles, the majority of the news today is written by people like us who share observations, experience, and opinions. The difference of course is that most mainstream semiconductor bloggers do not have deep semiconductor experience like the SemiWiki contributors.

Dozens of people have blogged on SemiWiki and more than three million people have visited. SemiWiki has published more than five thousand blogs since 2011 garnering more than thirty-three million views.

The result is a trove of content and analytics of who reads what, when, where, how, and why. Several of the regular SemiWiki bloggers have launched off into bigger and better things but most are still here to stay active in the industry that we all love.

On June 1st, 2019 we launched SemiWiki 2.0 which will include an IP
Enablement Portal. We will talk about this more in the Semiconductor IP
Chapter update so keep reading. It will be another SemiWiki disruption and
we hope you will be part of it, absolutely.

SemiWiki has also published seven books, with more planned. This particular book started it all when Paul McLellan, Beth Martin, and I decided to document the history of the fabless semiconductor industry as published on SemiWiki.com. It was a labor of love since we posted a free PDF version and have given away thousands of print copies over the last six years.

A lot has happened in the semiconductor ecosystem since we first published in 2013 so we decided to do a revised edition. It has grown more than 50 pages and includes updates from eSilicon, Synopsys, Mentor Siemens, Cadence, ARM, and new “In Their Own Words” entries from Achronix, Methodics, and Wave/MIPS. Also included are industry updates on: FPGA, Foundry, EDA, IP, TSMC, GLOBALFOUNDRIES, and a new subchapter on IP Management. Most importantly there is a NEW chapter 8: “What’s Next for the Semiconductor Industry” written by EDA icon Dr. Walden Rhines. Thank you again for reading and I hope to see you on www.SemiWiki.com.

Daniel Nenni

Founder, SemiWiki.com LLC June 2019

Posted on

300mm Fab Watch 2019!

300mm Fab Watch 2019!
by Daniel Nenni on 08-09-2019 at 10:00 am
Categories: Semiconductor Services, TechInsights

Unless you are new to SemiWiki you should be familiar with Scotten Jones, founder of IC Knowledge, semiconductor process expert, and blogger extraordinaire. Scott joined SemiWiki in 2014 and has been blogging ever since with 130 posted thus far.

Scott’s, company, IC Knowledge LLC, is the world leader in cost modeling of Semiconductor and MEMS products with five different cost models covering low power silicon ICs, high power silicon and compound semiconductor ICs and discrete devices, MEMS products, assembly and test, and future IC technologies. Their cost models produce detailed cost and price projections. Models such as the MEMS and future IC – “Strategic Model” also produce details equipment and materials requirements. The forward-looking strategic model also includes a detailed roadmap of semiconductor technologies for the next decade and beyond.

IC Knowledge also produces a database of all the 300mm fabs in the world including both currently operating fabs and announced new fabs. The 2019 – revision 03 version is available now and includes detailed profiles of 190 fabs.

As of the end of 2019 IC Knowledge expects 146 – 300mm fabs to be operating made up of 14 development fabs and 132 productions fabs.

It is interesting to track the progression of capacity by country. In 2010 Taiwan had the most installed capacity followed by Korea, Japan, the US and China. By 2020 IC Knowledge is forecasting the capacity by country to switch to Korea at number one followed by China, and then Taiwan, with Japan and the the US in a distant 4th and 5th place respectively.

In terms of companies, the five largest in terms of currently installed capacity are Samsung followed by TSMC, SK Hynix, Micron and Toshiba. With the exception of TSMC at number two all of the top five companies primarily produce memory products.

In terms of the average size of fabs, the average foundry fab is just over 34,000 wafers per month, the average DRAM fabs is just over 80,000 wafers per month and the average 3D NAND fab is almost 88,000 wafers per month.
Worldwide 300mm wafer capacity has increased from 37.8 million wafers in 2010 to an estimated 83.2 million wafers in 2020.

In terms of number of fabs by product type, foundry has the most operating fabs followed by Flash and then DRAM. Foundry also has the most installed capacity followed by Flash and then DRAM.

The 300mm Watch database includes detailed profiles of each fabs with company, location, product, key dates, cost, cleanroom size, linewidths and capacity by year from 2010 to 2030. The database also includes analysis pages of capacity by linewidth, country, product and company, also number of fabs by type, and product and finally average fab capacity by year and type.
The following figure is an example from production fabs by type sheet that includes numeric values and two different graphs.

Figure 1. Worldwide number of 300mm fabs by type and year

The IC Knowledge 300mm Watch database is an essential source of information for anyone interested in tracking 300mm fabs.

For more information as well as pricing on any IC Knowledge product please go to www.icknowledge.com

List of blogs by Scotten Jones

Posted on

Chapter 5 – Consolidation of the Semiconductor Industry

Chapter 5 – Consolidation of the Semiconductor Industry
by Wally Rhines on 08-09-2019 at 6:00 am
Categories: Wally Rhines
9 Comments

For the last decade, semiconductor industry analysts have been writing articles and giving presentations that predict the increasing consolidation of the industry to the point where a few large companies dominate worldwide sales of semiconductor components.  In recent years there has been some justification for this view as the combined market share of the top five companies in the industry has increased, as has the combined market share of the top ten.

The general thesis of these discussions of semiconductor industry consolidation is the widely accepted model of growth and maturation of an industry.  Industries like steel, automobiles and others that have propelled decades of economic expansion in the world should grow rapidly in their youth and then slow down as their markets saturate and stabilize.  During this period approaching maturation, revenue growth is not large enough to drive increased profit and enterprise value so the focus becomes cost reduction.  By becoming more efficient, these mature industries reduce their labor and material costs, acquire competitors to achieve better economies of scale and reduce their research and development expenses since their industry is no longer evolving rapidly and there are fewer opportunities for new product and technology innovations. The acquisition process eventually leads to an oligopoly of a few large surviving companies that can achieve the required economies of scale to prosper despite their slow or declining revenue.

There are at least two problems with this kind of analysis.  First, the assumption that industries mature and consolidate down to a few large enterprises may be the exception rather than the rule.  Second, the analysis of the semiconductor industry as a candidate for this model in 2016 is probably premature since we’re seeing new growth in revenue and profits and innovation despite the sixty year age of the semiconductor electronics industry.

Consider first the assumption that most industries eventually consolidate.

Figure 1. Steel industry consolidation in the U.S.1,2

While consolidation certainly occurred in the U.S. steel industry in the 1960’s and employment has now been reduced by nearly 85%, the number of steel companies was only reduced by 50%.  New technology provided by mini mills created a set of new competitors in the industry.  Worldwide, consolidation of the steel industry has left us with far more than the classical oligopoly of companies (Figure 2). The five largest steel companies in the world account for only 18% of the revenue of the industry and it takes forty companies to account for half of the worldwide steel production.

Figure 2. Competitive state of the worldwide steel industry

The case of the automobile industry, though different, also provides insight into the maturation process of industries. Figure 3 shows the growth of the automotive industry, reaching a peak of 272 companies in 1909 and consolidating down to GM, Ford and Chrysler with 91% U.S. market share in the 1960’s.  This oligopoly was temporary, however, as foreign manufacturers from Europe, Japan and Korea gained market share in the U.S., passing the combined market share of GM, Ford and Chrysler in 2007. Emergence of electric cars and evolution of technology for driverless cars has stimulated the emergence of over 400 new companies announcing plans to produce electric cars and light trucks in the near future and nearly 200 planning driverless cars.

Figure 3.  Growth of the automobile industry

Are there any industries that consolidate down to an oligopoly and remain that way?  The answer is, “yes, but….”.  The well accepted model of consolidation seems to work in industries that operate in relatively free worldwide markets that are largely free of regulatory and tariff barriers and have a low cost of transport so that products can flow easily from one region to another. Two examples of this are the hard disk drive and the dynamic RAM (dynamic random-access memory) businesses.

Figure 4. Market shares of the leading hard disk drive manufacturers in 2017

The number of competitor companies in the hard disk drive industry peaked at 85.  Figure 4 shows the current state of that industry with three participants controlling almost 100% of the revenue of the industry.  But like most industries, technical discontinuities change the game.  Emergence of solid-state storage to replace rotating media hard disk drives is changing the market share outlook (Figure 5). Samsung is emerging as the new leader partly because of its leading position in the NAND FLASH component business.

Figure 5. Solid state storage changes the competitive landscape

The other example of the consolidation of an industry is the DRAM business.

Figure 6. DRAM worldwide market share. Combined share of the three largest companies grew from about 35% in 1994 to 95+% in 2016.

In 1997, the top three producers of dynamic RAM had less than 40% of the market. By 2014, they had 95%.  Both DRAMs and hard disk drives satisfy the requirement of low cost of transport. They are also industries that have relatively free market design, production and distribution worldwide.

How does all this relate to the broader semiconductor industry? Will it consolidate down to a dominant few companies and remain there, as the analysts suggest?  It’s doubtful, at least for the near term.  Let’s look at the history of semiconductor industry consolidation, or more accurately, its “deconsolidation”.

Since 1965, the semiconductor industry has been “deconsolidating” (Figure 7). In 1966, three companies, TI, Fairchild and Motorola, shared about 70% of the total semiconductor market.

Figure 7. Semiconductor industry deconsolidation from 1965 to 1972

Over the next seven years, that share dropped to 53%, driven by new entrants like National Semiconductor, Intel, AMD, LSI Logic and about 25 more.  Over the next 40 years, the market share of the top semiconductor company remained roughly the same, near 15% market share, although the names changed from TI in 1972 to NEC and then to Intel.  Combined market shares of the top five and top ten semiconductor companies decreased or remained flat during this period (Figure 8).

Figure 8.  Combined market share of the five and ten largest semiconductor companies

During 2016 through 2018, the combined market share of the top ten semiconductor companies increased modestly, partly due to an unusual increase in DRAM unit prices as well as a very strong computer server market that favored Intel.  The most remarkable piece of data is shown in Figure 9.  Throughout history, the combined market share of the fifty largest semiconductor companies has been decreasing.

Figure 9.  Combined market share of the fifty largest semiconductor companies from 2003 through 2014

This observation says a lot about the character of the semiconductor industry both now and throughout history.  Company leadership in the industry is continuously changing as new technologies emerge and new companies secure the leading market share in these new technologies.  Figure 10 shows the top ten ranking of semiconductor companies over a fifty year period. The company names shown in green are ones that have dropped out of the top ten and never reappeared except for NXP.  The number of companies that have retired from the top ten is greater than half of all those who have ever been in the top ten. Only Texas Instruments has remained in the top ten throughout the fifty year period and even it is probably destined to drop out as it focuses its business in analog and power and further disengages from the high volume “big digital” chips that constitute, along with memory, so much of the semiconductor revenue today.

It’s difficult for semiconductor companies to reinvent themselves as new growth markets emerge.  The large semiconductor companies tend to grow at about the overall semiconductor market average growth rate while the new entrants grow much faster, albeit from a smaller revenue base. Gradually, these small companies climb the ranks on their way to the top ten.

Figure 10. Top ten semiconductor companies change with time. Companies shown in green fell out of the top ten

Will the wave of merger mania in 2016 and 2017 continue into the future as the semiconductor industry finally matures and consolidates? Surely the competitive advantage of scale will lead to more mergers and a more difficult environment for small companies to compete without the scale of the big ones? The recent slowing of merger activity, although significantly affected by government regulatory disapprovals, suggests that we may not have reached that stage of consolidation (Figure 11). Actual numbers make 2017 and 2018 among the lowest dollar value of major merger years in recent history, both in number and in enterprise value. The recent increase in semiconductor industry revenue growth rate to 22% in 2017 after two years of no growth also suggests that the announcement of industry maturity may have been premature.

Figure 11.  Value of semiconductor industry mergers by year

In the next chapter, we will examine the factors behind the consolidation that has been occurring. A reasonable conclusion would be that the limited amount of consolidation that is occurring in the semiconductor industry is not motivated by size or broad economies of scale but by specialization.  Profitability in the semiconductor industry is driven by market share in very specific specialties and the industry is in a transition to increased specialization which is also increasing overall profitability.

1https://www.nwitimes.com/business/local/steel-ceo-more-consolidation-inevitable/article_c407cc83-7d1b-59eb-a838-f1ea1723845c.html

2https://247wallst.com/investing/2010/09/21/americas-biggest-companies-then-and-now-1955-to-2010/

Read the completed series

Posted on

WEBINAR: The Brave New World of Customized Memory

WEBINAR: The Brave New World of Customized Memory
by Randy Smith on 08-08-2019 at 10:00 am
Categories: Events, IP, sureCore

The need to design low power devices is not new. However, the criticality of lowering the power consumption of chip designs has never been as important as it is now. In 1989, I purchased one of the first consumer cell phones produced by Panasonic. The battery was the size of a brick, but only about a third of the thickness. If the battery were half that size, it would not have mattered much to me since it was still like carrying a purse. Or sometimes I clipped it into a docking station under the passenger seat of my car. Today, in cell phones and a myriad of IoT devices, battery size is critical, as is the total runtime available on a single charge to the system. While battery technology is important, it is even more important to reduce the power required to operate a device. Founded in 2011 with just this focus in mind, sureCore Limited will be presenting at a SemiWiki Webinar Series event to discuss the technologies that they have available to assist chip designers and chip architects in substantially reducing chip power.

For at least the past 20 years, memory blocks have dominated the on-chip real estate. The larger area has also consumed the largest portion of the chip power budget. sureCore has developed an arsenal of low power memory IP services and products to enable designers to build customized low-power SRAM memory blocks – SureFIT™, PowerMiser™, and EverOn™. These are not simple memory compiler solutions as they integrate very advanced features supporting low power. For example, EverOn has been built to support DVFS (dynamic voltage and frequency scaling).  sureCore’s “SMART-Assist” technology allows robust operation down to the retention voltage, critical in ‘keep-alive’ specifications.

Memory compilers have been used for a couple of decades now, though not all have been successful in their ability to deploy in low power processes. These tools are used to generate SRAM memory blocks over a huge number of memory configurations and memory specification options for a specific process. There is a need for them to be quite robust in the face of low voltage thresholds, process variation, and a large number of possible option choices. To do this, the memory architecture, as well as the generators, need to embed special knowledge beyond simply repeating bit cell patterns. There may be the use of self-timing chains or circuits tricks to get the memories to work based on the options selected. These designs seem to be built using engineering, science, – and art.

The event will be moderated by SemiWiki founder, Daniel Nenni. The presenter will be Paul Wells. Paul has worked in the semiconductor industry for over 30 years. He co-founded sureCore in 2011 and has kept them focussed on the market for low power embedded SRAM. His previous experience in design & management at several respected companies such as Pace Networks, Jennic Ltd., Plessey Semiconductors and Fujitsu Microelectronics, has enabled sureCore to build this broad yet focused portfolio of low power memory IP solutions while also offering a Low Power Mixed Signal Design Service.

This webinar, “The Brave New World of Customized Memory” will be held on Wednesday, August 28, 2019, from 10:00a m to 10:45 am PDT. To sign up for the webinar, register using your work email address HERE. A replay URL will be sent to all registrants in case you miss the live version.

About sureCore
sureCore Limited is an SRAM IP company based in Sheffield, UK, developing low power memories for current and next-generation, silicon process technologies. Its award-winning, world-leading, low power SRAM design is process independent and variability tolerant, making it suitable for a wide range of technology nodes. This IP helps SoC developers meet challenging power budgets and manufacturability constraints posed by leading-edge process nodes.

Posted on

Tortuga Webinar: Ensuring System Level Security Through HW/SW Verification

Tortuga Webinar: Ensuring System Level Security Through HW/SW Verification
by Bernard Murphy on 08-08-2019 at 6:00 am
Categories: Cadence, Events, Security, Synopsys, Tortuga Logic, Xilinx

Jason Oberg

We all know (I hope) that security is important so we’re willing to invest time and money in this area but there are a couple of problems. First there’s no point in making your design secure if it’s not competitive and making it competitive is hard enough, so the great majority of resource and investment is going to go into that objective. Security might get one person or a small team, working with the hardware root of trust and providing guidance and review for the rest of the design team. Which the latter will address and prioritize as best they can among the thousand other things they have to do.

WEBINAR REPLAY

Then there’s that nagging question – how much work do I have put into security verification to know my design is truly secure? Does this mean lots of new simulation and formal testbenches have to be built, and what should they be stimulating and checking? Even more important, a lot of emerging hardware hacks leverage a combination of software and hardware (Spectre for example). How are you going to check these? Formal is out, and for simulation how would you even stimulate, much less check for these classes of problem? Even if you could answer these questions for specific threats (each probably a research project in its own right) is it feasible to cover a realistic set of potential threats?

That’s a lot of questions without easy answers in traditional design verification. You want to do a thorough job, but you don’t want to have to create masses of new and highly complex testbenches. Fortunately there’s a good answer. Tortuga have been developing technology around this area for multiple years and are now partnered with Synopsys and Cadence and licensed by Xilinx. They have a very interesting approach to both build confidence that you are comprehensively covering a range of threats and to reuse existing verification testbenches in their analysis. That’s exactly what you need, and I have to believe that this stuff works, based on their industry references.

Check out their upcoming webinar on applying these techniques to your hardware root of trust.

WEBINAR REPLAY

Summary

In this webinar, we will discuss common hardware security concerns in many market verticals including IoT, Datacenter, and Aerospace/Defense that are often centered around a Hardware Root of Trust. We then discuss common hardware security verification techniques, as well as their benefits and drawbacks. Next, we will present the best-in-class techniques and methodologies for understanding the system security ramifications of a mixed hardware/software system. Lastly, we will present an example security analysis on a real-world hardware/software system using the discussed techniques.

All attendees will receive a copy of the white paper, “Detect and Prevent Security Vulnerabilities in your Hardware Root of Trust.”

The presenter will be Jason Oberg, co-founders and Chief Executive Officer of Tortuga Logic. Jason oversees technology and strategic positioning of the company. He is the founding technologist and has brought years of intellectual property into the company. His work has been cited over 700 times and he holds 6 issued and pending patents. Dr. Oberg has a B.S. degree in Computer Engineering from the University of California, Santa Barbara and M.S. and Ph.D. degrees in Computer Science from the University of California, San Diego.

About Tortuga Logic
Founded in 2014, Tortuga Logic is a cybersecurity company that provides industry-leading solutions to address security vulnerabilities overlooked in today’s systems. Tortuga Logic’s innovative hardware security verification platforms, Radix™ enable system-on-chip (SoC) design and security teams to detect and prevent system-wide exploits that are otherwise undetectable using current methods of security review. To learn more, visit www.tortugalogic.com.