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China Winning the Future of the semiconductor industry?

China Winning the Future of the semiconductor industry?
by Bart van Hezewijk on 09-01-2019 at 11:00 am
Categories: General
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In this second article about China’s role in the global semiconductor industry I analyse the impact of the Chinese government’s Big Fund and compare Chinese investments in semiconductor R&D with those in other countries. In my previous article, I looked at the possible effects of a US-China decoupling in the semiconductor industry. Both articles are available in Chinese as well: decoupling, Big Fund (文章翻译成中文：脱钩，大基金).

The Chinese government has made no secret of its ambitions to further develop the domestic semiconductor industry. In May the Chinese Semiconductor Industry Association (CSIA) reported that the value of China’s integrated circuit (IC) imports reached $312 bn in 2018 and has been higher than the value of crude oil imports for some years already. The “Made in China 2025” policy, published in May 2015, mentions specific targets to increase self-sufficiency in IC production to 40% in 2020 and 70% by 2025. It is clear that China aims to accelerate the development of the semiconductor industry and reduce the reliance on imports of chips.

To help reach these goals, the Chinese government established the China Integrated Circuit Industry Investment Fund (CICIIF) or ‘Big Fund‘ in September 2014. The Big Fund was set up to invest in and promote mergers and acquisitions in the semiconductor industry. Beijing envisioned spending more than $150 billion over 10 years to stimulate developments in semiconductor design and manufacturing.

The Big Fund is a government-guided investment fund and operates as a corporate entity under the Ministry of Industry and Information Technology and the Ministry of Finance. The largest shareholders include the Ministry of Finance (36%) and several state-owned enterprises (SOEs), such as China Development Bank Capital (22%), China Tobacco (11%), E-Town Capital (10%), and China Mobile (5%).

The national government encourages local governments, SOEs, private capital, and even overseas investors, to participate in the Big Fund. But since the government is one of the investors it should be considered a government-guided fund according to the National Development and Reform Commission (NDRC). The NDRC lists seven areas for government funds to invest in, which include ‘strategic emerging industries and advanced manufacturing industries,’ and ‘innovation and entrepreneurship.’

Round One: The Big Fund raised CN¥138 bn ($22 bn) in its first tranche in 2014.

One of the major players in the Chinese semiconductor industry is mainland China’s largest foundry Semiconductor Manufacturing International Co. (SMIC). In February 2015, the Big Fund became HK-listed SMIC’s second biggest shareholder acquiring 4.7 billion new shares for HK$ 3.1 bn ($400 M). Currently, the fund holds almost 16% of SMIC’s shares (right behind Datang holding 17%).

Another major transaction involving the Big Fund in 2015 was the $780 M buyout of Singapore-based STATS ChipPAC, the world’s fourth largest chip-packaging and testing company at the time, by Jiangsu Changjiang Electronics Technology (JCET). The buyout included a $240 M investment by the Big Fund and a $150 M investment by a subsidiary of SMIC (SilTech). It instantly made JCET the number three packaging and testing firm in the world.

The Big Fund has been used to support the creation of a joint venture between Nantong Fujitsu Microelectronics (now known as Nantong Tongfu Microelectronics, TFME) and AMD Penang (Malaysia) and AMD Suzhou (China) in April 2016. With AMD‘s world class assembly and test technologies TFME aims to develop into a global Outsourced Semiconductor Assembly and Test (OSAT) company.

In March 2017 Tsinghua Unigroup signed a deal to receive up to CN¥150 bn investment, two-thirds coming from China Development Bank and one third (no less than $7 bn) from the Big Fund. The company did not provide any specific details how the money would be used, other than upgrading its R&D and scale up its operations. Tsinghua Unigroup acquired Spreadtrum Communications and RDA Microelectronics in 2013 and 2014 respectively. Its subsidiary focused on R&D of core chipsets for mobile communications and IoT is now known as UNISOC and is China’s second largest mobile chipmaker, after Huawei’s HiSilicon.

Last year January SMIC set up a joint venture with the Big Fund and the local government’s Shanghai IC Fund focusing on 14nm and below process and manufacturing technologies. The Big Fund invested $947 M for 27.0% of shares, Shanghai IC Fund invested $800 M for 22.9% of shares and SMIC invested $1.54 bn to be Semiconductor Manufacturing South China’s (SMSC) majority shareholder holding 50.1% of shares.

In the first round, the Big Fund invested in more than 70 projects and companies, some of whom are listed on the Hong Kong, Shanghai, Shenzhen and NASDAQ stock exchanges. These include above-mentioned Tongfu Microelectronics (Big Fund holds 22% of shares), JCET (19%), and SMIC (16%). But also test equipment company Changchuan Technology (7%), wafer cleaning technology company ACM (6%), etch tools and MOCVD system maker Advanced Micro-fabrication Equipment Inc. China (AMEC, listed on the Shanghai Stock Exchange STAR Market since July 22), equipment maker NAURA Technology Group, and Yangtze Memory Technologies Co. In all these cases, the Big Fund did not become the majority shareholder through its investments, which is in accordance with a statement of fund President Ding Wenwu in 2015 that the Big Fund did not seek to become the largest shareholder of the companies it invested in.

This is not necessarily the case for other funds the Big Fund participates in. In May 2018, the Big Fund joined a group of companies to set up the $244 M IPV Capital Global Technology Fund to invest in semiconductor companies. The Big Fund committed $121 M and controls 49.5% of the fund, L&L Capital 39.29%, SMIC’s subsidiary China IC Capital 10.21%, and IPV Global 1%.

Round Two: The Big Fund raised CN¥200 bn ($29 bn) by July 2019 in its second tranche, which was announced in March 2018.

Last month the fund raising for the second tranche of the Big Fund was completed with a total commitment of CN¥200 bn ($29 bn). New investments will likely be more focused on applications in the downstream supply chain of the semiconductor industry, such as chip design, advanced materials, and tools and equipment. Considering the investment priorities for 2019 as mentioned by the NDRC: Artificial Intelligence (AI), the industrial internet, Internet of Things (IoT), and 5G, promising chip design companies in these areas could be looking at an interesting year ahead if they are looking for funding.

Big Fund = Big Impact?

In its first two rounds, the Big Fund has raised an impressive total of $51 bn. But exactly how impressive is this in the capital- and R&D-intensive semiconductor industry?

The American Semiconductor Industry Association (SIA) writes in its April 2019 report‘Winning the Future – A Blueprint for Sustained US Leadership in Semiconductor Technology’ that “Technology challenges and ambitious steps by foreign governments put at risk continued semiconductor innovation and US leadership in this sector. (…) Although US companies still lead the world with nearly half of global market share, state-backed competition from abroad seeks to displace US leadership.” And more specific on the potential impact of the Big Fund: “The Chinese government has announced efforts to invest well over $100 billion over the next decade to catch up to the United States in semiconductor technology, artificial intelligence, and quantum computing. While China may not meet all its goals, the size and scale of its effort should not be ignored.”

In the remainder of this article, I analyse the size and scale of R&D spending and investments in the semiconductor industry for the most relevant countries in the industry. For each of them I looked at the R&D spending of their most important semiconductor companies and, if available, data on semiconductor R&D specific government funds or investments. I have to note it is very challenging to find (reliable) data on government funding or investments specific to the semiconductor industry. As the focus is on semiconductor industry R&D, I have not looked at government funding for purely academic research. Therefore, the data is definitely not complete, but I believe it still gives a general idea about the differences in semiconductor-related R&D and investments in these countries.

For industry R&D expenses, I looked at a selection of semiconductor companies active in the entire value chain, including chip design companies, equipment makers, and chip production companies. The last category includes front-end wafer fabrication as well as back-end testing, assembly and packaging. This R&D data is more readily available from the companies’ annual reports. I only included companies that have annual R&D expenses exceeding US$100 M, except for China. Because the Chinese semiconductor industry is not as mature yet, the focus of this article is on the potential impact of the Big Fund, and including more Chinese companies probably means learning about new companies for many readers, I decided not to use this threshold for Chinese industry R&D expenses.

US American semiconductor companies have by far the highest R&D expenses. Intel’s R&D spending of $13.5 bn in 2018 (19% of sales) is far higher than any other company in the world. Within the US, Intel is followed by Qualcomm ($5.6 bn, 25%), Broadcom ($3.8 bn, 18%), Nvidia ($2.4 bn, 20%), Micron ($2.1 bn, 7%), Applied Materials ($2.0 bn, 12%), Texas Instruments ($1.6 bn, 10%), AMD ($1.4 bn, 22%), Lam Research ($1.2 bn, 11%), Marvell ($914 M, 32%), Xilinx ($743 M, 24%), ON Semiconductor ($651 M, 11%), KLA ($609 M, 15%), Maxim Integrated ($451 M, 18%), Cypress Semiconductors ($364 M, 15%), Teradyne ($301 M, 14%), and Amkor ($157 M, 4%). Together, these 17 companies spent $35.8 bn (16% of their combined sales of $234 bn) on semiconductor research and development. Per year! In the ‘Winning the Future’ report, SIA urges the US government to triple US investments in semiconductor-specific research from the current $1.5 bn to $5 bn annually, to ensure continued US leadership in the global semiconductor industry.

South Korea On April 30, South Korean President Moon Jae-in spoke at the ceremony to unveil Korea’s ‘System Semiconductor Vision’: “We will expand government R&D in the semiconductor field, giving top priority to promising technologies in high demand. Starting next year, a technology development project worth one trillion won ($0.86 bn) will be pursued as part of the efforts to secure original technologies for next-generation semiconductors.” As a reaction to Japan’s tightening of semiconductor materials exports to Korea, the Korean government also recently announced plans to invest 1 trillion won annually ($0.86 bn) to develop semiconductor materials. Samsung’s reported semiconductor revenue is $77.2 bn, but the annual report does not mention R&D spending for its semiconductor division. R&D expenses as percentage of sales for the whole company are 7.5% and considering semiconductor sales represent 35% of Samsung’s total sales, I take $5.8 bn (7.5% of $77.2 bn) as an estimate for Samsung’s semiconductor-related R&D expenses. With SK Hynix reporting R&D expenses of $2.6 bn in 2018 (7.1% of sales), Korea’s two semiconductor giants spent $8.4 bn (7.4% of their combined sales) on R&D.

Taiwan TSMC is the semiconductor industry’s top R&D spender in Taiwan with $2.9 bn, or 8.3% of sales. MediaTek follows with $1.9 bn (24%), before ASE Technology Holding ($490 M, 4.0%), UMC ($427 M, 8.6%), Realtek ($425 M, 28%), Novatek ($254 M, 14%), Winbond ($252 M, 15%), and Nanya (NTC, $160 M, 6%). These 8 Taiwanese semiconductor companies spent $6.8 bn or 10% of their combined sales ($66.1 bn) on R&D. President Tsai Ing-wen mentioned last year that the government is committed to developing Taiwan’s semiconductor sector and providing all requisite assistance for local firms upgrading competitiveness and retaining leadership positions. However, I did not find any specific details on governmental research funding or investment support for the semiconductor industry.

Japan Renesas leads semiconductor R&D spending in Japan with $1.1 bn (17%), followed very closely by Sony Semiconductor Solutions ($1.1 bn, 14%). Toshiba Memory has separated from Toshiba and will continue as Kioxia Holdings, but Toshiba Memory’s R&D expenses in the year ending March 2018 were also $1.1 bn (10%). Tokyo Electron’s R&D expenses were $1.0 bn or 9% of sales in 2018. Rohm Semiconductor follows with $357 M (10%), Advantest spent $341 M (13%) and Dainippon Screen spent $206 M on R&D (6%). Together these seven companies spent $5.2 bn on R&D (10% of their combined sales of $49.6 bn). I did not find any information on government funds for R&D or investments in the Japanese semiconductor industry.

The Netherlands In the Netherlands the only recent semiconductor-related government investment is a $86 M investment for a public-private photonics initiative. The top 3 Dutch semiconductor companies spent a combined $3.6 bn on R&D (16% of their combined sales of $22.7 bn). ASML leads Dutch semiconductor industry R&D investments with $1.8 bn (14%), followed by NXP ($1.7 bn, 18%), and ASM International ($101 M, 11%).

China HiSilicon is most likely China’s biggest semiconductor R&D spender but it does not publish financial data. HiSilicon’s 2018 revenue is reported to be $7.3 bn. Taking parent company Huawei’s R&D expenses as percentage of sales (14%) as a proxy, HiSilicon’s R&D expenses would be around $1.0 bn. For UNISOC I take a similar approach. Using parent company Tsinghua Unigroup’s R&D expenses as percentage of sales (30%) for UNISOC’s revenue, their estimated R&D expenses are $480 M. For one more non-listed company, Beijing OmniVision, revenue is reported to be more than $1.0 bn but I did not find any information on their R&D expenses. For China’s listed semiconductor companies, SMIC spends by far the most on R&D reporting $558 M R&D expenses in 2018 (15% of sales). Packaging and testing company JCET spent $129 M (4%), followed by IC design company Goodix, who recently acquired NXP’s Voice and Audio Solutions, with $121 M (23%). TFME spent $81 M (8%), Tianshui Huatian Technology $56 M (5%), equipment maker NAURA $51 M (11%), pure-play foundry HHGrace $45 M (5%), GigaDevice $30 M (9%) and equipment maker AMEC $17 M (7%). Combined, these eleven Chinese companies’ R&D expenses are $2.6 bn, or 13% of their combined sales ($20.3 bn).

The industry R&D expenses for all companies except Samsung, HiSilicon and UNISOC are derived from the companies’ annual reports. To compare annual R&D expenses and investment, I divide the money raised by China’s Big Fund in its first round ($22 bn) over 4 years (2015-2018), which results in an average annual budget of $5.5 bn.

Industry and government spending on semiconductor R&D

Figure 1: Industry and government spending on semiconductor R&D

Figure 1 shows that only in China the government’s semiconductor investments are (much) higher than the companies’ R&D expenses. For example, the government’s investments in China are more than 2 times as much as industry R&D expenses. Whereas in the US, industry’s R&D expenses are 25 times as much as the government’s semiconductor-specific research funding.

However, it is not completely clear how much of the Big Fund’s first round funding has been spent until now. The assumption that $22 bn has been spent over 4 years (2015-2018) may not be completely accurate, but it’s my best guess. When the Big Fund was established in 2014, the plan was to invest more than $150 bn in ten years, which amounts to an average annual spending of $15 bn. This is considerably more, but still not much more than Intel’s current annual R&D expenses of $13.5 bn. Including the second round, the Big Fund has raised $51 bn until now, but we are also halfway the original 10 years horizon. So, either the initial goal of raising $150 bn was overly enthusiastic or the government has to accelerate fund raising.

Comparing semiconductor R&D spending across countries, it is clear from Figure 1 that the R&D expenses of Chinese companies lag behind those of other countries, even including the six Chinese companies that spend less than $100 M on R&D. It should also be mentioned that many Big Fund investments are not targeting R&D per se. Actually, a lot of funding so far has been used for expanding fab capacity (e.g., SMIC, SMSC, HHGrace, Huali, Yangtze Memory Technologies). Building more capacity for current technology nodes may help to increase sales and thus potential future R&D expenses, but the global semiconductor industry keeps moving ahead. If China does not invest more in R&D, it will continue to be very challenging to catch up from a technology perspective.

Conclusion

Does the Big Fund have a Big Impact on the development of the Chinese semiconductor industry? Yes. More investments in China’s semiconductor industry are required for China to achieve its goals of increasing self-sufficiency in IC production and accelerating the development of the domestic semiconductor industry. And $150 bn is a lot of money.

But… The impact of the Big Fund should also be put in perspective. The size and scale of China’s effort to invest in semiconductor technology is impressive, for a government fund. However, the R&D expenses of semiconductor companies in some other countries are at least as impressive. There are many companies in the semiconductor industry that spend more than $1 bn on R&D every year. I mentioned 20 in this article, but there are more (e.g., ST Microelectronics), and some are very close to the $1 bn mark (e.g., Marvell and Infineon). Figure 1 shows that the US is still far ahead of all other countries when it comes to semiconductor R&D. Actually, the top 10 US semiconductor companies, ranked by R&D spending, together spend more on R&D every year than all industry and government spending of the other countries combined ($34.5 bn vs $33.9 bn). So, the Big Fund does definitely not instantly make China the global leader in semiconductor R&D investments. Moreover, the Big Fund’s investments are not all focused on technology development, but for example at increasing capacity and acquiring existing technology. There is still a long way to go before China is winning the future and leading innovation in the semiconductor industry.

Bart van Hezewijk

Officer for Innovation, Technology & Science

Holland Innovation Network

Consulate-General of the Kingdom of the Netherlands in Shanghai

@bartvanhezewijk

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3D TCAD Simulation for Power Devices

3D TCAD Simulation for Power Devices
by Daniel Payne on 08-30-2019 at 10:00 am
Categories: EDA

Silvaco: Split Gate, Figure 1

My first IC design back in 1978 was a DRAM and it ran on 12V, 5V and -5V, but then my second DRAM was using only a 5V supply. Today we see SOCs running under a 1V supply voltage, but there is a totally different market for power devices that are at the other end of the voltage spectrum and they handle switching ranges from 12V – 250V. To learn more about power devices and how the process and device modeling is done, I read a Silvaco publication entitled Advanced Process and Device 3D TCAD Simulation of Split-Gate Trench UMOSFET.

For vertical discrete power MOSFETs there are two important specifications that engineers look at:

  • Breakdown voltage (BV)
  • Specific on-state resistance (RSP)

A couple of approaches have been used for power devices: Trench MOSFETs, RSO MOSFETs. The winning approach has been the Split-Gate RSO MOSFETs because of their low channel resistance, plus ultra-low drift region resistance with a smaller Cgd (gate-to-drain capacitance), improving switching speeds.

Process engineers use 3D TCAD tools to model power devices and optimize them by looking at the predicted values of:

  • Capacitance-Voltage (C-V)
  • Current-Voltage (I-V)
  • Breakdown Voltage (BV)

Silvaco provides Victory Process and Victory Device simulators to do this modeling of power devices. So let’s start with a 3D process simulation of a Split-Gate UMOSFET, where Victory Process is used to build the device structure. Several simulated process steps  are shown below:

a) Formation of a deep trench with rounded bottom, both dry and wet etch steps

b) Shield oxide growth

c) Shield poly deposition

d) Inter-poly oxide deposition and etch back

e) Gate poly deposition and etch back

f) Core contact etching and deposition of the contact plug

Victory Process simulation of key process steps to fabricate the Split-Gate UMOSFET

A 3D numerical mesh is the next step using the Victory Mesh tool, and a 3D Delaunay mesh was generated to accurately resolve the 3D geometrical features. Here’s the result of meshing:

Delaunay mesh to resolve complex 3D geometry features (a) and doping profiles (b)

3D device simulations are then run with the Victory Device simulator, and this is quite powerful because it can model 3D unstructured tetrahedral meshes for any device shape. To run Victor Device simulations you have several actions:

  • Specify the materials, models and simulation values
  • Simulate steady-state  Id-Vg, gm-Vg, Id-Vd and BV
  • Small-signal (AC) capacitance-voltage (C-V) plot
  • Device switching plots

An initial solution is computed, then Id-Vg curves are produced for each Vds voltage, then transconductance gm-Vg are computed as shown below:

Computed Id-Vg curve (at Vd=0.1V) and extracted transconductance gm-Vg characteristics

Here’s the plot of Id-Vd at a select Vgs bias voltage:

Computed Id-Vd output characteristics, for selected Vg bias (Vg = 5V)

A plot of Breakdown I-V is shown where the gate bias Vg = 0V:

Computed Breakdown I-V characteristics, for Vg=0V

Each of these I-V curves was generated by the TonyPlot tool.

C-V plots are simulated with Victory Device, and here’s the small-signal (AC) results showing intrinsic capacitances:

Computed device Capacitances versus Gate Voltage (Vg)

Summary

Process engineers equipped with the proper modeling and simulation tools can now predict the behavior of power devices like Split-Gate Resurf Stepped Oxide (SG-RSO) MOSFET. Instead of running lots of silicon, measuring, tweaking and repeating, engineers can accurately model and optimize virtually, saving lots of time and money. Read the complete article online.

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Chapter 8 – Value Through Differentiation in Semiconductor Businesses

Chapter 8 – Value Through Differentiation in Semiconductor Businesses
by Wally Rhines on 08-30-2019 at 6:00 am
Categories: Wally Rhines
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Gross Profit Margin Percent Provides a Measure of Product Value

The difference between what customers will pay for a physical product and what it costs to make or acquire it is a good measure of differentiation. This difference divided by the revenue is the gross profit margin percent or GPM%. Once a product has an established market share, difficulty of switching to another product usually maintains or enhances the GPM% even if the product differentiation diminishes.

At the time the Apple iPhone was introduced in 2007, it was priced at $749 “unlocked” (i.e. without service provider subsidy) compared to commodity cell phones that sold for $15 at the same time (Figure 1). Why would anyone pay fifty times more for a product that did the same thing – made phone calls and sent text messages? Apple proved that there was much more differentiation possible.

Apple’s previous attempts with differentiation encountered some difficulties (Figure 2). Before the IBM personal computer was introduced, Apple was able to capture one third of the PC market and maintain a GPM% between 40% and 50%.  After the Macintosh introduction, Apple returned to 50% GPM for a while but its market share had dropped to about 20%.  Apple then introduced the Mac Classic priced to compete with IBM.  This and the introduction of Windows 95 by Microsoft drove Apple’s GPM% down to 10% along with its market share. As Apple’s market share subsequently declined to 5% shortly after 2001, GPM% became negative.  The iPod and iPhone reversed this corporate trend, bringing the MacBook along with them and resulting in a corporate GPM% of 40% in 2010 and a $999 price for a MacBook that was roughly twice the price of equivalent IBM-compatible PCs.  Even today, Apple PCs sell for nearly double the price of the IBM-compatible PC of “equivalent” capability.

Apple’s differentiation after 2001 came from more than just the products themselves.  Apple built an interdependent ecosystem that made it difficult to switch suppliers if you committed to any part.  The infrastructure included iTunes, Apple stores, Genius Bars and MobileMe/Cloud.  But the best part of any ecosystem is the part that isn’t paid for by the supplier. In Apple’s case, that meant the connectors in cars and hotels, the third-party apps on the iPhone and Mac, the peripheral devices, and many more (Figure 3).

Figure 1.  iPhone differentiated value versus commodity cell phones

End product companies are not the only ones who have achieved differentiation that translates into GPM%.  Even component suppliers can do this (Figure 4). Intel’s 8088 16-bit microprocessor was arguably the worst of its generation.  Clearly superior products were introduced (within a year) by Motorola and Zilog.  Combining “first to market advantage” with some legal protections through extension of copyright law to semiconductor photomasks, Intel was able to create a highly differentiated dynasty of products with high switching costs that today dominate the computer server business.

Figure 2. Apple GPM% and market share

Figure 3.  Building an ecosystem to make switching more difficult for existing users

Figure 4.  Intel component differentiation

 

Can a Commodity Product Be “De-commoditized”?

Before all the suppliers of “commodity” products become depressed, let’s consider the question of “de-commoditization”.  Don’t give up hope.  There are lots of examples.  Consider Figure 5. Water is generally available for $0.0002 per glass.  Yet, in the last few decades, innovative companies have found ways to sell water for $0.75 per glass.  A similar, but less extreme, scenario could be described for coffee.

I was personally involved in one of the more notable cases of de-commoditization in electronics.  In 1977, I was Engineering Manager for Texas Instruments’ (TI) Consumer Products Group.  TI had aggressively reduced the component count of a basic four-function (add, subtract, multiply, divide) calculator from 480 components in 1971 to a single chip in 1977 (Figure 6).

Pretty impressive, don’t you think?  TI must have made a lot of money from those innovations?  Actually, no, they didn’t.  The four-function calculators continuously lost money although the scientific calculators made up for much of the loss.

Figure 5.  De-commoditization of water

The losses became so painful that TI finally resorted to OEMing (selling calculators manufactured by other companies) as shown in Figure 7.

De-commoditization wasn’t easy.  But TI had an example to follow from early history with a product called the “Little Professor” which was designed to teach arithmetic. It had a life of its own.  Unlike other calculators, the sales continued despite recessions and obsolescence.  We learned that parents will pay whatever is required to give their children an advantage in school.

Figure 6.  Innovation reduced component count of electronic calculators from 480 to one component in five years

Armed with this history, the TI Consumer Products Group focused on the education market.  Over the next two decades, they worked with teachers, school boards, educators, course developers and the entire educational ecosystem to develop a program geared to their graphing calculators. Figure 8 shows TI calculators that are both differentiated and commoditized. The TI-89, shown on the left, sells for $150.  I have personally bought six of these.  My two daughters lose them, loan them to friends, break them or require different versions for different classes.  TI probably OEMs them for less than $20 each.

Figure 7.  TI begins “OEMing” calculators made by foreign manufacturers

For TI, a money losing calculator business has now become one of its most profitable businesses.  Figure 9 shows the reported segment profit for TI calculators. In 2007, GPM % for TI calculators had reached 65%, at which point TI stopped reporting this segment.  As a former TI executive, I have concluded that the reason TI stopped breaking out the reporting of this segment is that it became embarrassingly profitable – more so than the semiconductor component businesses of TI.

Figure 8.  Differentiated and commoditized TI calculators

Figure 9. TI’s education focus leads to an Increasingly profitable calculator business

What about semiconductors? Historically, the industry grew with very limited differentiation.  Faster, better germanium transistors were quickly matched by competitors because the original AT&T licensing program created a level playing field for semiconductor patents.  TI gained a two-year advantage with the silicon transistor but that was soon matched as well.  Integrated circuit designs were easily copied and customers had sufficient power to force semiconductor suppliers to have an alternate source of supply for their designs before the customer would “design in” the product.

Over time, semiconductor companies found ways to create differentiation.  The most common type is the differentiation that comes with analog components because they can be differentiated by both the design and the manufacturing process.  As a result, pure analog companies like Analog Devices and Maxim have demonstrated consistently high GPM%.  Most knowledgeable people are surprised to learn that analog components are not the highest consistent GPM% products — Field programmable gate arrays, or FPGAs are.  Like analog components, FPGAs carry high switching costs once they are designed into a product (Figure 10). FPGAs have an additional barrier to switching suppliers that extends across the entire component product line — differences in the way different manufacturers’ FPGAs are programmed creates a barrier for designers to switch suppliers.  In addition, libraries of proven reusable blocks of a design are built up in a company over time and are difficult to re-create.

Figure 10.  FPGAs have consistently provided the highest GPM% in the semiconductor industry

Next highest GPM% among major semiconductor categories, after FPGAs and analog, is the microprocessor.  These can be differentiated by their computer architectures and embedded software microcode that can be copyrighted. Patents in the semiconductor industry are difficult to enforce because most large companies are cross-licensed and, even when a patent lawsuit is successful, the precedents for royalties are small, usually less than 5%, assuming the licensee doesn’t have any patents that can be used as bargaining chips against the licensor.

Intel’s de facto standard 808X microprocessors would probably be commodities today if Intel hadn’t followed a unique path, i.e. enlisting the forces of the U.S. government to extend copyright legislation to the photomasks for semiconductor components in 1984.  The act of copying physical objects that are copyrighted had always been protected before 1982.  If you saw a building you liked, you could build one just like it and incur no liability unless you stole the plans from the architect or owner.  Intel’s “Semiconductor Chip Protection Act” of 1984 prohibited direct physical copying of chips, even though it had been standard practice in the industry until that time. This limited competing 808X microprocessor suppliers to the Intel-licensed source, Advanced Micro Devices (AMD), and companies that utilized Intel cross-licensed companies like TI for manufacturing. Cyrix was one example of a company that circumvented Intel’s barriers by using a licensed manufacturer, TI .  In addition, Intel was careful to keep their pricing near the learning curve so that competitors like AMD could be held to a small market share.

Figure 11.  2009 – 2010 GPM% for major semiconductor component categories

Figure 11 shows the GPM% of major semiconductor product categories.  There is GPM% differentiation within each category due to other factors such as existing market share. Categories with high switching costs, like FPGAs and microprocessors, tend to have one or two suppliers at the high end of GPM% and others below.

Commodity products like memory and discrete devices are more difficult to differentiate partly because their commodity nature is core to the value perceived by customers.  Most customers wouldn’t design in a DRAM that has no “pin compatible” alternate sources.

Increasing Semiconductor Component Differentiation

What can semiconductor companies do to increase their average GPM%?  Figure 12 offers some suggestions.

Figure 12.  Other ways that semiconductor component companies can enhance GPM%

Semiconductor companies have a difficult time differentiating on price, quality of support, sales distribution and many approaches that work in other industries.  In general, even manufacturing process differentiation is difficult to sustain for more than one technology generation.  Design offers more opportunities to differentiate, especially with “system on a chip”, or SoCs, that are sourced by only one supplier.  If they incorporate complex algorithms and copyrightable microcode, so much the better.  Combinations of process and design, as with analog, RF and power devices, is even better.  This benefit accounts for the general movement of companies like TI, NXP and others to an analog-rich portfolio.

Reusable IP blocks are becoming commoditized.  There is still an opportunity, however, to develop proprietary IP blocks, as companies like Qualcomm have done, to facilitate superior performance or time to market.

Finally, the best differentiation is that created and paid for by customers.  ARM is a successful example of a company that built a niche in low power embedded microprocessors for wireless handsets and then expanded to a variety of other applications.  Third parties provide a wide variety of assistance, interfaces to other IP, endorsements, etc.

Another example is the effectiveness of open sourcing of a product that increases the value of a proprietary one.  Adobe did this with Acrobat.  In semiconductors, one of the most impactful moves was from TSMC.  Until the late 1980s, silicon foundries kept their “design rules” secret.  Customers signed non-disclosure agreements just to find out the information needed to evaluate the viability of a particular foundry for the capabilities the designer needed. TSMC management was frustrated by the share of their business that came from designs that were developed using someone else’s design rules, forcing TSMC to tweak their process to match the results provided by the other foundry.  Compass Design Automation, a subsidiary of VLSI Technology, even provided a design library called “Passport”.  It was popular with designers because, if you used the cell libraries in Passport, multiple foundries had a manufacturing flow that would accommodate the design and produce the same results as the simulated ones.  TSMC went one step further by removing secrecy restrictions on their design rules.  Compass found it easier to adopt the TSMC design rules for their library, thus solving TSMC’s problem.  Now all the other foundries had to tweak THEIR processes to match the TSMC results.  Effectively, a large share of the foundry customer base became standardized on TSMC’s design rules and process.

For the future, the biggest differentiation challenge of the semiconductor industry comes with the Internet of Things.  IoT sensors, actuators and controllers are projected to sell in very high volumes at very low prices.  Achieving reasonable GPM% is difficult.  In the world of IoT, the profit goes to the owners of the information collected from the network of sensors and data collection sites rather than to the providers of the IoT components.  As a result, companies like Google, Amazon, automotive OEMs and others are designing their own chips to deploy in information collecting networks.  In these environments, the same company can design and own the IoT sensors and the information collected.  Semiconductor companies with IoT component businesses are trying to figure out how to couple their design and manufacture of the components in a joint venture with those who analyze the data.  This is a difficult sale so it’s likely that we will see continued entry of systems companies into the world of SoC design.

Information and figures in this Chapter are covered in greater detail in a You Tube video entitled “Value From Differentiation” presented at the ARM TechCon in 2011 (below).

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GloFo & TSMC lawsuit- A Surrogate Trade War- Pushing TSMC into China’s open arms?

GloFo & TSMC lawsuit- A Surrogate Trade War- Pushing TSMC into China’s open arms?
by Robert Maire on 08-29-2019 at 10:00 am
Categories: Semiconductor Advisors, Semiconductor Services
2 Comments

Surrogate Wars
Is GloFo using the trade war as an excuse?
Does TSMC get lumped in with China on trade?
Does this alienate TSMC into China’s embrace?

Much like Vietnam and Korea before it, there have been a number of “surrogate” wars between the US and China as well as many other wars between the US and Russia using other surrogates.

Though it may or may not be the intention of the current administration to make the lawsuit between Global Foundries and TSMC a surrogate trade war, it certainly has the right script.  A US based company, Global Foundries, is suing a “China” based (cause thats what China says Taiwan is…) for intellectual IP and patent infringement.  GloFo even has at its technology heart, the once proud, now rusting, old IBM technology base, that back in the day was a technology leader now blown past by TSMC (read that as China). It conjures up the standard “China is killing US industry” image as GloFo has wrapped an American flag around itself.

(We will omit the inconvenient truth that GloFo is setting up shop in China mainland along with TSMC).

A “Twitter Ready” Lawsuit
The lawsuit by GloFo against TSMC seems to be a “twitter ready” set up for someone to come along and hit it out of the park.  The timing is obviously very suspect given the current trade war issues with China and many politicians looking for more excuses and ammunition.

 It paints TSMC (and Taiwan) as the enemy & part of China
The problem we have is that the lawsuit obviously paints TSMC and Taiwan with the same broad paint brush as China.

Since when did TSMC & Taiwan become the enemy of the US and the US industrial base?

Follows in the footsteps of Hong Kong
We had warned in a recent newsletter that we were concerned that Taiwan could become the next Hong Kong as the Chinese could be emboldened by the administrations “abandoning” of Hong Kong by saying “its none of our business because Hong Kong is part of China”.

Could this lawsuit further embolden China towards Taiwan if the US administration distances itself further from Taiwan and views Taiwan as part of the China trade threat against the US heartland?  If the administration takes the GloFo side that would seem to be the case.

Could TSMC run into China’s open arms?
If it looked like the US government were taking sides against TSMC they may not have a choice but to seek refuge.

UMC (TSMC’s competitor) is already deep within China’s embrace as they clearly had a hand in stealing some of Micron’s IP from Taiwan to mainland China in the case of Jinhua.

TSMC obviously is building up fabs in China and could decide to move more operations there or bring more technology thus accelerating “made in China 2025.

It depends a lot on how the current US administration plays this and how much they take sides.

GloFo reaching out from the grave
Given that Global Foundries gave up the race to be a technology leader in the semiconductor industry a year ago when it abandoned advanced technology, they now don’t have a lot to lose by starting a war against TSMC related to leading edge process. Theres not a whole lot TSMC can do to shut down GloFo’s advanced technology through legal means as GloFo already shut it down themselves.  TSMC on the other hand has a lot to lose as the technology leader with the biggest customers.

GloFo clearly lost the technology & production war with TSMC in the market and this may be a bit of a revenge or sour grapes or both….except that the real reason is money….

Squeezing money out of a dead fab
It has long been rumored that Abu Dhabi is looking to unload GloFo and we have seen parts already sold off. Recently the mask operations were sold off and some ASML EUV scanners have already been sold off as part of the leading edge equipment yard sale.

It would seem very logical that GloFo would seek to monetize any and all assets to maximize a sale value or cash return on their way underwater investment.  TSMC could decide the risk is too big  (especially if the US government backs GloFo) and just pay a royalty to GloFo. In fact the current administration would probably trumpet a “China based” company paying a royalty to a “wronged” US company. So its not too far out of the question

Stuck in a “Catch 22”
We see the current situation as a bit of a “catch 22”. If the US sides with GloFo, it alienates TSMC and Taiwan whom have been great partners and the key enablers of US technology. If it sides with TSMC, it will be seen as against US based companies and for Chinese IP theft. If it doesn’t take a position it will be seen as ignoring a major trade and IP theft issue with China….the issue that has been the hallmark of the administration.

Its a bad situation and GloFo may have put the administration in a box at a sensitive time.

Summary:
While we certainly have been very vocal about US and China trade and IP issues, the GloFo and TSMC lawsuit has absolutely zero to do with them and is not part of the overall larger trade & IP issue even though GloFo would like to make it so.

The semiconductor industry is a virtual landmine field of patents that make it almost impossible to manufacture a leading edge device without leaning on someone else’s IP or patents.  TSMC is quoted as having 37,000 patents and GloFo got 16,000 from IBM.

Companies collect patents like nations collect nuclear weapons in a game of “mutually assured destruction” in which one doesn’t sue the other as they are afraid of the response. GloFo is no longer in the game so they don’t care, they are already dead.

Its a bad precedent to set and the US is going to have to walk a carefully choreographed tightrope to avoid a mess.

The stocks
All this just adds to the general “overhang” on the stocks related to China trade and adds another variable and another news point to move the stocks.

Other companies like Apple, AMD, Nvidia and other customers and suppliers could get sucked into the vortex as well. GloFo doesn’t care as they aren’t customers and GloFo is private anyway.

It will be a long time to resolve but we would be more concerned about either a near term escalation or involvement of other companies that get hit by collateral damage.

Related SemiWiki Forum Discussion

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Lint for Implementation

Lint for Implementation
by Bernard Murphy on 08-29-2019 at 6:00 am
Categories: Cadence, EDA

Conformal Litmus

When I was at Atrenta, we took advantage of opportunities to expand our static tool (aka linting) first to clock domain crossing (CDC) analysis and DFT compatibility and later to static analysis of timing constraints, all of which have importance in implementation. CDC is commonly thought of as an RTL-centric analysis, however, late-stage clocking refinements due to low-power implementation also require runs at the gate-level. These kinds of analyses are in effect a lint for implementation, a pre-check to ensure that the design and timing constraints are consistent and clean according to a variety of requirements. I’m encouraged to see that this mindset is becoming even more common, as evidenced in Cadence’s recent release of their Conformal Litmus tool.

The need for CDC checking should (I hope) be beyond debate. Virtually every SoC design hosts multiple clock domains, for different standard I/O interfaces (PCIe, USB, etc) and for different on-chip functions (CPU cluster, GPU, DMA, AI accelerators, etc). Data or control passing between these domains can drop bits/words or run into lockups which may only be fixable through a system reset. Neither static timing analysis (STA) nor simulation can reliably find all possible problems and design review is not up to comprehensive checks on these massive devices. This is serious; missing CDC problems have led (and continue to lead) to more than a few embarrassing field failures.

The need for constraint checking may not be so obvious to many of you. After all, you’re going to do all of this properly during STA in implementation, right? True, but implementation cycles are not very quick. There’s no way around this when you’re dealing with key implementation choices, say adding pipelining or fiddling with your CTS. But there’s a very obvious way to minimize iterations caused basic inconsistencies in constraints – flush them out early, the same way you flush out basic errors in RTL, by linting the constraints.

You might be surprised to hear that constraints need this kind of checking. You shouldn’t be. They’re IP data, no more immune from errors than any other IP data. The IP used in an SoC comes from a bunch of different sources, so constraints are developed by different people with differing expectations and perhaps differing quality control. At Atrenta we had a number of IP-provider customers who had their customers advise they needed to do more checking. Even if the individual IP constraints are correct by some measure, when you put them together in an SoC with constraints for the top-level, it’s not uncommon to find cross-hierarchy inconsistencies.

Since mistakes and misunderstandings happen, you have to plan for checking across the full design, and this is much faster to do at RTL. Fast is good, but you also have to be able to trust the checking will fully correlate with your later STA runs. This is where it got a little hairy for us at Atrenta. We didn’t build production synthesis tools or signoff timers so we had to rely on customer feedback on what we might be missing. We did pretty well but not to the point you could consider our checks signoff-grade for pre-implementation. To do that you have to own the timer certainly and ideally the synthesis tool as well.

Conformal Litmus is integrated with Tempus (the Cadence STA solution) using the same interpretation of the design, timing and constraints you’ll find in that timer; therefore, consistency throughout the flow is verified with the same signoff timer you’ll be using implementation.

Since the design will certainly evolve through the flow, and generally constraints do also, consistency checks are necessary to validate such changes. Does my RTL plus RTL-constraints match my netlist plus netlist-constraints (at a consistency level), for example? We had some of this capability at Atrenta, but we didn’t have a netlist equivalency checker, where Cadence obviously has Conformal. Litmus supports all required combinations of consistency checks between different steps.

I asked Kam Kittrell (senior product management group director at Cadence) about false-path and multicycle path checking (I knew you would have this question too). Litmus doesn’t do this, although it does do consistency checking for path exceptions across the flow—which makes sense. I don’t know anyone who really proves FPs and MCPs well, despite many claims. And these kinds of checks would definitely not work at the full-chip level.

CDC checking is integrated in all of this. Litmus checks for metastability, glitch potential and reconvergence possibilities (reconverging separately synchronized signals). The CDC checks are structural, missing some of the formal possibilities, but since this is intended for full-chip checking, that’s not surprising. Again, ability to run these checks at each stage is important since domain crossings can be introduced or changed during low-power implementation.

You can learn more about what Cadence provides in Conformal Litmus, including how they manage for low noise reporting, HERE.

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Webinar: VLSI Design Methodology Development (new text)

Webinar: VLSI Design Methodology Development (new text)
by Tom Dillinger on 08-28-2019 at 10:00 am
Categories: Events
1 Comment

Daniel Nenni was gracious enough to encourage me to conduct a brief webinar describing a new reference text, recently published by Prentice-Hall, part of the Semiwiki Webinar Series.

VLSI DESIGN Methodology Development Webiner Replay

Background

I was motivated to write the text to provide college students with a broad background on SoC design.  My experience with hiring new college microelectronics grads was that they typically received a good introduction to CMOS logic circuits, although likely using a somewhat dated text.  Yet, the students often have not been exposed to a full SoC design and analysis methodology.

Specifically, there have been recent methodology enhancements driven by technology node evolution that students would benefit from including in their curriculum:

  • hard and soft IP integration
  • voltage domain and power state definitions with a power format file
  • multipatterning lithography, other lithography restrictions (unidirectional wires, forbidden pitches, via/contact size options)
  • characteristics of FinFET-based circuit design
  • electrical analysis with layout-dependent effects, (global and local) process variation

The goal was to provide students with an up-to-date SoC design perspective.   Examples of figures from the text are appended below.

Layout Dependent Effects in device models

Multipatterning decomposition and “odd cycle DRC check”

FinFET layout example

The industry experts that reviewed the text for Prentice-Hall indicated that professional engineers would likely find material of interest.  They asked that the text also include some practical subjects and examples.  As a result, there are discussions on topics such as:

  • managing ECO’s
  • executing silicon bring-up and debug
  • SoC project management

A few cases of SoC project setbacks are provided, as well.

The webinar will briefly review the organization and context of the text, highlighting some of the unique topics associated with leading process nodes.  A general Q&A session will follow that introduction.

Please feel free to register for the webinar, using the link on the left side of the semiwiki.com home page.

-chipguy

PS.  There is also a website where readers can provide comments, and identify (hopefully few) errata:  http://www.vlsidesignmethodology.com .

Any feedback on the text would definitely be most welcome.  Thanks in advance!

VLSI DESIGN Methodology Development Webiner Replay

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IEDM 2019 to Highlight Innovative Devices for an Era of Connected Intelligence

IEDM 2019 to Highlight Innovative Devices for an Era of Connected Intelligence
by Scotten Jones on 08-28-2019 at 6:00 am
Categories: Events

The IEEE International Electron Devices Meeting is in my opinion the leading technology conference to understand the current state-of-the-art in semiconductor process technology. Held each year in early December in San Francisco it is a must attend conference for anyone following technology development. The following is a press release about this year’s conference:

2019 IEEE International Electron Devices Meeting to Highlight Innovative Devices for an Era of Connected Intelligence

  • A focus on devices for new and More-than-Moore applications
  • An extensive offering of tutorials, short courses, focus sessions and panels, plus poster sessions from affiliated groups
  • A supplier exhibition will be held in conjunction with the technical program
  • Industry and scientific leaders will talk about their personal experiences in the context of career growth.

SAN FRANCISCO, CA (August 20, 2019) –The upcoming 65th annual IEEE International Electron Devices Meeting (IEDM), to be held December 7-11, 2019 at the Hilton San Francisco Union Square hotel, will once again feature the latest and most important research taking place in semiconductors and other electron devices, but with a sharper focus this year on devices intended to support diverse new applications.

Under the theme “Innovative Devices for an Era of Connected Intelligence,” IEDM 2019 will turn a brighter spotlight on the processors, memories, 3D architectures, power devices, quantum computing concepts and other technologies needed for new applications. These applications include artificial intelligence, mmWave/5G communications, automotive electronics, Internet of Things infrastructure and systems, and others. Talks on these topics will complement presentations describing breakthroughs in CMOS scaling, which remains an area of major importance in the semiconductor industry.

At IEDM each year, the world’s best scientists and engineers in the field of microelectronics gather to participate in a technical program consisting of more than 220 presentations, along with a variety of panels, focus sessions, tutorials, Short Courses, a supplier exhibit, IEEE/EDS award presentations and other events highlighting leading work in more areas of the field than any other conference.

This year IEDM once again will feature special Focus Sessions of invited papers on some of today’s most important areas of research.[1] This year’s Focus Session topics are AI technologies; the human-machine interface; quantum computing infrastructure; and reliability for circuits and systems.

“IEDM 2019 will feature state-of-the-art results from major semiconductor companies, universities and other research institutions around the globe, continuing the conference’s tradition of being the premier venue for the presentation of the highest quality research,” said Rihito Kuroda, IEDM 2019 Publicity Chair and Associate Professor at Tohoku University. “While CMOS scaling remains very important and IEDM once again will feature the latest work in that area, many diverse new, fast-growing applications demand different types of devices. Therefore, we have reorganized the technical subcommittee structure of IEDM to better align the conference with the innovative semiconductor concepts and technologies required.”

“The heart of the IEDM conference is the technical program,” said Dina Triyoso, IEDM 2019 Publicity Vice Chair and Technologist at TEL Technology Center America, “but the conference is also known for the many opportunities it affords attendees to interact directly with the world’s technology leaders.”

Here are details of the 2019 IEDM:

90-Minute Tutorials – Saturday, Dec. 7

The 90-minute Saturday tutorial sessions on emerging technologies have become a hugely popular part of IEDM. They are presented by experts in the fields, the goal being to bridge the gap between textbook-level knowledge and leading-edge current research. The topics for 2019 are:

  • Oxide Semiconductors and TFTs: What is Different from Conventional Semiconductors?Hideo Hosono, Tokyo Institute of Technology
  • Cryogenic MOSFET Modeling, Christian Enz, EPFL
  • FEFE Memory (FRAM, FTJ and NCFETs), Johannes Mueller, GLOBALFOUNDRIES
  • In-Memory Computing for AI, Abu Sebastian, IBM
  • 3D-Monolithic Integration, Perrine Batude, Leti
  • Magnetic Sensors, Keith Green, TI

Short Courses – Sunday, Dec. 8

Early registration for the full-day Sunday Short Courses is recommended, as they are often sold out. They offer the opportunity to learn about important areas and developments, and to network with global experts.

Technology Scaling in the EUV Era and Beyond, organized by Wook-Hyun Kwon, Samsung

  • Future of Computing: From Core to Edge Computing, Karim Arabi, Qualcomm
  • Logic Transistor Options for 3nm Node and Beyond, Jin Cai, TSMC
  • Advanced Processes for Technology Scaling Beyond 3nm, HooChur Kim, Samsung
  • Design Technology Co-Optimization for Advanced Scaling, Lars Liebmann, TEL
  • Novel Interconnect Techniques for CMOS Technologies in the EUV Era, Chris Wilson, IMEC
  • Low-Power Device Solutions for Ultra-Low-Power Computing, Arokia Nathan, Univ. of Cambridge

Technologies for Memory-Centric Computing, organized by Ali Keshavarzi, Stanford University

  • Emerging Memories on Advanced Technology Nodes, Oleg Golonzka, Intel
  • Advanced DRAM, 3D-stacked SDRAM and HBM Technologies, Kyomin Sohn, Samsung
  • Novel 3D NAND, Lower Latency NAND and Persistent Memory Technologies, Jian Chen, Western Digital
  • Emerging Memory and AI Technologies, Edith Beigne, Facebook
  • Requirements of Advanced Memory Devices, Alessandro Calderoni, Micron Technology
  • Advanced Memory-Centric Computing: A Device, Circuit and System Perspective, Arijit Raychowdhury, Georgia Tech.

Luncheon – Tuesday, Dec. 11

IEDM will have a career-focused luncheon this year featuring industry and scientific leaders talking about their personal experiences in the context of career growth. It will be moderated by Jungwoo Joh of Texas Instruments, and this year’s speakers will be Ramune Nagisetty from Intel and Linda Sommerville from Micron.

Evening Panel Session – Tuesday evening, Dec. 11

IEDM 2019 will offer attendees an evening session where experts will give their views on important industry topics in a fun, engaging format. Audience participation is encouraged to foster an open and vigorous exchange of ideas. The title of this year’s evening panel is “Rest in Peace Moore’s Law, Long Live Artificial Intelligence,” organized by Vijay Narayanan, IBM Fellow and Manager, Materials Research.

Vendor Exhibition/Poster Sessions

  • A vendor exhibition will be held once again.
  • This year two poster sessions will be held, one on MRAM technology organized by the IEEE Magnetics Society, the other a student research showcase hosted by the Semiconductor Research Corporation.

Further information about IEDM

For registration and other information, visit www.ieee-iedm.org.

Follow IEDM via social media

 About IEEE & EDS
IEEE is the world’s largest technical professional organization dedicated to advancing technology for the benefit of humanity. Through its highly cited publications, conferences, technology standards, and professional and educational activities, IEEE is the trusted voice in a wide variety of areas ranging from aerospace systems, computers, and telecommunications to biomedical engineering, electric power, and consumer electronics. Learn more at http://www.ieee.org.

The IEEE Electron Devices Society is dedicated to promoting excellence in the field of electron devices, and sponsors the IEDM.  Learn more at https://eds.ieee.org/.

[1] The Focus Sessions will be detailed in a separate news release.

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Tensilica DNA 100 Brings the AI Inference Solution for Level 2 ADAS ECUs and Level 4 Autonomous Driving

Tensilica DNA 100 Brings the AI Inference Solution for Level 2 ADAS ECUs and Level 4 Autonomous Driving
by Randy Smith on 08-27-2019 at 10:00 am
Categories: Cadence, Events, IP

I recently wrote about Tensilica’s HiFi DSPs which played a significant role at Cadence’s Automotive Design Summit which was held on the Cadence San Jose campus at the end of July. That article focused on infotainment while briefly touching on Advanced Driver-Assistance Systems (ADAS). ADAS is NOT synonymous with autopilot. Level 2 automotive ADAS features help the driver to drive more safely and also complement additional ADAS safety features in the current fleets of deployed cars, buses, trucks. The technologies used in ADAS are merely one step along the way to driverless or full self-driving (FSD) vehicles if viewed as a continuum. We define the  progression to driverless or FSD vehicles like this:

Level 0: No automation
Level 1: Driver assistance
Level 2: Partial automation
Level 3: Conditional automation
Level 4: High automation
Level 5: Full automation

The most advanced ADAS features available in production cars today are Level 2/3. There are some limited taxi-like early pilot test services available now with Level 4 with limited range and use-case testing, subject to NHTSA guidelines. Cadence is doing a great job of making the EDA tools and IP available to build and enable these types of safe vehicles. But before we get into those details, I wanted to point out two important statements that stuck in my mind from the event: (1) security is more important than safety; and (2) several legal issues regarding autonomous vehicles have yet to be addressed.

The explanation for the higher priority security over safety is simple. If someone with evil thoughts can take over control of your vehicle, you are no longer safe. If someone else has control of your vehicle, they can determine where it goes, or they can crash it. Or they can be very annoying and blast music at full volume while leaving your wipers running continuously. If they can control one car, why not millions all at once? Unsecure autonomous driving systems would be unsafe and likely deadly. We must put security first, though safety is also critical. The crucial requirement of security is why Cadence’s relationship with Green Hills is so important. It will take software and hardware working together to implement the needed levels of security in autonomous FSD vehicles.

Autonomous vehicles are expected to reduce traffic fatalities dramatically. However, not all fatalities will be avoided. According to the World Health Organization (WHO), there were 1.25 million road traffic deaths globally in 2013. I think it would be fantastic if by 2032, through the increasing use of autonomous vehicles, we can cut that number in half. But that still means there would be over 600,000 traffic fatalities. Would we blame the car manufacturers? Would they be sued over every collision? Let’s face it, even if they reduce the number of traffic fatalities by 90%, when people get injured, they still want to blame someone. How will this work?

Sorry for the detour, but these things are important. Tensilica is enabling the drive from Level 2 ADAS up to Level 5 FSD by supplying a crucial piece of the autonomous driving system IP, artificial intelligence (AI). The Tensilica DNA 100 processor IP can handle the demands of the latest features in ADAS such as neural networks based emotions and Facial Action Coding Systems (FACS), gesture tracking, and occlusion detection. The number of new AI features in the pipeline for our cars is staggering. Beyond all that, the Level 5 systems will have many AI processes monitoring a huge hub of sensors and communication networks/protocols while also providing navigation, mapping, and trajectory planning with a focus on safety. AI neural networks will be key to all of this, and Tensilica will be a key IP supplier of AI-based systems.

I came away from the Cadence Automotive Summit impressed with Cadence’s overall grasp of the needs of the designers of autonomous driving systems. They seemed to have expertise in every field, and partners where the required expertise is well outside the Cadence domain. My thanks to Pradeep Bardia, Cadence Product Marketing Group Director for AI, for his presentation on “Automotive – AI Processor Solutions.” And thanks also to Robert Schweiger, Cadence’s Director of Automotive Solutions, for the timely and insightful event.

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Build More and Better Tests Faster

Build More and Better Tests Faster
by Bernard Murphy on 08-27-2019 at 5:00 am
Categories: Breker Verification Systems, EDA, Security
3 Comments

Breker has been in the system test synthesis game for 12 years, starting long before there was a PSS standard. Which means they probably have this figured out better than most, quite simply because they’ve seen it all and done it all. Breker is heavily involved in and aligned with the standard of course but it shouldn’t be surprising that they continue to leverage their experience in extensions beyond the standard. This is evident for example in their support for path constraints to prevent or limit creation of certain paths and to bias towards other paths during test synthesis.

The value of path constraints becomes apparent when you look at the coverage view the Breker tools generate following simulation/emulation/ etc. In the image a red action was not tested, orange was tested once, green multiple times and blue a lot of times. You could imagine running multiple times, randomizing each time, to see if you could hit all the actions with sufficient frequency. You really want an equivalent to constrained random, but it needs to be more than simply randomizing fields (what PSS currently provides). Path constraints provide a better way for you to steer randomization to improve hit frequency for more comprehensive coverage along paths that are meaningful to real system usage.

Eileen Honess, tech specialist at Breker, recently delivered a SemiWiki-hosted webinar on the objective of these flows, together with a demo. I can’t blog demos so instead I’ll tell you what really stood out for me from this session. What Breker is doing is all about accelerating high-value test generation. Whether or not you are enamored with PSS, you certainly get the value of generating 10k high-value tests, getting you to 95% coverage (because you can better control how to get to high coverage), in 2 weeks. This is versus manually creating 500 tests in 2.5 months which only get you to 87% coverage (stats based on real customer case).

Along similar lines, Breker support accelerated testing through pre-packaged apps. The app concept was most notably introduced by Jasper as a method to pre-package formal verification for dedicated use-models. Breker have built on that idea in four domains – cache coherency checking, power verification, security and an ARMv8 app focused on typical processor test issues (there is a rumor of a RISC-V app on the horizon also). I’ll touch on a couple of these. For cache coherency checking, you’re probably heard that formal methods are extensively used. These play an important role in verifying control logic sequencing but that alone isn’t enough. Directed/randomized testing also plays a big role in verifying inter-operation of caches and the bus together with the controller. The Breker approach is a perfect application for this class of testing, providing a mechanism to capture the potential graph of actions, then generate randomized tests over that graph. This has to be substantially easier than building such tests from scratch in UVM. It should also be much easier to review how effectively you are covering the problem.

Verifying power management is another area where an app can accelerate test development and is also a natural for a PSS approach. After all, the power state-machine is – a state machine. It’s a graph defining the various possible states and what drives transitions between those states. You can build that model in UVM but why not start with a model already built from the UPF power state table?

Evidence that Breker are enjoying success with approach is apparent in their customer list, including companies like Broadcom, Altera, IBM, Huawei among others, including 8 out of the top 10 semis I’m told. They’re also proven with pretty much every tool I know of in the functional verification flow:

    • Simulation: Questa, VCS and Xcelium
    • Emulation: Palladium, Veloce and ZeBu
    • FPGA prototyping: HAPS, Virtualizer and custom FPGA boards (curiously no mention of Protium, maybe an oversight)
    • Virtual prototyping: Imperas and QEMU
    • Debuggers: Verdi naturally plus the other standard platforms
    • VIP: Synopsys, Cadence and Avery

So if you’re into PSS, you should check these guys out because they have a pretty advanced solution. If you’re a PSS sceptic, you should check them out because you can build more tests faster to get to higher coverage. Just ignore that it’s PSS-based. You can watch the webinar HERE for more details.

Also Read

Taking the Pain out of UVM

WEBINAR: Eliminating Hybrid Verification Barriers Through Test Suite Synthesis

Breker on PSS and UVM

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Achieving Functional Safety through a Certified Flow

Achieving Functional Safety through a Certified Flow
by Daniel Payne on 08-26-2019 at 10:00 am
Categories: EDA, Perforce

Methodics: Tool and process certification

Functional safety (FuSa) is a big deal, especially when driving a car. My beloved 1998 Acura RL recently exhibited a strange behavior at 239K miles, after making a turn the steering wheel would stay tilted in the direction of the last turn instead of straightening out. The auto mechanic pinpointed the failure to the ball joints, so I ended up selling the vehicle to someone who was willing to make the repairs. Today our cars are filled with complex electronics, semiconductor IP, firmware, software, sensors, actuators and a variety of propulsion systems: internal combustion engines, hybrids, and electric motors. How should we meet functional safety requirements for industries like automotive, medical and life-critical domains?

Complying with functional safety requirements is an emerging field, and in the automotive industry we see the quest for Advanced Driver Assistance Systems (ADAS) inch towards autonomous vehicles. A recent White Paper written by Vadim Iofis of Methodics brought me up to speed on the challenges, and their approach of using an IP-centric flow to reach compliance by tracing down to the hardware and software component levels.

If each component in a system is designed and developed with certified tools and processes, then it becomes functional safety compliant. Here are examples of tools that are certified for FuSa compliance:

Your functional safety team ensures that each new version of a tool is certified before it’s used in a FuSa-compliant design and development process. Even the design and development process becomes FuSa compliant, adopting rules for approved tools and listing out the steps on verifying components, so that requirements and specifications are met. Both tools and process are version controlled. Wokflows are described using the Business Process Model and Notation (BPMN) 2.0 standard.

Even when your team has defined FuSa-compliant tools, processes and workflows, there’s still the issue of tracing the certifications down to each hardware block and software component. Where does this traceability come from?

Methodics has an approach to this traceability concern, and that is by defining each project as an IP hierarchy, where IP can be either a hardware design block or a software component. The Methodics Percipient tool provides IP management, versioning IP, and linking an IP object to hardware or software. Each IP also has metadata to enable traceability of certificates, process documentation and workflows.

Project Example

OK, time to get specific and look at a typical ADAS application for an Automatic Collision Avoidance System (ACAS), breaking up the project into hardware and software components as shown below.

Shown in Yellow are Containers, a way to use hierarchy with groupings of other IP blocks. The Green blocks represent hardware blocks, Blue blocks are for software components, and finally the Purple blocks are the FuSa artifacts for each component to certify that the design and development process are meeting your team’s compliance standards.

The Sensor Package on the left-hand side has sensors, hardware and FuSa artifacts (tool certifications, Design Workflow Model using BPMN 2.0 diagram). The ACA Module on the right-hand side is all software components and FuSa artifacts, and you could use Git or Perforce as a code repository.

Using the Percipient tool it only takes a few steps to create the Sensor Package hierarchy.

You can define using hierarchy for both hardware blocks and artifacts. Each artifact has certification IPs attached, and in this case it was from Word documents. Your team can update each new certification version, add new project components and certify each component.

Summary

It’s much easier to reach FuSa compliance in a system design by using an automated approach for hierarchy and traceability like that found in the Percipient tool from Methodics. Both hardware and software components are linked with their FuSa artifacts as proof of compliance. The functional safety manager on your team can now inspect the version history and know which releases belong to which tool certification, even see when and where anything was changed.

Why use manual, error-prone methods when a vendor like Methodics has helped automate so much of the FuSa process. Request the full 11 page White Paper here.

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