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NATO’s Collective Defense for Cyber Attack Remains Fragile

NATO’s Collective Defense for Cyber Attack Remains Fragile
by Matthew Rosenquist on 09-08-2019 at 3:00 pm

The Secretary-General of NATO, Jens Stoltenberg, stated all 29 member countries would respond to a serious cyberattack against any of the nations in the coalition. The pressing question is will NATO work together with combined forces when one of the members is attacked in an asymmetrical manner with digital technology?

When it comes to cyberattacks, there are many grey-zones that could be manipulated in ever-increasing escalations of warfare. NATO’s Article 5 in the founding charter is known as the “collective defence” commitment which states that an attack on one shall be considered an attack on all. Historically, it has a high threshold. The first time the criteria was met was the 9/11 terrorist attacks of 2001 against the United States.

There is a lot of ambiguity in the shadows of bits and bytes. Does shutting down the banking system or mercantile logistics count as an Article 5 attack? Would significant and prolonged communications and internet disruption count? What if the power was shut off by another nation-state and it caused harm to people? How about disrupting the transportation networks or other critical infrastructure? Such attacks can be localized or nationwide, can cause annoyances or lives to be lost, and could undermine the trust and control of a representative government. There are currently no thresholds of what should be considered to reach the level of an ‘attack’ by another nation.

Identifying the aggressor is another significant problem. The requirements to determine attribution or accountability for the source of any digital attack is highly subjective. It is easy to attribute the origin of tanks, planes, ships, and advancing soldiers to another country. Tracking malicious packets, origins of destructive code, and owners of crypto accounts is not simple. In the electronic world, it is easy to mislead, masquerade, conceal, or implicate others.  The question becomes if an attack was merely criminals or if it was sponsored/coordinated by the government of another nation-state, which is extremely difficult.

All the variables and hidden truths must be uncovered before discussion about equitable response options can be explored. The first fundamental order-of-business will be to determine if collective reactions are limited to the digital domain or if physical attacks can also be part of the joint reaction.

The first fundamental order-of-business in which NATO needs to determine is if the collective reactions are only limited to the digital domain or if physical attacks are permitted. This decision must be clearly understood as it may have even greater ramifications if it leads to an escalation of conventional or nuclear warfare.

Presently there are too many unanswered questions, unknown factors, and doubt. This results in an ineffective policy position.

It is time for NATO to codify the criteria, validation requirements, and allowable responses. Only then can cross-nation training and coordination begin in earnest. There is so much to be done. Until then, Article 5 for cyber attacks is just an idle threat of solidarity. It will take tremendous teamwork to make this a clear and effective deterrent for the NATO coalition.

Matthew Rosenquist, Cybersecurity Strategist -Former Intel Corp, LinkedIn Top10 TechVoices, 180K+ followers, Keynote Speaker, Board Advisor


Chapter Nine – Specialization Inhibits System Level Optimization

Chapter Nine – Specialization Inhibits System Level Optimization
by Wally Rhines on 09-06-2019 at 6:00 am

Solving critical customer problems sometimes isn’t enough.  One of my most interesting experiences came during the development and rollout of a product that was designed to optimize integration of hardware and embedded software.  In this case, the product performed exactly as planned but the plan ignored the organizational complexities that come with specialization of skills in different divisions of a large company.

The product, called ASAP (not a great name but that wasn’t the reason it failed), analyzed a customer’s design at the RTL functional level, along with the embedded software.  It determined where the bottlenecks existed for optimum performance or power of the system.  We found an ideal customer who was designing a portable consumer product that was dissipating 8.5 Watts and wasn’t viable with the required size of batteries. Three engineers had worked for a year trying to reduce the power and had modified the design to dissipate only 6.5 watts, still far from the required 4.5 watts. We analyzed the customer’s design and, within a few hours, generated changes that reduced the power to 4.1 watts, well below the 4.5 watts goal of the customer.  This was done by identifying bottlenecks and automatically synthesizing hardware to substitute for functions that were inefficiently executing in software on an embedded CPU (Figure 1).  The customer was ecstatic about the result and we expected a major sale.

Figure 1 – Automatic analysis and synthesis to achieve reduced power

When we didn’t receive an order, we investigated.  The problem, it turned out, was an internal disagreement.  While the customer engineers agreed that they badly needed our product, they couldn’t agree which group, hardware or software design, would be responsible for using it.  The hardware engineers were adamant that “no software engineer is going to generate hardware in my chip design” and the software engineers were adamant that “no hardware engineer is going to change a single line of my software”.  Amazingly, the disagreement was so strong that they decided not to adopt our product and, instead, to kill the development of their own very promising product.

You might think that this was an extreme example but I’m increasingly convinced that it wasn’t. We experienced the same thing every time we developed products that crossed domains of expertise, from analog to digital, from mechanical to electrical, from software to hardware, from design to manufacturing, etc.  Software tools that appealed to one domain were not accepted by the other domain. (Figures 2 and 3)

Figure 2.  Differences in the way specialized groups do their work make it difficult to provide tools that cross domain boundaries

Figure 3.  Differing standards, metrics of performance, modes of communication and other differences prevent system level optimization

This is a phenomenon that appears repeatedly, especially in large organizations.  There are, however, ways that system level optimization can be achieved.  Some of these are listed in Figure 4. One of the most apparent examples of the evolution from problematic partitions to a successful organization structure was the change in the customer/supplier relationship that evolved with the advent of silicon foundries in the semiconductor industry over the last thirty years. When most semiconductor companies were vertically integrated, the tradeoffs of every new process technology led to major feuds between the design and the manufacturing engineers.  I know this because I had to referee the arguments many times.  A new generation of product required the most aggressive feature sizes possible while manufacturing yield and throughput favored the least aggressive.  A compromise had to be made and it usually was influenced more by politics than by engineering.  With the emergence of silicon foundries, the problem went away.  Now there were suppliers whose success depended upon providing the most aggressive design rules possible in a cost-effective manufacturing environment.  No more politics.  Just an insightful analysis of the manufacturing and design tradeoffs.

Another approach to solving the specialization problem is to form a startup company (Figures 4 & 5).  In a typical early stage startup, partitions of specialization have not yet formed, so the hardware engineer also frequently writes some of the embedded software, or is at least heavily involved in both.  In addition, startups typically have a key technical expert who will be respected by the potential customers’ most valuable development engineers.  The two of them can get together and exchange ideas for the ideal product because the startup engineer is not constrained by finding the solution in only one domain, e.g. in software or hardware.

Assimilating the task of one group into another also removes artificial partitions. This assumes that the new group truly integrates the responsibilities. It could mean making a group leader at a low level responsible for an integrated solution that involves both hardware and software, for example.

Figure 4.  Ways to overcome the barriers of organizational partitions

Figure 5. Removing the interfaces between customer and supplier

Another approach is to move the design to a higher level of abstraction so that tradeoffs can be made among differing specialties, e.g hardware/software, mechanical/electrical, etc. If the abstraction level is high enough, then everyone can speak the same language (Figure 6).

Figure 6.  Abstraction temporarily solves optimization challenges

This works for a while but very quickly, the addition of detail into the design causes a split among specialties and the optimization effort is reduced or ceases entirely. In some industries, a new abstraction layer can be created at a lower level to overcome this problem.  SysML is one example.  AUTOSAR, for the automotive industry, is another.

Another solution is to conduct multi-physics simulation of designs to see the impact of tradeoffs in different domains (Figure 7). Even with this type of simulation data, it’s frequently difficult to determine which design domain should make changes to improve system level performance. As a minimum, however, it provides data for a rational discussion and takes some of the emotion out of the decisions.

Figure 7.  Multi-physics simulation

While these approaches offer potential, one must wonder whether there are any solutions that are universally applicable?  One overarching approach comes from the way a company handles its data management. For years, company managements hoped for the universal workstation that could be used by the many different disciplines— mechanical, electrical, software, etc.  That is not likely to happen.  Engineers need their own ways of working with design and manufacturing data and they are not going to change, nor would it be advisable to do so.  Efficiency in one domain requires different tools and methods of analyzing data that may not be efficient in another domain.

Despite this need for separation of development functions, engineers still need information from other domains to do their jobs.  A systems company needs a centralized database from which groups in different areas of the company can download and upload data for their own work and to access information from other domains.  A good example is the engineer who is developing wiring for a plane or car. Electrical design of the wiring harness requires detailed electrical simulation, analysis of potential sneak paths and optimization of “take up” alternatives of options in the vehicle so that the basic wiring cost is minimized while the wiring harness can be customized for a multiplicity of option combinations in a vehicle.  At the same time, the wiring approach will change to meet the three-dimensional characteristics of the mechanical design of the vehicle.  How does the electrical designer obtain the data needed to determine if a wire bundle will fit through a hole in the frame of the car?  Or how does the designer know the wire lengths in three dimensions? Does the designer import the mechanical database?  Impractical and probably impossible.  An extract of estimated wire tracks and lengths must be exported to the mechanical design environment and then simulated with mechanical models and tools. Similarly, subsets of system design data must be extracted from one design discipline to another throughout the design process evolution.

Figure 8. In an enterprise data base, unique data structures are needed for each type of discipline

Over many years, I have had the opportunity to work with teams to develop and modify products to make them usable by developers in different domains of expertise.  Some of the lessons learned from this experience are illustrated here.

First, it’s important to provide unique data structures and dataases for each discipline. Mentor’s experience with Version 8.0 of our software drove this one home.  Forcing all the users to format their data in a fixed set of predetermined formats creates an inflexible system that doesn’t benefit anyone but the database vendor.  The database needs to be open and flexible.  Beyond Mentor’s own disastrous experience with the fixed data formats of the Falcon 8.0 database, we were later forced to support our Capital electrical architecture software on a Catia set of formats that suffered the same problem as Falcon.  Performance would have been hopelessly compromised, changes to database structures would require a major regeneration and verification of the database software and our product would have been vulnerable to knockoff by the database owner.  Instead, we created a digital flow for our data outside the Catia database. This approach requires working with data base vendors who favor openness.  This has always been a fundamental priority for Siemens Teamcenter and federated data base approaches of other companies but not necessarily for all database providers. Openness was a key compatibility philosophy for the merger of Siemens with Mentor Graphics that made the union successful.

Figure 9.  Don’t burden one discipline with another discipline’s detailed information

As mentioned earlier, there are still many people who believe that disparate design disciplines in a company should all use the same workstations, the same user interface, the same data structures, etc.  This philosophy is driven by the idea that it is good to have a single design and verification environment that transcends the differences in the enterprise. Engineers can then move from group to group with minimal retraining and design information is more easily shared.   Despite support for this concept among the managements of many companies, it rarely, if ever, happens.   Burdening an electrical designer with the overhead of the mechanical, manufacturing, thermal, etc. detailed design information doesn’t seem to work.  The trick is to be able to access the pieces of data from another domain that are needed to do your job in your domain.  Even better is an architecture that lets you export abstractions of your design to another domain to perform tasks not well suited to the domain of your expertise.  This is how electrical wiring is done when the electrical designer needs to make sure his design meets the constraints of the mechanical embodiment of the product (Figure 10).

Figure 10. Enable selective access to the required data; facilitate rapid translation of data formats

Flexibility and openness of the enterprise data base is the most important criterion (Figure 11).  If addition of a new data format requires a major revision of the entire data base system, it’s impractical to wait. Typically, other things are impacted when a major revision of this type is attempted so the data base structure must be designed for flexibility to change some formats without having to reverify the entire database system.

Finally, the more a design environment feels familiar, the more likely the development engineers will create good products (Figure 12)

Figure 11.  Make sure the enterprise data management has the flexibility to add or change data formats selectively without re-verification of the entire data base management system

Figure 12.  Developers have enough to worry about without adapting to changes in their design environment and support

Although the “lessons learned” provide guidance for how data bases and design environments should be structured, few large corporations have been able to implement the level of interoperability between disciplines that they would like.  Figure 13 is still a hope rather than a reality.  Even if the commercial databases and design software provide the capability for data to be accessed and analyzed from functional domain to functional domain, system optimization would still require that compromises be made in one domain to achieve the optimum result at the system level.  Perhaps this is why systems companies who find ways to overcome this challenge have traditionally achieved higher operating margins than component companies.

Figure 13.  Specialization in large enterprises can be a strength, rather than a burden.  Development environments that maintain the needed specialization by discipline while affording access to data in other domains leads to the most productive enterprise

It’s likely that success will evolve application by application.  The case of electrical wiring of cars and planes reached such a critical level that integrated solutions evolved among the electrical, mechanical and manufacturing domains. Other applications are reaching a critical point where system optimization can only be achieved in an environment where multi-domain tradeoffs can be made. Making these tradeoffs at the highest possible level of abstraction is most likely to produce an optimum result and is also most likely to facilitate compatible development in the diverse functional domains of the corporation.


TSMC OIP Overview and Agenda!

TSMC OIP Overview and Agenda!
by Daniel Nenni on 09-05-2019 at 6:00 am

The TSMC Symposium and OIP Ecosystem Fourm are the most coveted events of the year for the fabless semiconductor ecosystem, absolutely. In my 35 years of semiconductor experience never has there been a more exciting time in the ecosystem and that is clear by the overview and agenda for this year’s event. I hope to see you there:

The TSMC OIP Ecosystem Forum brings together TSMC’s design ecosystem companies and our customers to share practical, tested solutions to today’s design challenges. Success stories that illustrate TSMC’s design ecosystem best practices highlight the event.

More than 90% of last year’s attendees said that, “the forum helped me better understand TSMC’s Open Innovation Platform” and that “I found it effective to hear directly from TSMC OIP member companies.”

This year’s event will prove equally valuable as you hear directly from TSMC OIP companies about how to apply their technologies and joint design solutions to address your design challenges in High-Performance Computing (HPC), Mobile, Automotive and Internet-of-Thing (IoT) applications.

This year, the forum is a day-long conference kicking-off with trend-setting addresses and announcements from TSMC and leading IC design company executives.

The technical sessions are dedicated to 30 selected technical papers from TSMC’s EDA, IP, Design Center Alliance and Value Chain Aggregator member companies. And the Ecosystem Pavilion feature up to 70 member companies showcasing their products and services.

Date: Thursday, September 26, 2019 8:00 AM – 6:30 PM

Venue: Santa Clara Convention Center

Learn About:

  • Emerging advanced node design challenges including 5nm, 6nm, 7nm, 12FFC/16FFC, 16FF+, 22ULP/ULL, 28nm, and ultra-low power process technologies.
  • Updated design solutions for specialty technologies supporting Internet-of-Thing (IoT) applications
  • Successful, real-life applications of design technologies and IP from ecosystem members and TSMC customers
  • Ecosystem-specific TSMC reference flow implementations
  • New innovations for next generation product designs targeting HPC, mobile, automotive and IoT applications

Hear directly from ecosystem companies about their TSMC-specific design solutions. Network with your peers and more than 1,000 industry experts and end users.

The TSMC Open Innovation Platform Ecosystem Forum is an “invitation-only” event.  Please register to attend. We look forward to seeing you at the event.

The views expressed in the presentations made at this event are those of the speaker and are not necessarily those of TSMC.

Agenda:

Join the TSMC 2019 Open Innovation Platform® Ecosystem Forum and hear directly from TSMC OIP companies about how to leverage their technology to your design challenges!

08:00 – 09:00 Registration & Ecosystem Pavilion

09:00 – 09:20 Welcome Remarks

09:20 – 10:10 TSMC and its Ecosystem for Innovation

10:10 – 10:30 Coffee Break

REGISTRATION

Please click the paper title to see its abstract:

HPC & 3DIC Mobile & Automotive IoT & RF
10:30 – 11:00
TSMC 3DIC Design Enablement Updates
TSMC
TSMC EDA & IP Design Enablement Updates
TSMC
TSMC RF Design Enablement Updates
TSMC
11:00 – 11:30

Calibre in the Cloud – A Case study with AMD, Mentor & TSMC

Microsoft/AMD/Mentor

Functional Safety Analysis and Verification to meet the requirements of the Automotive market

Texas Instruments/Cadence

Simplify Energy Efficient designs with cost-effective SoC Platform

Dolphin Design
11:30 – 12:00

Optimizing FPGA-HBM in InFO_MS Structure

Xilinx/Cadence

Thermal-induced reliability challenge and solution for advanced IC design

ANSYS

Flexible clocking solutions in advanced FinFET processes from 16nm to 5nm

Silicon Creations
12:00 – 13:00 Lunch & Ecosystem Pavilion
13:00 – 13:30

Chiplets solutions using CoWoS and InFO with 112Gbps SerDes and HBM2E/3.2Gbps for AI, HPC and Networking

GUC

Overcome time-to-market and resource challenges: Hierarchical DFT for advanced node SoC design and production

AMD/Mentor

Developing AI-based Solutions for Chip Design

Synopsys
13:30 – 14:00

Realizing Adaptable Compute Platform for AI/ML and 5G with Synopsys’ Fusion Design Platform

Xilinx/Synopsys

Comprehensive ESD/Latch-up reliability verification for IP & SoC Designs

NXP/Silicon Frontline/Mentor

Reliable, Secure and Flexible OTP solutions in TSMC for IoT, AI and Automotive Applications

eMemory
14:00 – 14:30

HBM2E 4gbps I/O Design Techniques in 7nm & Below Nodes

Open-Silicon

Sensor fusion and ADAS SOC designs in TSMC 16FFC and N7

Cadence

High-Speed Interface IP PAM-4 56G/112G Ethernet PHY IP for 400G and Beyond Hyperscale Data Centers

Synopsys
14:30 – 15:00

Pushing 3GHz Performance of TSMC N7 Arm Neoverse N1 CPU using the Cadence Digital Flow

Cadence/Arm

AWS Cloud enablement of design characterization flows using Synopsys® Primetime® & HSPICE®

Xilinx/Synopsys

Automotive IP Functional Safety – A Verification Challenge

Cadence
15:00 – 15:30 Coffee Break & Ecosystem Pavilion
15:30 – 16:00

Large Scale Silicon Photonic Interconnects for Mass Market Adoption

HPE/Mentor

A New Era of MIPI D-PHY and C- PHY: Automotive Applications

M31

Best practices for Arm Cortex CPU energy efficient implementation flows

Arm
16:00 – 16:30

Photonics Coming of Age: From Laboratory to Mainstream Applications

Cadence/Lumerical

Integrating ADAS Controllers with Automotive-Grade IP for TSMC N7

Synopsys

The Challenges Posed by Dynamic Uncertainty on AI & ML Devices Targeting 16nm, 7nm & 5nm

Moortec
16:30 – 17:00

Accelerating Semiconductor Design Flows with EDA on the Cloud

Astera Labs/AWS

Arm automotive physical IP addresses new feature and functionality demands

Arm

Developing AI Accelerators for TSMC N7

Synopsys
17:00 – 17:30

Best Practices using Synopsys Fusion Technology to Achieve High-performance, Energy Efficient implementations of the latest Arm® Processors in TSMC 7nm FinFET Process Technology

Synopsys/Arm

Cloud-based Characterization with Cadence Liberate Trio Characterization Suite and Arm-based Graviton

Cadence
Optimize SOC designs while enabling faster tapeouts by closing chip integration DRC issues early in the design cycle
MaxLinear/Mentor
17:30– 18:30 Social Hour

 

TSMC pioneered the pure-play foundry business model when it was founded in 1987, and has been the world’s largest dedicated semiconductor foundry ever since. The company supports a thriving ecosystem of global customers and partners with the industry’s leading process technology and portfolio of design enablement solutions to unleash innovation for the global semiconductor industry.

TSMC serves its customers with annual capacity of about 12 million 12-inch equivalent wafers in 2019 from fabs in Taiwan, the United States, and China, and provides the broadest range of technologies from 0.5 micron plus all the way to foundry’s most advanced processes, which is 7-nanometer today. TSMC is the first foundry to provide 7-nanometer production capabilities, and is headquartered in Hsinchu, Taiwan.

REGISTRATION


Carnegie Robotics Case Study: RTLvisionPRO

Carnegie Robotics Case Study: RTLvisionPRO
by Daniel Nenni on 09-04-2019 at 10:00 am

RTLvisionPRO has proven to be an indispensable tool which has greatly improved the productivity and work-flow of our current task: understanding, verifying, and documenting the existing RTL IP library at our company. Consisting of about 500 Verilog and VHDL files, the library has been under development for several years and implements a multitude of image-processing modules and pipelines used in our current sensor and peripheral products. While well-tested and vetted, most modules in the library lack an in-depth level of documentation that is needed for effective re-deployment in new products. Our task has been to carry out a critical review of the library modules and to create a detailed set of documents which convey the deep knowledge necessary to understand their implementation and function.

Webinar: Designing Complex SoCs and Dealing with Multiple File Formats?

As expected, the task has been overwhelming and difficult. Perhaps a complicating factor is the fact that the same FPGA serves multiple purposes in different products and peripherals. Many pins have multiple functions with a significant percentage remaining unused in each implementation. Working through the design by tracing from signals can be quite time consuming. One needs to navigate from file to file tracing signals and nodes in an effort to understand how the design works. This is a tedious task as steps need to be documented while traversing from module-to-module. RTLvision essentially does all the tedious parts of this task. It has a seamless interface with which one can navigate through the design. It keeps track of every step along the way so you can step back and forth and record the appropriate snapshot for documentation. If you go through something unimportant, you can simply go back to where you were before you took the wrong turn. This is an outstanding feature. It also supports bookmarks so you can jump to strategic places quickly.

The typical first step in understanding an existing design is to get a top-level picture of the entire system. This requires a comprehensive capture and representation of the design, all in one place. We were able to import the entire code base into RTLvision using a simple script which listed the directory paths to the libraries and the RTL design files themselves. The tool crunched on the files and returned with a set of top-level designs it found in the provided files. This was surprisingly simple and quick. After the importing stage, the tool builds a database which can be saved to a file eliminating the need to reimport the files. The database of our 500-file design loads in seconds.

The global schematic view given by all FPGA tools is not particularly useful. Essentially, you see a schematic view similar to the figure above. A number of modules are connected by millions of undiscernible connections. Tracing through that is basically impossible. We needed a tool to show the modules but help us trace signals as we work our way through a data path. This is exactly where RTLvision shines. Using the Cone view, you can focus on the parts of the path you are interested in and not display all the clutter from all adjacent nodes and signals. This is a powerful feature of the program. You can see more and more detail by repeatedly clicking on the traced signal. If you click too many times, uncovering uninteresting parts, you can always go back where you were before using the back arrow.

You can quickly generate schematic diagrams which are derived from the RTL files. You can move things around or have the program place components in a sensible orientation to make a clear diagram similar to the one above.

We continue to learn about the other debugging and analysis features of the program. But simply for going through and understand the bulk of a large design, RTLvisionPro has been an indispensable tool.

Omead Amidi, Ph.D.

Carnegie Robotics, LLC
4501 Hatfield Street
Pittsburgh, PA 15201

Webinar: Desinging Complex SoCs and Dealing with Multiple File Formats?


AI, Safety and the Network

AI, Safety and the Network
by Bernard Murphy on 09-04-2019 at 6:00 am

If you follow my blogs you know that Arteris IP is very active in these areas, leveraging their central value in network-on-chip (NoC) architectures. Kurt Shuler has put together a front-to-back white-paper to walk you through the essentials of AI, particularly machine learning (ML) and its application for example in cars.

He also highlights an interesting point about this rapidly evolving technology. As we build automation from the edge to the fog to the cloud, functionality, including AI, remains quite fluid between levels. Kurt points out that this is somewhat mirrored in SoC design. In both cases architecture is constrained by need to optimize performance and minimize power across the system through intelligent bandwidth allocation and data locality. And for safety-critical applications, design and verification for safety around intelligent features must be checked not only within and between SoCs in the car but also beyond, for example in V2x communication between cars and other traffic infrastructure.

What’s driving the boom in AI-centric design? If you’re not in the field it might seem that AI is just another shiny toy for marketing, destined for the garbage can when some inevitable fatal flaw emerges. You couldn’t be more wrong (pace Sheldon Cooper). Tractica estimates that more than 80% of the growth in semiconductors between now and 2025 with be driven by AI applications, whether based on standard platforms (CPU, GPU or FPGA) or custom-built ASIC/ASSPs or highly-specialized accelerators. (The overlay in the image above is Kurt’s addition).

None of this demand depends on major inflection points in the way we live. It’s all about incremental improvements to safety, productivity, security, convenience – all the things technology has been improving for a long time. Whether or not ADAS in cars impresses insurance providers (per my earlier blog), it definitely impresses this owner and apparently many others. I’ve said before I’ll never switch back to a car with lesser ADAS features – they more than pay for themselves. Security for business and industrial plants is already moving from need to constantly monitor security camera feeds to only having to check when unusual movement and/or sounds (dog barking, glass breaking) are detected. Also incidentally this is much better for home security.

Oncologists may be able to more reliably detect potentially cancerous lung tissue based on CT scans (following further analysis). Smart storage solution providers now need to build intelligence into their solutions to better manage housekeeping and other scheduling to maximize throughput and minimize failures. All of this is bread-and-butter stuff, no consumer, industrial or business revolutions required, just adding more automation to what we already have.

McKinsey went a step further than Tractica, breaking down AI hardware growth between training and inference in the datacenter and training and inference on the edge. The biggest contributors are in the datacenter (I’m curious to know how much of that is for cat recognition and friend-tagging in Facebook photos.) And the highest growth is on the edge, growing in 7 years from essentially zero to $5-6B. These two surveys don’t come up with the same numbers for 2025, but that’s not very surprising. What is consistent is the high growth.

Why do Kurt and Arteris IP care about this? They care because the interconnect within an SoC is proving to be at the nexus of AI performance, power, cost and safety for these fast-growing applications. On performance, power and cost, these are big SoCs, smartphone AP-size or even bigger. Which means on-chip networks have to be NoCs and Arteris is pretty much the only proven commercial supplier in that area. Also, AI accelerators are not intrinsically coherent with the compute cluster on the SoC but have to become so to share imaging, voice and other data with the cluster. Arteris IP solutions help here through proxy caches and last-level cache solutions. And with the more advanced accelerators these NoC solutions often play an even deeper role in islands of cache coherence, in mesh, ring or torus architectures and in connecting to external dedicated high-bandwidth memory.

Finally on safety, Arteris IP is well plugged into ISO 26262 (Kurt has been on the working group for many years), they work very closely with integrators and with a certification group to ensure their product meets the letter and the spirit of the standard (increasingly important in ISO 26262-2). And they provide safety-related features within the logic they develop to support ECC, duplication and other safety related requirements with the domain of the logic they supply.

You can learn more by reading this white-paper.


SiFive to Host its Tech Symposium on RISC-V in Israel on September 5

SiFive to Host its Tech Symposium on RISC-V in Israel on September 5
by Swamy Irrinki on 09-03-2019 at 10:00 pm

There’s no question that the RISC-V ISA is revolutionizing the semiconductor ecosystem around the world. We see Israel as the epicenter of RISC-V based development and innovation in the Middle East. For the second year in a row, SiFive will be hosting its Tech Symposium on RISC-V in Israel to help foster the growth and momentum that’s happening in the region.

This year’s event will take place in Herzliya on September 5. It will feature presentations by several industry veterans, including Andrew Waterman, the privileged architecture committee chair for the RISC-V Foundation and co-founder and chief engineer at SiFive; Hiren Majmudar, vice president of corporate business development for SiFive; Moshe Sheier, vice president of marketing for CEVA; Danny Biran, business development advisor in Israel for Silicon Catalyst; Amir Fridman, senior director of corporate development and capital investment for Western Digital; Leonid Yavits, postdoctoral research fellow in electrical engineering at Technion; and Jahoor Vohra, senior field applications engineer at SiFive.

This powerful symposium is intended not only for those who are already well-versed in RISC-V, but also for newcomers and students who are planning to tap into the RISC-V community. It will be highly educational and will present many opportunities for networking and engagement with industry veterans, ecosystem partners and academic luminaries. Attendees will learn about the SaaS-based approach that is enabling fast access to custom cores, design platforms, and custom SoC solutions for emerging applications.

Attendance is free, but registration is required. Please visit https://sifivetechsymposium.com/agenda-israel/ to learn more and to secure your seat.

We look forward to seeing you!

About SiFive
SiFive is the leading provider of market-ready processor core IP and silicon solutions based on the free and open RISC-V instruction set architecture. Led by a team of seasoned silicon executives and the RISC-V inventors, SiFive helps SoC designers reduce time-to-market and realize cost savings with customized, open-architecture processor cores, and democratizes access to optimized silicon by enabling system designers in all market verticals to build customized RISC-V based semiconductors. With 15 offices worldwide, SiFive has backing from Sutter Hill Ventures, Qualcomm Ventures, Spark Capital, Osage University Partners, Chengwei, Huami, SK Hynix, Intel Capital, and Western Digital. For more information, www.sifive.com.


Leave the Driving to Musk!

Leave the Driving to Musk!
by Roger C. Lanctot on 09-03-2019 at 10:00 am

For years Tesla Motors’ CEO Elon Musk has been taunting the global insurance industry that he would offer insurance coverage directly from Tesla if he was dissatisfied with the industry’s own underwriting. That shoe dropped last week with a resounding thud as Tesla Insurance Services launched in California.

As part of the filing, made earlier this year in collaboration with insurer State National, Tesla intends to offer the usual range of discounts: good driver, elite driver, good student, mature driver improvement course, multi-car, anti-theft, airbag, etc. But Tesla also intends to offer discounts based on level of driving automation based on SAE autonomous driving definitions (as follows):

“Auto-Pilot Discount”

“Vehicles equipped with an autonomous feature option will be eligible for credits based on the level of autonomy of the vehicle. The discount is applied to Bodily Injury, Property Damage, Medical Payments and Collision coverages.

“Available level definitions are shown below:

“Level 0 – The full-time performance by the human driver of all aspects of the dynamic driving task, even when enhanced by warning or intervention systems.

“Level 1 – The driving mode-specific execution by a driver assistance system of either steering or acceleration/deceleration using information about the driving environment and with the expectation that the human driver perform all remaining aspects of the dynamic driving task.

“Level 2 – The driving mode-specific execution by one or more driver assistance systems of both steering and acceleration/deceleration using information about the driving environment and with the expectation that the human driver perform all remaining aspects of the dynamic driving task.

“Level 3 – The driving mode-specific performance by an automated driving system of all aspects of the dynamic driving task with the expectation that the human driver will respond appropriately to a request to intervene.

“Level 4 – The driving mode-specific performance by an automated driving system of all aspects of the dynamic driving task, even if a human driver does not respond appropriately to a request to intervene.

“Level 5 – The full-time performance by an automated driving system of all aspects of the dynamic driving task under all roadway and environmental conditions that can be managed by a human driver.”

Tesla is enhancing the attractiveness of self-driving technology by not only offering discounted insurance coverage (in spite of some early negative assessments of the initial rates, since adjusted), but also incenting Tesla owners by offering escalating discounts based on the level of automated driving. For drivers who might be hesitant or put off by the concept of automated driving, Tesla is saying: “Jump in! The water’s warm and we’ll give you a discount!”

The significance of this gesture is underpinned by recent research from J.D. Power & Associates and the Insurance Institute for Highway Safety suggesting that consumers are resistant to lane-keeping assistance technologies – turning off these systems because they are annoyed by the alerts. In other words, both J.D. Power and IIHS are suggesting that discounts should not or cannot be offered to consumers who buy cars with lane keeping, because the feature is frequently disabled.

The same researchers, and others, suggest that consumers and drivers are leery of self-driving technology in general. Tesla is clearly intending to win these folks over as well. Tesla is essentially endorsing insurance discounts for lane keeping technology and autonomous driving, plain and simple. Tesla is saying, in essence, “Automated driving isn’t annoying. It’s awesome.”

The offer may only be coming to market in California, but the message from Tesla is clear: the implementation of lane keeping and automated driving ought to be tied to insurance discounts. Competing auto makers cannot guarantee that insurers will provide such discounts for their systems and the National Highway Traffic Safety Administration has yet to pursue a lane-keeping mandate, so Tesla is moving the issue forward as a challenge to the industry – and a differentiator vs. competing auto makers.

Tesla’s stated objective, based on recent earnings call comments by CEO Musk, is to reduce the overall cost of ownership of a Tesla vehicle. Tesla’s assumption is that insurance is a considerable component of a vehicle’s cost of ownership.

The problem with this argument is that for most middle-aged or older drivers insurance is much less of a cost consideration when acquiring a car. By the time drivers have crossed in to middle age – in most regions of the world – their car insurance rates have plunged to inconsequential levels below which it is difficult to discount.

On the other hand, for younger drivers, always coveted by car makers around the world for new car sales, insurance rates can be steep indeed. The net conclusion is that the Tesla insurance discounts will be most appealing to younger drivers.

This means that Tesla is not only skimming the cream off the top of the luxury market – giving a market share haircut to the likes of Mercedes-Benz, BMW, Audi, and Lexus – it is now giving them a demographic trim as well with a blatant insurance-based appeal to younger drivers.

So researchers and insurance companies grouse about annoying lane-keeping alerts, while Tesla blows by with in-house insurance discounts encouraging and rewarding the use of lane-keeping and, ultimately, promoting autonomous driving. The crowning touch is the fact that Tesla is promoting sales of its autonomous driving systems.

Tesla’s Autopilot is an option that can range from $4,000 for the basic application to $7,000 for “full self driving” (FSD). Tesla insurance may be intended to reduce the cost of ownership, but the biggest discounts may only be available to those customers willing to fork over thousands of dollars for optional Autopilot capabilities.

This is a breakthrough marketing play recognizing what experts have known for decades: Safety Sells! The automotive industry and regulators have exhausted their passive safety system regulations and mandates for such things as airbags and seatbelts. Tesla is seizing a leadership role in promoting active safety system technology.

For Tesla customers – at least those in California for now – still on the fence over upgrading to Autopilot, the insurance offer might tip the balance. It’s just another step in Musk’s march to dominate the business of automating driving.

Tesla’s single greatest advantage over Waymo, Cruise and all the other companies working on autonomous driving technology is the wealth of data being collected from its semi-autonomous vehicles with human drivers. Every Tesla driver with Autopilot is an active sensor on Tesla’s self-driving network gathering data on edge cases on highways all over the world.

Cruise Automation may someday master autonomous operation in San Francisco and Waymo may conquer Phoenix – both at relatively slow speeds. Tesla threatens to be the first to offer a global or near-global Level 3-4-5 experience on a massive scale.

It is ironic that insurance emerges at the core of Tesla’s strategy. In a recent interview with Lex Fridman of MIT, Comma.ai founder George Hotz suggested that there is a multi-billion dollar insurance opportunity in autonomous driving technology. If so, Musk is the canary in the coalmine hoping to find gold underwriting automated driving.


Cryptocurrencies Should be Enabled to Blacklist Criminal Holdings

Cryptocurrencies Should be Enabled to Blacklist Criminal Holdings
by Matthew Rosenquist on 09-03-2019 at 6:00 am

Cryptocurrency is seen as a new, wild, reckless, revolutionary, and sometimes shady financial instrument. In addition to legitimate transactions, a disproportionate amount of attention is paid to the criminal use of cryptocurrency to store wealth, collect payments, transfer illicit funds, and launder money. Malicious people, who victimize others, use it as a tool to hide and protect their ill-gotten gains. Law enforcement and even currency champions are mostly powerless to do anything about it. Criminals will continue to use cryptocurrency as their haven unless something is improved.

Recently, the U.S. Treasury identified several foreign nationals who were laundering vast sums of money and using cryptocurrency to support illegal drug smuggling. The U.S. Treasury notified legitimate exchanges to ‘blacklist’ any transactions originating from these drug kingpins, but it is more likely that the unlawful assets will be moved, shifted, and eventually extracted by the criminals. If the funds were in a bank they could be seized. Decentralized cryptocurrencies, like Bitcoin and Ethereum, don’t work that way. This is exactly why criminals use crypto so much, as it keeps their assets out of reach from authorities.

recent Chinese Ponzi scheme involving the PlusToken netted criminals $3 billion since 2018. With authorities in pursuit, the bad actors are now dumping massive amounts of Bitcoin, Ether, and EOS in a massive sell-off, to launder the money. Due to the sheer amounts, this sell-off may be contributing to the recent downward price pressure of the entire Bitcoin and altcoin markets. That affects everyone.

Not much can be done if the criminals are savvy and careful. Cryptocurrency was originally designed to preserve anonymity, not have a central control point, and be accessible from anywhere. These traits are very attractive to criminals. Attacks are increasing in size and becoming more common as the world embraces digital technology. Unfortunately, cyber criminals are misusing technology to steal, swindle, ransom, and become more powerful.

Solution in the Code – Proposal
There could be a way to help thwart big crimes involving decentralized types of digital currency while still retaining all the desired benefits for the vast majority. The result may be enhanced legitimacy and trust, thereby strengthening the adoption and favorable regulation for cryptocurrency. Specialized functions could undermine the methods being employed in big digital crimes and provide relief to some victims.

The solution to this problem may reside in the self-regulating architecture of the cryptocurrency code itself.

Cryptocurrencies are created with a set of rules and decentralized nodes then enforce them. As part of the self-governance, the rules can be changed via ‘forks’ in the code, but it takes a certain percentage of the distributed nodes to agree to the change. This enables new features, contracts, or just about any beneficial rules the community may want.

The idea is to create a Blacklist Revocation Function. This would only be triggered by a consensus mechanism when a suitable situation arises but would result in the criminal accounts being rendered invalid and coins recovered to be redistributed back to the victims or re-absorbed into the system.

The goal would be to penalize, not reward, criminal behavior and to make them think twice about using cryptocurrency for harmful purposes. Not every crime needs to be thwarted, but the risk of losing everything may be enough to deter or discourage villains.

How it Would Work
This year criminals stole $40 million from the Binance exchange and are now working to digitally launder and extract those funds. If the Blacklist Revocation Function were in place, it could be activated and if it reached consensus, the funds could be pulled from the attacker’s accounts and returned to the rightful owners.

The process would not need to be overly complex (although details would obviously need to be worked out).

  1. Step 1: Investigation – Legitimate law enforcement conducts an investigation and identifies the attacker’s wallets. This can be done quickly in most cases, with the cooperation of victims, for public blockchains like Bitcoin.
  2. Step 2: Activation – The Blacklist Revocation Function process would be activated. Basically, it is a soft-fork request that activates already coded routines. As part of the request, it would identify which accounts and tracks of transactions would be invalidated. It must also specify what is to be done with the blacklisted coins and the timing to take effect. If a known victim(s) are listed, their assets could be returned by voiding out the original transfer transactions or by some other follow-on means. If not, then the coins could be re-absorbed into the system in some way (general distribution, extend mining curve, temporarily increasing block validation rewards, or pay for general transaction fees for all users for a period of time). The point is that the coins won’t be burned, lost, or seized. The total number of expected coins in the system will remain predictable. They will continue to benefit the community with minimum disruption to the overall coin availability.
  3. Step 3: Validation – Now comes the tricky part. Carefully prepared evidence must be made available by the submitting law enforcement, for the community to ‘judge’ if this is a valid request. The reputation of previous submissions will play a part in trusting the accuracy and completeness of the information. A vote would take place and this function would only activate if it met the required consensus, usually more than 50%, is in support to make the changes. In essence, the community would decide by a pseudo-public trial to pass or fail the request.
  4. Step 4: Resolution – If the soft fork is not supported by the community, it dies and is simply not implemented. If it passes, then it is activated on the blockchain like any other decentralized digital contract or soft-fork. The power of the system itself is utilized to do the work of enacting changes to invalidate accounts, turn-back transactions, or effectively seize assets.

In addition to the interdiction of attacks, recovery of assets, and victim restitution, the benefits also include deterrence. It is reasonable to assume not every Blacklist Revocation Function request will be approved. But some will, which gives law enforcement and victims a powerful capability to correct the wrongs of attackers. As attackers would not know which would or wouldn’t be passed, it creates uncertainty for them that their assets may be stripped. This may cause enough doubt and fear to deter such attacks or illicit use of cryptocurrency.

Another important aspect is that the use of this Blacklist Revocation Function would not result in the law enforcement agencies seizing any assets. In fact, they don’t financially gain anything as the coins would be returned to the victims or redistributed back to the community in some way. This would deter potential abuses of overly aggressive seizures and forfeitures, a concern of many, to reinforce trust in the system.

Conclusions
Crime is disruptive; it impacts victims, markets, law enforcement, and therefore everyone in some way. Decentralized cryptocurrencies are incredibly powerful. These enabling technologies should be designed to be less beneficial to malicious criminals and lean towards protecting benevolent users. A Blacklist Revocation Function could provide tremendous benefits and relief to victims of digital crimes. At the same time, they increase trust and legitimacy for cryptocurrency. There is no perfect solution to digital crime, but applying the strengths of decentralized blockchain architectures could be an important step in the right direction to empower justice without sacrificing the independence of cryptocurrency.

Is there a better way of balancing security and trust when it comes to pursuing criminals into the realm of cryptocurrency? Innovation is needed to enable improved tools for law enforcement while preserving the independence of decentralized digital currency. A Blacklist Revocation Function could be one answer.

Matthew Rosenquist, Cybersecurity Strategist


WEBINAR: Lightspeed Data Sync – Design Workspace Problems Solved!

WEBINAR: Lightspeed Data Sync – Design Workspace Problems Solved!
by Daniel Nenni on 09-02-2019 at 10:00 am

With every process node and every SOC design, engineering and IT teams are experiencing an unprecedented data explosion. User workspaces routinely exceed 10’s of GB and sometimes even 100’s of GB. Regression runs, characterization runs, design and debug of workspaces, building verification environments – all of these put a great stress on Network Attached Storage (NAS) and Cloud resources, create NFS and IO bottlenecks, and cause significant project delays. And things are only going to get worse.

REPLAY

WarpStor is a Content Aware optimizer and accelerator that works to dramatically reduce workspace storage requirements, engineering workspace creation time, network IO bandwidth, and provides almost “lightspeed” data sync whether you are using on premise storage, cloud storage, or both.

Unlike other systems, WarpStor optimizes user workspaces at build time. It does not require any kernel level changes on the client machines, and it does not require post-processing like some data-deduplication technologies. It works in real time and scales easily as needed. For example, additional WarpStor instances can be added at any time on premise, across the enterprise at remote datacenters, and to the cloud, all without disrupting ongoing projects. WarpStor provides its benefits through the use of proprietary technology that creates and manages workspace ‘Masters’ and ‘Clones’. It is transparent to all users. Workspaces are built as fully functional ‘Clones’ of an existing master. These clones start off nearly empty, but to the OS and applications, they appear like any other set of files on disk.  As users or applications modify files in the workspace, WarpStor makes the actual file blocks instantly available in the workspace using highly efficient ‘Copy-On-Write’ technology.

This only makes those blocks within files that have been modified local to the workspace at the time of writing. This ensures that workspaces occupy the minimum possible space on disk, as all blocks that are common between a master and its clones are abstracted away. The results experienced by users are dramatic – incremental data syncs are virtually “lightspeed” across the enterprise, workspace creation time is reduced to seconds from minutes or hours and, at the same time, users can see up to 90% reduction in storage requirements and a corresponding reduction in network IO traffic.

In summary, WarpStor can be viewed as a seamless way to radically reduce your expensive storage requirements and engineering workspace creation and submit times for all design and test related workspaces. It works with your current storage and cloud solutions, your current IT infrastructure, and your current IT policies.

REPLAY

About Methodics
Methodics solutions enable high-performance hierarchical analog/mixed signal, digital, software, embedded software, and SOC design collaboration across multi-site and multi-geographic design teams, assuring full traceability of the use and reuse of important design assets for Functional Safety compliance with such standards as ISO26262 and DO-254. With Methodics, traceability is built into the design process – it’s not added on as an after thought.

Advanced IP distribution, cataloging, and workspace management ensure that no matter where designers are located they have full visibility into the IP available to them and can easily access the corresponding data.

And integration of IP Lifecycle Management with industry-standard data management solutions, such as Perforce, Subversion, Git and others makes designs more efficient and predictable, and with higher quality. This approach ensures data is safe, always available, and that the tools can take advantage of the latest advancements from the software configuration management community.

Our highly scalable and industry proven solutions are ideal for large multinational, multisite SoC design teams as well as for small, specialized design teams. www.methodics.com


From AMD to Actel (to Microchip)

From AMD to Actel (to Microchip)
by John East on 09-02-2019 at 6:00 am

By the late 80s it had become clear to me that the Japanese were right.  Memories,  Microprocessors,  and Gate Arrays (As well as ASICs) were what customers wanted then.  “Building blocks of ever-increasing complexity” was obsolete.  What next?  Should I try to become an overnight networking expert?  Maybe a DSP expert?  Pretty tough to do!!  Or — how about programmable logic?  That could work!!

MMI (Monolithic Memories Incorporated) and others had introduced field programmable logic products a couple of decades earlier using nichrome fuses – devices that conducted current unless you forced a high current through them and “blew them out”.  The high current destroyed the fuses so that they would no longer conduct current.  This “off” state would be the new permanent state of the fuse.   This was exactly the same concept as the fuses that were in the fuse box of every home back when I was young.  (Remember – I’m a dinosaur.) MMI’s programmable logic was great.  People loved it.  But  — the programmable circuits available then (Called PALs) were small  — on the order of a few hundred gates when the real demand was for circuits with capacities of many thousands of gates.   It was clear to me that a truly field programmable gate array would be a big winner.

I was approached by the board of directors of Actel.  They were looking for a new CEO.  Their product was to be a field programmable gate array. (Andy Haines came up with the term “FPGA” at Actel in 1989 so they weren’t using the term “FPGA” when they were trying to hire me, but that’s what it was.)

The existing FPGA technology (Xilinx) used large numbers of flip flops to store the configuration data.  Xilinx referred to these products as “SRAM Logic Cell Arrays” (Later they changed that to SRAM FPGAs).  Actel planned to use antifuses instead of flip-flops.  An antifuse is the opposite of a fuse.  Antifuses do not conduct electricity unless a very high voltage is placed across them.  When that happens the fuses are “burned in”.  In other words,  they will now conduct current.  This “on” state is the new, permanent state of the antifuse.

It seemed to me that SRAM FPGAs had a glaring defect. There are many ways that the state of a flip flop can accidentally be changed.  A power supply spike.  A power supply brown out.  A hit by a proton or ion or by some stray radiation.  These are all unpredictable ways that configuration can be lost. To make the problem worse, there was never a good way to know in real time that corruption had occurred.  (I think that this is true even today).  So  — if corruption occurred,  the circuit might go merrily on its way producing incorrect results and the user wouldn’t know.  It was a recipe for disaster!!  Or so I thought.  The SRAM technique did have a significant advantage —  it allowed you to use a standard foundry process.  The antifuse required a handful of tricky extra process steps the foundries didn’t like.  But  — overall I felt that the antifuse would prevail.  The process would eventually become a standard and the reliability benefits accruing to the antifuse would win the day!!  Again  — so I thought.

Actel’s board of directors looked like an all-star team.  Ed  Zschau (formerly in the US House of Representatives) was on it.  Bill Davidow  (One of the most famous marketing guys in the IC industry) was on it.  And Carver Mead was on it as well.  Carver was a Cal Tech professor with an IQ of about 200 who had co-written a textbook that was used in virtually every university. (The textbook was known as “Mead-Conway”).  After some foreplay,  Ed Zschau invited me to have breakfast at his home in Los Altos.  During the meal, he offered me a job as the CEO of Actel.  Wow!!!   I had an opportunity to become the CEO of the only antifuse based FPGA company.  I love FPGAs! Antifuses will dominate the industry!!!!   I’LL TAKE IT!!!  WHEN DO I START?

Boy.  Was I ever wrong!!!  Sometimes I feel like I’ve spent the better part of my life being wrong,  but that was the pinnacle.  The antifuse did not turn out to be a wonderful thing! Why?  First,  customers wanted reprogrammability  — the ability to change the configuration as many times as might be needed without having to remove the part from the board and pay for a new part..  Antifuses were OTP (One time programmable).  If you wanted to change something in an antifuse FPGA, you were out of luck.  You had to unsolder it from the board, throw it out, buy a new one, program it, and solder it back onto the board. Customers hated that!!!  Second,  antifuses required a difficult custom fab process that prohibited us from ever being on an advanced process node (Xilinx was always on the most advanced process nodes.).  Those two problems prevented us from competing well in the two biggest and fastest growing market segments – telecom and networking.

I started at Actel in 1988.  By the mid 90s my love affair with antifuses had all but ended.  It had become clear to me that the SRAM configuration technique was clearly better for the majority of applications in those days.  Xilinx and Altera were already there with SRAM products.  We had only antifuse products.  There’s an old business school case study that goes something like this:  Company A dominates a market.  Company B comes along later with a better way to do it.  Who wins?  It’s not obvious.  It should shape up into a good fight.  That’s the battle I thought we’d be fighting when I joined Actel.  It wasn’t.  The battle we actually fought was: Company A dominates a market.  Company B comes along later with a worse way to do it.  Who wins?  Duh. …..  By the mid 90s I could see that we would eventually die fighting that battle unless we changed the rules of the game.

Clearly we had to replace our antifuse technology with something better.  With what?  Good question!!  I wasn’t sure. What was clear, though, was that it was going to take time and money!  It wouldn’t be fast.  It wouldn’t be cheap.  And it wouldn’t be easy!! Meanwhile,  the job was to figure out some market segments where we could at least compete well in the interim.  My favorite marketing book is the 22 Immutable Laws of Marketing.  It’s only 140 pages,  but they’re 140 pages of real wisdom.  Chapter 2 tells you in essence,  “Don’t try to horn in on a market that someone else already owns.  Figure out a subset of the market that you can own and go after it!!!”   And we did.  Our successful subsets generally centered around the reliability issues that I spelled out earlier.  The big markets like communications and networking weren’t buying into the antifuse concept.  But  —  markets that were super-worried about reliability often saw the Actel advantages.  The best of these markets for us turned out to be the satellite market.  In general, though, we did pretty well in the military and aviation markets as well as with certain industrial and medical products.  Those markets were good to us.  They allowed us to be consistently profitable.  But  —- they were all slow growing markets.  Wall Street wants fast growing markets and fast growing sales.  I always wanted to be growing faster, but it wasn’t to be. Life wasn’t easy in the antifuse business.

Nine years ago,  Microsemi bought Actel.  A year ago, Microchip bought Microsemi.  Today, the old Actel is a division of Microchip – a highly successful company based in Phoenix.

So  —- what became of the antifuse?  Actel still ships some antifuse products  — mostly into designs that were won long ago  —  but it’s no longer an antifuse technology-based FPGA company.  Under the leadership of Esmat Hamdy, Esam El Ashmawi and Bruce Weyer,  (Esmat is a founder who directs technology development. Esam and Bruce took turns running the company after I left), Actel completed our long strived-for transition into being a flash based FPGA company.   (To be exact,  flash and other newer reprogrammable NVM technologies).  Flash FPGAs retain the benefits of antifuses, but are reprogrammable and use a process that’s much closer to standard. Sales are rising and profits are very, very solid.  Actel is on a roll!!  Steve Sanghi made a wise acquisition!*  Actel and Microchip are thriving together thanks to the folks who have been there making things happen for so long –  many of them for 20 years or more.

So  —  Thanks Esmat, Thanks John. Thanks Ted. Thanks Lisa. Thanks Jon. Thanks Sinan. Thanks Ken. Thanks Fei. Thanks Joel. Thanks Arun. Thanks Jerome. Thanks Toufik. Thanks Nizar. Thanks Frank. Thanks JJ.  Thanks Fethi. Thanks Salim. Thanks Greg. Thanks Sifuei. Thanks Raymond. Thanks Habtom. Thanks Antony. Thanks Kathleen. Thanks Melissa. Thanks Nuru. Thanks Justin. Thanks Hui. Thanks Cathy. Thanks Chih Ping. Thanks Alynn. Thanks Rick. Thanks Paul. Thanks Gina. Thanks Pam. Thanks Vidya. Thanks Ken. Thanks Val. Thanks Volker. Thanks Dirk. Thanks Amir.  Thanks Gina. Thanks Jose. Thanks Max. Thanks Trina. Thanks Dora. Thanks Norma. Thanks Lisa. Thanks Carlos. Thanks Mateo . Thanks Hung. Thanks Dave. Thanks Bruce . Thanks David . Thanks Ray . Thanks Frank. Thanks Nelson . Thanks Becky. Thanks Vinh.  And thanks Tessie!!

(Good to see you the other day!)  We owe you a lot!!!

Next week:  Foundry woes

*No surprise there.  Steve (CEO of Microchip) does things right.

Pictured :  From left to right

Bill Davidow.  Former General partner of Mohr-Davidow Ventures.  Author of three books on High Tech including the immensely popular “Marketing High Technology”.

Carver Mead.  Former professor at CalTech.  Co-author of “Introduction to VLSI Design.”.  Involved in the founding of more than 20 high-tech start-ups.

Ed Zschau.  Former member of the US House of Representatives.  Former professor at Stanford.  Founder of Systems Industries. Former General Partner of Brentwood Associates.  Former CEO of Censtor.

See the entire John East series HERE.

# Andy Haines, Ed Zschau, Bill Davidow, Carver Mead, Esmat Hamdy, Esam El Ashmawi, Bruce Weyer, Steve Sanghi, MMI, Xilinx