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Why we will all benefit from the next space race

Why we will all benefit from the next space race
by Vivek Wadhwa on 01-27-2019 at 7:00 am
Categories: General
1 Comment

Until January 3, no human being had ever set eyes upon the “dark side” of the moon: the side always facing away from the Earth. It always remained a mystery. But no longer. China’s National Space Administration successfully landed a lunar lander, Chang’e-4, at South Pole-Aitken, the moon’s largest and deepest basin. Its lunar rover Yutu-2 is sending home dozens of pictures so that we can see the soil, rocks, and craters for ourselves. Seeds it took on the journey also just germinated, making this the first time any biological matter from Earth has been cultivated on the Moon.

Scientists had long speculated about the existence of water on the Moon — which would be necessary to grow crops and build settlements. India’s Chandrayaan-1 satellite confirmed a decade ago that there was water in the Moon’s exosphere, and in August 2018, it helped NASA find water ice on the surface of the darkest and coldest parts of its polar regions.

India’s Mangalyaan satellite went even further, to Mars, in 2014, and is sending back stunning images. Prime Minister Narendra Modi has promised a manned mission to space by 2022, and one Indian startup, Team Indus, has already built a lunar rover that can help with the exploration.

The Americans and Soviets may have started the space race in their quest for global domination, but China, India, Japan, and others have joined it. The most interesting entrants are entrepreneurs such as Elon Musk, Jeff Bezos, Richard Branson, and Team Indus’ Rahul Narayan. They are space explorers like the ones we saw in the science fiction, driven by ego, curiosity, and desire to make an impact on humanity. Technology has levelled the playing field so that even startups can compete and collaborate with governments.

In the fifty years since the Apollo 8 crew became the first to go round the moon and return, the exponential advance of technology has dramatically lowered the entry barriers. The accelerometers, gyroscopes, and precision navigation systems that cost millions and were national secrets are now available for a few cents on Alibaba. These are what enable the functioning of Google Maps and Apple health apps—and make space travel possible.
Satellites, rockets, and rovers are also much more affordable.

The NASA space-shuttle program cost about $209 billion over its lifetime and made a total of 135 flights, costing an average per launch of nearly $1.6 billion. Its single-use rockets were priced in the hundreds of millions of dollars. Elon Musk’s company SpaceX now offers launch services for $62 million for its reusable Falcon 9 rockets, which can carry a load of 4020 Kg. And yes, discounts are available for bulk. Team Indus built their lunar rover with only $35 million of funding and a team of rag-tag engineers in Bangalore.

NASA catalyzed the creation of technologies as diverse as home insulation, miniature cameras, CAT scans, LEDs, landmine removal, athletic shoes, foil blankets, water-purification technology, ear thermometers, memory foam, freeze-dried food, and baby formulas. We can expect the new forays into space to yield even more. The opportunities are endless: biological experimentation, resource extraction, figuring out how to live on other planets, space travel, and tourism. The technologies will include next-generation nano satellites, image sensors, GPS, communication networks, and a host of innovations we haven’t conceived of yet. We can also expect to be manufacturing in space and 3D-printing buildings for space colonies.

Developments in each of these frontiers will provide new insights and innovations for life on earth. Learning about growing plants on the moon can help us to grow plants in difficult conditions on this planet. The buildings NASA creates for Mars will be a model for housing in extreme climates.

As with every technology advance, there are also new fears and risks. Next-generation imagery can provide military advantages through intelligence gathering. The military already has an uncanny ability to track specific people and watch them in incredible detail. For any sort of space station or base on another planet or moon, there is the question of who sets the rules, standards, and language that’s used in outer space. Then there’s the larger question of whose ethical and social values will guide the space communities of the future — and the even larger question of whether places beyond Earth are ethically claimable as property at all.

Regardless of the risks, the era of space exploration has begun and we can expect many exciting breakthroughs. We can also start dreaming about the places we want to visit in the heavens.

For more on how we can create the amazing future of Star Trek, please read my book: The Driver in the Driverless Car

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ASML and Memory Loss 2019

ASML and Memory Loss 2019
by Robert Maire on 01-25-2019 at 7:00 am
Categories: Semiconductor Advisors, Semiconductor Services

ASML reported a more or less in line quarter as expected, coming in at EUR3.14B in revenues and EPS of EUR1.87. However, guidance was worse than most analysts were expecting with Q1 revenues expected to be EUR2.1B or down about one third.

This cut is something we have been talking about for a while as we have expected sharp memory CAPEX cuts with recent logic/foundry cuts adding to the downturn. Since things were going to be bad anyway, ASML decided to throw in the kitchen sink and settle its lawsuit with Nikon which will cut Q1 even further after its payments to Nikon for patent infringement. Orders dropped very sharply from EUR2.2B in Q3 to EUR1.59B in Q4 but more importantly, 80% of those orders were for logic/foundry which means that memory spending has virtually ground to a halt.

This means that memory spending is down about 50% from peak levels.

The breakout of system sales tells the story; USA (meaning Intel since GF is dead) went from 5% in Q3 to 32% in Q4, China stayed at 18%, Korea dropped from 33% to 26% and Taiwan (TSMC) dropped from 30% to 20%. In Q3, memory was 58% of sales whereas in Q4 memory fell to 40%. 5 EUV systems were shipped, same as Q3.

Memory orders fell from 63% of orders in Q3 to 20% of orders in Q4 as memory drove off a cliff without skid marks.
Unfortunately ASML is stuck in a typical downcycle which they can’t do a lot about. In our view, it is clear that ASML will be one of the least impacted companies, as litho systems have the longest lead times and customers never want to step out of the queue for fear of not having litho capacity during an upturn. In addition, ASML also has the significant benefit of the EUV transition which we think remains on track.

Perhaps the biggest question from an investment perspective is how long and how deep is the downcycle. On the call, management echoed statements from their customers which suggested things getting better in H2 2019. However, there is zero evidence to suggest a second half recovery other than hope and good wishes. Even if memory prices stabilize it doesn’t mean that capex spending will pick up again. We would expect capex spending increases to only come after memory pricing has stabilized and perhaps started to move north again.

In the mean time we have a slowdown in foundry spending which will likely add to the length of the downturn as the negative Apple news trickles down through the supply chain.

The company did announce a 50% increase in dividend which will offset some of the negative news and Nikon settlement.

ASML the stock
As we have seen with other stocks, there is increasing down side resistance to bad news or worse than expected news. In addition, ASML has the benefit of more European investors who tend to be longer term and more resistant to near term negative news. European investors will also like the dividend increase. As such we expect the stock to trade flat to up as “it could have been worse” is the likely prevailing sentiment. We still favor the shares of ASML given their monopoly position, EUV progress and solid financial performance.

Collateral Damage
As we have been saying for a while, ASML and KLAC will be less impacted while LRCX and AMAT will be much more impacted by collapsing memory capex.

Lam, which is the poster child of memory making equipment, is the most impacted as at its peak memory was 84% of revenues. Given that TEL and Hitachi have a bigger share of Intel’s spend versus Lam, we do not expect Intel spending to offset memory weakness as it did at ASML. AMAT will be impacted more by weakened spend coming out of TSMC. LRCX reports tonight and we would expect them, to reset their guidance to a lower range than most are expecting, as analysts have been slow to reflect or admit to the reality of the down cycle.

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Having Your Digital Cake and Eating It Too

Having Your Digital Cake and Eating It Too
by Bill Montgomery on 01-24-2019 at 12:00 pm
Categories: Security

Anybody who’s ever read the iconic MAD magazine would be familiar with the wordless Spy vs Spy cartoon. First published in January, 1961, it features two agents involved in stereotypical and comical espionage activities. One is dressed in white, and the other in black, but they are otherwise identical. A parody of the political ideologies of the Cold War, the strip is now in its 68th year and continues to delight its loyal readers.

Nations spying on one another is as old as the creation of geographical borders. And when the notion of spying entered the public persona, through literature and film, it pretty much followed the same formula. Real (albeit fictional) characters were charged with the task of gathering intelligence on the “bad guys,” and using it to save the world. The Spy Who Loved Me, The Spy Who Came in From the Cold, Tinker, Tailor, Soldier, Spy. The list goes on and on.

In “Cold,” officer Alec Leamas (Richard Burton) offers a harsh appraisal of his profession: “What the Hell do you think spies are? Model philosophers measuring everything they do against the word of God or Karl Marx? They’re not. They’re just a bunch of seedy, squalid bastards like me …civil servants playing cowboys and Indians to brighten up their rotten little lives.”

Not any more

In the Digital era, as has happened in near every occupation – illicit or otherwise – spying has taken on a whole new persona. It’s no longer a secretive, person-on-person, in-your-face activity that might result in a few deaths or a terrifying car chase along the way. Spying in the Digital Age is a mainstream practice that is happening everywhere, every day. It involves sophisticated computers instead of dreary trench coats, keyboards are weapons, and the vulnerabilities that get exploited don’t involve moats, or complex door locks, or hard-to-crack safes. The vulnerabilities that spies use today are inherent in the very networks, and products and protocols that render our world digital. And compared to the risks that characterized the world of spying in the pre-digital age, the risks that stem from digital spying are of a magnitude that could literally destroy our world as we know it. The power grid, our water systems, nuclear sites, our transportation networks, our governments – every mission-critical digital service, application and product upon which the civilized world relies is subject to spying with a single goal in mind – weaken, maybe even destroy the “other guy.”

Here’s the Proof

If by now, you’re thinking that I might be overstating the amount of digital spying that’s taking place in today’s world, consider the following:

Canada (on behalf of 5-Eyes Nations) Spies on Brazil Mining Industry.
That’s right. Canada. And when the mild-mannered, “I’m sorry” nation is in on the spy game, you know for sure industrial and political espionage is rampant. Here’s another one:

China Spies (hacks) on US Navy Undersea Warfare Plans. Well, that’s one way to prevent a sneak attack. That’s akin to one Super Bowl finalist being given the playbook and game plan of its opponent before the big event. It kind of defeats the purpose of preparing a plan in the first place, doesn’t it?

Germany Accused of Spying on Austria.Germany spying on Austria? Really. Can’t we all just hit the hills and have a ski day?

And no surprise here, North Korea is accused of Spying on South Korea, and stealing its neighbour’s “South Korea-USA war plans.”

And of course, no list of cyber spying examples would be complete without some reference to the increasingly chilling US-China relationship, and the mounting concern about giant telecom manufacturer, Huawei, amidst claims that its 5G mobile network technology is filled with back doors, which will facilitate widespread spying by the Chinese government. I’m not equipped to comment on this one way or another. Smarter people than I will determine whether or not the threat from Huawei is real, but what is real is that the company’s 5G technology has already been banned in some countries and the American marketing machine is full bore against them.

Chinese authorities have pushed back on this, but not in the way one might think. As reported in Neikkie Asia Review, China may be spying on the US, but it learned from the best. According to China’s Foreign Ministry, “For a long time, the U.S. has systematically monitored and stolen confidential information from foreign governments, companies and individuals on a large scale through the Internet. That is an open secret.” Tit for Tat. Digital Spy vs Digital Spy.

The Birth of Digital Spying
So really, how is all this spying possible? The answer is pretty simple: via myriad built in technological “backdoors” that allow government security agencies (and spies who have discovered them) to openly spy on anybody using said technology. The practice, which has been denied for years, may have started when the US National Security Agency (NSA) insisted that backdoors be embedded in the world’s first commercial browser, released by Netscape in the mid 1990’s. One can argue that the rationale was solid at the time. The threat of “bad guys” getting access to this technology and using it to secretly communicate evil plans was very real, so it’s understandable that security agencies felt threatened by the emergence of the public Internet.

The practice of the NSA and other national security agencies inserting backdoors in digital technology continued over the years, usually under the banner of plausible deniability, but history confirmed that the practice was widespread and considered standard operating procedure. An article published in Toronto’s Globe and Mail clearly illustrated how the US and Canada’s security (aka spy) agencies worked together in approving and endorsing cryptographic technology that had a well-known backdoor. This technology was used by Blackberry, Cisco, RSA Security and many others, effectively rendering their products vulnerable to anybody who had access to the backdoor (and those clever enough to discover it).

Today, nations aren’t even pretending that backdoors don’t exist. They are banding together, demanding that technology companies open their digital kimonos to their national security forces. The “Five-Eyes” nations – USA, Canada, New Zealand, Australia, and the UK – recently issued a joint memo calling on their governments to demand tech companies build backdoor access to their users’ encrypted data — or face measures to force companies to comply.

Here’s what’s glaringly wrong with this thinking: security researchers have long said there’s no mathematical or workable way to create a “secure backdoor” that isn’t also susceptible to attack by hackers.

So, where does this leave our connected world? In a place that can only be categorized as a Digital Security Dilemma.

The Digital Cake
Hey, security agencies, didn’t your parents ever tell you that “you can’t have your cake and eat it too?” And if that old expression doesn’t resonate with you (or perhaps younger readers), here’s what it means in the context of today’s connected universe:

You can’t eliminate encrypted communication worldwide (i.e. create secret, hidden backdoors) for the sake of catching the bad guys (such as terrorists) when, in doing so, you create opportunities for every digital bad guy (hackers, spies, enemy nation states) to threaten our world by gaining access to those same backdoors. And trust me, the threats posed by the digital cybercriminals vastly outweighs those posed by evil drug dealers, and terrorist groups. The latter can certainly cause significant damage, and senseless loss of life, and that’s definitely of great concern. The former, on the other hand, could destroy our very way of life and kill millions in the process.

So, I believe the world’s leading nations need to make a choice: insist on technology backdoors and make our world even more vulnerable than it already is (because of earlier-created backdoors), or embrace nation-by-nation authenticated and encrypted communication for the greater good. And embracing secure cryptography doesn’t prevent you from tracking the bad guys. Use international laws, treaties and partnerships using good old-fashioned court orders that authorize you to spy on whomever you choose, whenever you like.

It’s the smart choice – the responsible choice.

You can’t have your digital cake and eat it too.

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Intel Swaggers at CES

Intel Swaggers at CES
by Daniel Payne on 01-24-2019 at 7:00 am
Categories: Events, General, Intel Foundry
11 Comments

Intel started out as a DRAM company using planar NMOS technology, then later on added EPROM and Microprocessors to the product mix. Their CPU technology enabled the dynamic growth of the PC industry starting with the IBM PC back in 1981 and continuing all of the way to this day. They long ago dropped out of the DRAM marketplace and began to diversify their chip offerings. Intel attends the annual CES show to draw attention to their chip know-how used in mobile, desktop, datacenter and automotive fields.

Gregory Bryantwas first up for Intel at CESand he was youthfully dressed in jeans and dark grey, long sleeves, extolling the virtues of the new Ice Lake chip, a 10nm product from the Client Computing Group. Here’s the list of cool features in Ice Lake for mobile computing (aka Laptops, Tablets):

  • Sunny Cove CPU Architecture
  • Generation 11 Integrated Graphics
  • Thunderbolt 3 I/O
  • WiFi 6
  • ML instructions added

Mixing heterogeneous cores on an SoC is in vogue as a way to balance power and performance, so Lakefield has five cores: One big CPU and then four smaller CPUs. Intel dubs this a Hybrid CPU.

Packaging for Lakefield is condensed by using a 3D approach with chiplets, and a marketing name of Foveros.

My engineering question with this 3D stacking is, how do they remove all of the heat generated in such a small area?

Bryant then held up a reference board using Lakefield and the whole thing fit into the palm of his hand, a pretty tiny PC motherboard.

Tony Werner from Comcast got the dress-code memo and also wore jeans and an open-collar shirt, and he talked about bringing 10 Gigabit speeds into homes and offices. Demos at CES showed Comcast routers pumping out 1+ Gigabit wirelessly using Intel technology inside.

Moving over to the Data Center Group at Intel we had Navin Shenoy talk about Cascade Lakeswith features like:

  • 48 cores
  • AI features – Deep Learning Boost
  • Optane Persistent Memory

His video demo showed 3D athlete tracking of runners, long jump and shot put using conventional cameras with analytics over-laid. The AI focus is in inferencing, and their Neural Network Processor for Inference (NNPI) is branded as Nervana, but you have to wait later in the year for details, today was just a tease.

Snow Ridge is a new SoC for 5G wireless access, planned for later this year. Shennoy showed a base station with a small form factor, the size of a paperback book.

Amnon Shashua spoke about autonomous driving and held up an EyeQ 5 board (Mobileye acquisition) that will be used in 2021 production, achieving Level 3-4 features.

Summary
Intel is in the data-centric era of computing, pursuing a $300B TAM market. The 9th generation of core products are coming for the desktop. Cascade Lakes is aimed for the mobile market. For the autonomous market the Mobileye acquisition has a new board called EyeQ5.

The big challenge of course is Intel actually delivering on all of the promises in a timely manner. Intel stock is still out-performing AMD over the past three months, but AMD beats Intel stock over the past 1 year and 5 year periods. Competition is healthy for the semiconductor industry.

View a video of Intel at CES, it lasts just 9:33.

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Contrarian Views on Quantum Computing

Contrarian Views on Quantum Computing
by Bernard Murphy on 01-23-2019 at 12:00 pm
Categories: General
6 Comments

I’m not opposed to the exotic ideas which capture public attention from time to time, but I do enjoy puncturing a popular expectation demanding every novel technology be a revolutionary breakthrough. I’ve already made my small contribution to driving a stake through the heart of claims that quantum computing (QC) will replace classical computing (it won’t) or that it will end security as we know it (unlikely). This still leaves a role for QC in some domains, but a couple of recent articles in Quanta magazine suggest even that muted expectation may be shaky.


The first blow came from a young (17) CS/Math major at UT who chopped the legs from under a QC algorithm for the recommendation problem. A paper published in 2016 had demonstrated a method that was exponentially faster than any known classical algorithm, raising hope that here, finally, was concrete proof that QC could do something practical far better than classical computing. But the UT teenager proved that some of the methods used in the QC approach could also be used in a classical approach, delivering almost comparable performance. Ouch. OK, one example doesn’t prove that QC isn’t useful; there can still be plenty of other applications where QC would tower above any possible classical algorithm. In fact another paper proves that (for another type of problem) QC can be demonstrably superior to classical computing. But it’s still kind of discouraging when one of the supposed star applications for QC turns out not to be a star at all.

The second possible blow suggests that effectively managing noise, at scale, through quantum error-correction (QEC) may be too expensive in practice or may even be theoretically impossible (though the author of this work acknowledges that his is a minority view). All systems are noisy and depend on the noise being managed down to an acceptable level. QC systems are particularly sensitive because they depend for their essential behavior on quantum coherence, which at the very simplest level means that a system can be in both of two possible quantum states simultaneously (think Schrödinger’s cat). Noise can break this coherence, collapsing the state into one or the other possibility, but no longer both. When this happens, QC becomes ineffective.

You can reduce thermal noise by dropping the QC to very low temperatures, which is why you always see these things submerged in liquid helium cryostats. Unfortunately, temperature isn’t the only source of noise. Quantum behavior is inherently noisy since it is probabilistic rather than deterministic; cooling doesn’t make this go away. There are yet more sources of noise but you get the point. So QC builders accept and adapt to the problem by adding QEC. Instead of using one physical qubit (quantum bit) per logical bit of information, they use multiple physical qubits per logical qubit, along with error-correction techniques between these multiple qubits. This might look like regular redundancy in safety-critical classical computing, but it’s a lot more tricky in QEC, since even looking at a qubit, much less correcting it, also breaks coherence.

I’ll skip the gory details, but two questions should be apparent at this point: how many physical qubits do I need per logical qubit, given realistic noise levels, and is this a fixed number or does it grow as the number of logical qubits grows? IBM announced a 50-qubit computer in 2017, which doesn’t sound like a lot, so I assume this does not factor in the redundant bits. One source estimates ~1,000 physical to logical qubits. Another credible source estimates that to apply Schor’s algorithm (a well-known QC algorithm) to factor a 2,000-bit number would require 10,000 logical qubits and 13,000 physical qubits per logical qubit. These are already daunting numbers and suggest a super-linear growth in physical to logical qubits, if you can trust the earlier estimate.

The contrarian (Gil Kalai) argues, and has proven for one class of computation, that this growth is unavoidably exponential. Even if he’s wrong in other cases and growth is slower but still faster than linear with logical qubits, this is still a problem given where we are today and expectations for QC. Which isn’t necessarily fatal since there seem to be many alternative implementations for physical qubits; possibly one or more of these might overcome this particular challenge. But it’s another potential setback and another cause for concern. The game is far from over, but it seems a little early to be breaking out the champagne.

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Accelerating 5G Design Innovation Through Simulation Workshop

Accelerating 5G Design Innovation Through Simulation Workshop
by Daniel Nenni on 01-22-2019 at 12:00 pm
Categories: 5G, Ansys, Inc., EDA, Events

DesignCon is coming up, kicking off the first of many industry conferences for the year. It’s at the Santa Clara Convention Center which is the best venue in Northern California. Not only is this a semiconductor crowd, it’s also a systems crowd covering chips, boards, and systems. More than 175 companies participate with an expected attendance of 5,000 people, I hope to see you there.

Even if your employer won’t cover the entry fee there is still plenty to do. The exhibit hall is always fun and there are workshops and other free events. A good example is the “Accelerating 5G Design Innovation Through Simulation Workshop”:

January 29, 2019
1:30 PM – 5:30 PM (PST)
Venue: Hyatt Regency
Room: Bayshore East/West

The next generation of wireless technology – driven by 5G – will transform the way we communicate, commute and collaborate with machines and humans alike in the near future. Ubiquitous connectivity, low latency and faster data rates are going to enable billions of more smart devices. These devices will be generating more data at the edge, transporting more data across the network and processing more data both at the edge and in the cloud. 5G network infrastructure will rely on high-frequency mmWave spectrum, massive MIMO, small cells and beamforming and beam tracking capabilities that will increasingly complicate the design of these electronics systems that must now absorb huge amounts of antenna data, support a variety of 5G air interfaces – such as massive Machine Type Communication (MTC), enhanced Mobile Broadband (eMBB), and Ultra-Reliable Communication (URC) and Low Latency – and offer significantly higher processing capabilities within a power and thermal constrained environment.

Electronics systems for 5G infrastructure will require fully integrated mmWave RF solution, advanced SoCs and state of the art 3D-IC and fan-out wafer-level packaging (FOWLP) technologies to deliver the required performance, power, system bandwidth and low latency. For these system-in-package designs, the chip needs to be designed in the context of the package and the overall system to deliver the highest performance for processing the huge amounts of data at lightning speed. Power integrity and signal integrity are critical for ensuring product success; however, they become increasingly challenging to achieve for these advanced system-in-package and 3D-IC designs. Also, addressing reliability challenges – including electromigration (EM), thermal-aware EM, thermal-induced mechanical stress, ESD and device aging- are key for 5G electronics systems that will enable mission-critical applications of the future like self-driving cars.

Attend this workshop to learn how ANSYS simulations can help you accelerate 5G design innovation across the spectrum of chip, package and system (CPS). Topics will cover simulation solutions for RF and antenna designs, electronics system reliability and chip-package-system co-analysis for power integrity sign-off for advanced packaging technologies – 3D-IC and FOWLP. Don’t miss this exciting opportunity to meet industry experts and get ahead in the race for 5G with ANSYS simulations.

DesignCon badge is NOT required, but pre-registration is a must to attend this workshop.

About DesignCon
DesignCon is the world’s premier conference for chip, board and systems design engineers in the high-speed communications and semiconductor communities. DesignCon, created by engineers for engineers, takes place annually in Silicon Valley and remains the largest gathering of chip, board and systems designers in the country. This three-day technical conference and two-day expo combines technical paper sessions, tutorials, industry panels, product demos and exhibits from the industry’s leading experts and solutions providers. More information is available at: www.designcon.com. DesignCon is organized by is organized by UBM, which in June 2018 combined with Informa PLC to become a leading B2B information services group and the largest B2B Events organizer in the world. To learn more and for the latest news and information, visit www.ubm.com andwww.informa.com

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TSMC and Semiconductors 2019 and Beyond

TSMC and Semiconductors 2019 and Beyond
by Daniel Nenni on 01-22-2019 at 7:00 am
Categories: Foundries, TSMC
10 Comments

TSMC has always been my bellwether and for 2019 I think we need to pay careful attention. Bad economic news has been spreading inside the fabless semiconductor ecosystem (tool and IP budgets have been tightening) but I think it is a bit premature. Let’s take a look at the TSMC 2018 Q4 earnings call and talk more about it in the comments section:

  • Q1 of $7.3B to $7.4B, down 14%
  • TSMC expects 2019 revenue to grow 1% to 3% compared to 6.5% in 2018
  • TSMC cites inventory congestion
  • TSMC expects weak demand until 2H19
  • TSMC 2018 CAPEX 10.5B ($10-11B 2019)
  • Predicts global GDP growth from 3.2% in 2018 to $2.6% in 2019
  • Predicts 2019 non memory semiconductor growth at 1%
  • Predicts long term TSMC growth of 5%-10% CAGR

Revenue by technology Q4 2018:

  • 7-nanometer 23%
  • 10-nanometer 6%
  • 16/20-nanometer 21%.
  • 28-nanometer and below 67%

Full year revenue by technology 2018:

  • 7-nanometer 9% (25% in 2019)
  • 10-nanometer 11%
  • 16/20-nanometer 23%
  • 28-nanometer and below 63%

Contribution by application in 2018

  • Communications 56% (+1%)
  • Industrial/Standard 23% (+3%)
  • Computer 14% (+61%)
  • Consumer 7% (-17%)

(Smartphones 45%, HPC 32%, IoT 6%, Automotive 5%. 5G and AI will kick in this year and next).

Comments from CC Wei:
Our N5 technology development is well on track, with customer tape-out schedule for first half 2019 and volume production ramp in first half 2020. We are already in preparation for N5’s ramp. All applications that are using 7-nanometer today will adopt 5-nanometer. In addition, we are expecting the customer product portfolio at N5 and see expanding addressable market opportunities. We expect more applications in HPC to adopt N5. Thus we are confident that N5 will also be a large and long-lasting node for TSMC.

TSMC all but locked up 7nm and making the transition from 7N to 5N should pave the way for another big node for TSMC. Samsung however will be better prepared to compete with TSMC at 5nm so there may be a bigger split. For example, AMD is a big upside for TSMC 7nm in 2H 2019 but from what I am told AMD will split manufacturing between TSMC and Samung at 5nm. The same thing with Qualcomm and others. As I have mentioned before, multi-sourcing has always been the foundation of the fabless semiconductor ecosystem and at the leading edge it is TSMC and Samsung.

Now let’s take a look at the Analyst Q&A:

The first question was on CAPEX. TSMC had previously said CAPEX of $10-12B would be sufficient for 5-10% growth. In 2018 TSMC CAPEX was $10.5B and in 2019 CAPEX is expected to be $10-11B. TSMC is a master of fab and equipment re-use so I do not see a CAPEX problem here as others have. For example N7+ will be a very quick node so the fab space and EUV machines will be reallocated to 5nm in short order.

The next question was on revenue by application which I found interesting. From what I have seen on SemiWiki, automotive is more of a bubble than a major growth area. IoT of course is booming. AI I guess is part of HPC but is overshadowed by the cryptocurrency bubble burst so you hardly notice it.

Roland Shu
Thank you. Happy New Year. First question is, C.C., you said for the mobile business this year, you still expect some growth, but under your overall year, on the whole year revenue growth just slightly. So how about the growth of the other platform products, IoT, HPC and automotive?

C.C. Wei
Okay, Roland, you asked a good question. Smartphone grows slightly. IoT grows double-digit. Automotive will be flat. HPC, if we’re excluding the cryptocurrency mining, HPC also grows slightly. But cryptocurrency is a big drop from 2018 to 2019. So if we put the cryptocurrency together in the HPC, it’s a big drop. It’s almost a double-digit.

The rest of the questions were about trying to figure out why the slowdown happened and what TSMC sees for the future. In my experience, at the beginning of a slowdown such as this, smart CEOs bite the bullet and give very conservative forecasts moving forward so they only have to deliver bad news once a year. This is what TSMC is doing in my opinion, being very conservative.

In my opinion smartphone sales have been sluggish due to market saturation, price gouging, and lack of innovation and will continue to be sluggish until we see 5G phones. Everyone will want 5G and very soon everyone will need 5G to keep up with the new features the extra bandwidth will bring. 5G really is a known term amongst the masses. I heard kids calling parents 3G as an insult when 4G came out.

Price is a big issue for me. We used to get big breaks on new phones from carriers with 2 year contracts. Now we don’t so we hold on to them longer. The carriers now offer low monthly payments on new phones in lieu of discounts but you still have to pay taxes on the retail price. It is a better deal but not by much and a big departure from when we got free phones for a new contract.

Bottom line:I don’t think this year will be as bad for the semiconductor industry as some are predicting. We absolutely got ahead of ourselves with the last two double digit growth years and 1H 2019 will be the correction. But moving forward I too see great promise in 5G and AI for companies making chips, absolutely.

You can see the whole transcript HERE.

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DAC 2019 Will Be Even More IP Friendly!

DAC 2019 Will Be Even More IP Friendly!
by Eric Esteve on 01-21-2019 at 12:00 pm
Categories: Events, IP, IPnest
1 Comment

DAC 2019 will take place in Las Vegas (June 2-6) this year before moving back to San Francisco in 2020 and for the next 5 years. Considering the various rumors about merging the conference, or even the end of DAC, this is a very good news! Not only for Design Automation, but, as we will see, for the IP industry.

In fact, if we look at the exhibitor list for the last DAC, we realize that the number of EDA start-up has declined. This is not a scoop, as this decline has started a while ago, reflecting the fact that the EDA industry is mature and consolidated. The good news is that IP start-up are now replacing EDA start-up as exhibitors, and the exhibition floors are still very busy, but populated by IP companies…


IPnest has made some research about the IP and EDA market evolution in respect with the semiconductor market, from 2006 to 2017. To be noticed, the above graphic (source: IPnest) show IP and EDA value as a percentage of the total semiconductormarket, but less memory. Why removing the memory (DRAM and Flash) market? Just because this market is non-only cyclical but also completely hectic!

The main observation is that the EDA market is almost a constant value, 1.87% in average for the last 10 years, when the IP market is growing, year after year. Obviously, the semiconductor market (less memory) is constantly growing, and EDA is growing as well.

But IP is a growing function of a growing market. In other words, the IP market is growing more than the EDA market. According with IPnest predictions, this will be true for the next 10 years or so, the time it takes for IP externalization to reach an asymptote, like the EDA market did in 2000. IPnest has calculated that the IP Market CAGR 2007-2027 will be 10,4%…

If you translate this data into an industry behavior, there is still room for enough IP market growth to justify the emergence of enough start-up to populate DAC exhibition floors for many years!

Coming back to Las Vegas in June 2019, we -the DAC IP Committee- are in the process of finalizing the various sessions dedicated to IP, invited presentation or panels, like below listed (not exhaustive and preliminary):

  • AI for Automotive
  • AI for Datacenter (in the cloud)
  • Low power AI (for IoT/Edge?)
  • Low power in advanced nodes
  • High speed serial data (56/112G, PAM4)
  • RISC V
  • Security IP
  • Functional Safety IP
  • Verification IP
  • Foundry Platform IP (Panel)
  • High performance memory interfaces

As you can see, AI came in first, not really a surprise, and IoT has almost vanished compared with the same list a couple of years ago. As far as I am concerned, I am not surprised by the fact that IoT doesn’t generate as mush interest as in 2015 or 2016. IoT is not really one market, but rather a collection of multiple markets (industrial, medical, smart home/city, etc.). Maybe some analysts have dreamed about IoT, thinking that it will be as large as wireless phone… but not IPnest.

There will be fast growing markets in 2020-2030, like automotive or data center, that’s why we can see “AI for automotive” and “AI for data center”. AI is a technique, not a market, and this technique will be applied to the most demanding market in term of processing power, automotive and data center, as well as in multiple smaller markets, in my opinion…

I expect this 56[SUP]th[/SUP] DAC to be a great event, even more exciting than the 55[SUP]th[/SUP] DAC, at least for people like me working in the IP business. I expect to see many good presentations or panels focusing on IP related topics, and I can tell you that the DAC IP Committee is working hard to select attractive topics, mostly targeting emerging IP or techniques. We are doing our best to make you happy next June!

See you in Las Vegas (and don’t worry “What happens in Vegas stays in Vegas”!)

From Eric Esteve from IPNEST

About DAC
The Design Automation Conference (DAC) is recognized as the premier event for the design of electronic circuits and systems, and for electronic design automation (EDA) and silicon solutions. A diverse worldwide community representing more than 1,000 organizations attends each year, represented by system designers and architects, logic and circuit designers, validation engineers, CAD managers, senior managers and executives to researchers and academicians from leading universities. Close to 60 technical sessions selected by a committee of electronic design experts offer information on recent developments and trends, management practices and new products, methodologies and technologies. A highlight of DAC is its exhibition and suite area with approximately 200 of the leading and emerging EDA, silicon, intellectual property (IP) and design services providers. The conference is sponsored by the Association for Computing Machinery (ACM), and the Institute of Electrical and Electronics Engineers (IEEE), and is supported by ACM’s Special Interest Group on Design Automation (ACM SIGDA) and IEEE’s Council on Electronic Design Automation (CEDA).

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At Last, Package and Chip integration for RF Design

At Last, Package and Chip integration for RF Design
by Tom Simon on 01-21-2019 at 7:00 am
Categories: Cadence, EDA

It seems that it has always been that there were packages and ICs, and in the design tool world “never the twain shall meet”. The tools for designing packages were completely separate from the tools used to design IC’s. This was so profoundly true that even after Cadence merged with Valid Logic back in the early 90’s, their Allegro Board products were not integrated with the Cadence Virtuoso IC tools. It’s not that they did not try. Cadence CEO Joe Costello tried valiantly to coax the two solutions into a common front end. I was there and lived through the turmoil. Perhaps the time was not ripe, therefore satisfying the need could be delayed.

However, many changes have occurred in electronics design that have made the integration between package and chip design essential. Nowhere is this truer than in the RF design space. Not only are the chips running faster, but more complex interconnections between them in the package and on interposers requires coordinated design, verification and closure. Lastly, the addition of multi-technologies like GaAs, SiGe, GaN, etc. have driven RF designs to multiple substrates, necessitating multichip packaging.

One of the main challenges created in RF flows is the need for EM analysis, both for interconnect and for a wide range of passive device types. This requirement spans the hierarchy, and includes on-chip devices such as MOM and MIM caps, inductors, critical nets and transmission lines. Also, EM effects can be profound for package nets. Finally, due to close proximity in some cases it is necessary to look at EM coupling between package and on chip structures. Even though there are EM tools that can address each of these domains, they often are hard to set up and present problems when it comes to inserting the generated models back into the design flow while maintaining design consistency across multiple views.

Design teams are often working on each of the pieces of a design concurrently, which makes the exchange of design data and the ongoing modifications essential. I’m sure everyone reading this has a horror story of a multi-chip module encountering issues due to out of sync design data that comes from batch transfers of interface specifications.

Cadence finally came back to the issue of module, package and chip design integration and the results look like just what is needed. Cadence has the benefit of strong, but separate, design solutions for each of these. Now with their Cadence Virtuoso RF Solution they have created the links in Virtuoso schematic to capture the entire schematic, including package and module. With a single golden schematic for the entire design they eliminate one of the major problem spots in the flow.

Even more interesting is how they added package layers to the IC technology file. With one unified technology file there is no more need to kludge together ad hoc layers in Virtuoso to add packaging information. Cadence has even added primitives for arcs and all angle routing so that package geometries can be represented without translation errors or dead-end data movement.

With all the elements captured in an integrated system, teams can be certain that interface changes will propagate through the hierarchy and ensure that everything stays in sync.

Cadence may be creating a revolution in RF design. They have also done extensive integration with board, package and chip EM solvers to ensure that high frequency effects are modeled and easily included in simulations. There are so many parts to this consolidated flow that it is hard to summarize. I suggest looking at a white paper they have written that digs deeper into the many facets of this solution.

After having seen the tumult after the Cadence – Valid merger, I can say that it is satisfying to see the vision finally coming to fruition. These changes would seem to cement Cadence leadership in the RF design space.