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The Evolution of the Extension Implant Part III

The Evolution of the Extension Implant Part III
by Daniel Nenni on 05-06-2019 at 7:00 am
Categories: Events, FinFET, Semiconductor Services, Threshold Systems

The problem of traditional FinFET Extension Implant doping concerns the awkward 3-dimensional structure of the fin. Because the Extension Implant defines the conductive electrical pathway between the Source/Drains and the undoped channel portion of the fin, it is essential that the fin be uniformly doped all three of its surfaces (the two sides and the top of the fin). The use of a short Amorphous Carbon implant mask helps enormously with this implant because is enables a steep +/- 30º implant angle that allows more of the dopant to be retained on the fin as discussed in part one of this series (refer to figure #1).


Figure #1

Implanting the fin with such a steep double implant allows each side of the fin to be adequately doped, but has the disadvantage that the top of the fin experiences both of these implants (refer to figure #2). This means that the top of the fin is doubly doped and becomes the most conductive fin element. This results in non-uniform fin conductivity that adversely affects transistor performance.


Figure #2

An alternative doping methodology that results in uniform doping on all three sides of the fin is required. This task can be accomplished with two additional masking and implant steps, a nitride deposition and etch operation, followed by a selective oxidation.

The process begins with a masking operation that covers up the N-Wells and exposes the NMOS devices located n the P-Wells. This is followed by an Arsenic implant at 90 degrees into the NMOS fins. (refer to figure #A). This will dope the top of the NMOS fins. However, because the fins are very vertical at the 14/10nm nodes, very little if any dopant will be implanted into the fin sidewalls.

Next, the photoresist is stripped and new photoresist is patterned that covers the P-wells and exposes the N-Wells where the PMOS transistors are located. A 90 degree Boron implant followed by a Carbon locking implant dopes only the top of the PMOS fins (refer to figure B).

Next, a thin nitride layer is blanket deposited across the wafer using Atomic Layer Deposition (refer to figure C). The nitride layer is then etched in a highly anisotropic etch that forms nitride spacers on the gate electrodes and the fins. This is followed by a mild oxide etch that removes the thin layer of oxide on top of the gate electrodes and the top of the fins and exposes the underlying silicon in these areas (refer to figure D).

The wafers then undergo an oxidation step. The Nitride acts as an oxygen barrier and prevents oxide from growing on the surfaces that it covers. However, on the exposed surfaces (the top of the fins and the top of the Gate Electrode) a thick layer of oxide grows (refer to figure E). This thick layer of oxide will act as an implant mask in the following Extension implant operations.

The nitride layer is then stripped from the wafer (refer to figure F). This step is followed by the deposition and patterning of a hard mask that after patterning will cover the N-Well and expose the NMOS devices in the P-Well.

The Extension implants for the NMOS devices are then conducted as illustrated in Figure #3.


Figure #3

However, since the top of the fins are now covered in a thick oxide, only the sidewalls of the fins will experience the +/- 30 degree double implant. This is because although the dose of the Extension implant is very high (10[SUP]15[/SUP] ion/cm[SUP]2[/SUP]), the energy of this implant is very low. The dopant from this implant will be able to penetrate the thin oxide along the sidewalls of the fin, but not the thicker oxide at the top of the fin (refer to figure #4).


Figure #4

The Extension implant is then repeated for the PMOS fins using Boron and Carbon.

This methodology ensures that the fins experience a uniform Extension implant across the top and on both sides of the fin and avoids the double implant of the fins on their upper surfaces that is common in more conventional implant schemes. However, such uniform fin doping is accomplished at the expense of significantly greater processing.

For more information on this topic and for detailed information on the entire process flows for the 10/7/5nm nodes attend the course “Advanced CMOS Technology 2019” to be held on May 22, 23, 24 in Milpitas California.

Also read: The Evolution of the Extension Implant Part 2

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Tesla: The Day the Industry Stood Still

Tesla: The Day the Industry Stood Still
by Roger C. Lanctot on 05-05-2019 at 7:00 am
Categories: Automotive
1 Comment

Tesla Motors held an investor event at its Palo Alto headquarters. CEO Elon Musk and a series of Tesla executives announced a new in-house developed microprocessor (already in production and being deployed in Tesla vehicles) and its plans and progress toward autonomous vehicle operation.

Tesla Autonomy Day Live Stream

To be clear – all Tesla vehicles are now getting the new processor the performance of which will be defined by software delivered via over-the-air updates. It’s a minor point for Tesla, which has been doing software updates for years. It’s a monumental change in business practices for the industry.

Musk and his colleagues held forth from a stage in front of an audience of rapt analysts and investors whose silence reflected the collective inhale being experienced across the entire automotive industry and supply chain. Musk’s announcement marked yet another key turning point for the company. He said Tesla is now focused completely on enabling automated driving with the objective of launching a fleet of robotaxis by the end of 2020.

The new microprocessor was the focal point of the event. Musk and his lead designer noted multiple performance advantages over the existing Nvidia hardware in use in older Tesla vehicles. (Nvidia released a blog today challenging and correcting some of Tesla’s claims.)

The event was preceded by Easter weekend news of a Tesla Model S bursting into flames in a parking garage in China and rumors of declining vehicle shipments in advance of Wednesday’s earnings report. Unfazed, Musk took the occasion to cast some shade on erstwhile supplier Nvidia while pointing out what he described as “the fool’s errand” of trying to use lidar technology to enable automated driving.

Despite the fact that so many organizations large and small are working on self-driving car technology, Musk has emerged from the autonomous driving mosh pit as a thought leader matched only in media-attention-getting magnitude by Amnon Shashua of Mobileye. Interestingly, both Shashua and Musk share the same vision of camera-centric automated driving enhanced with ultrasonic and forward facing radar sensors.

There are other contenders for the thought leadership throne in automated driving including Kyle Vogt at Cruise Automation, Jensen Huang of Nvidia, Gil Pratt at Toyota Research Institute, George Hotz formerly of Comm.ai, and Sebastian Thrun and Anthony Levandowski formerly of Google. But only Musk can stop the automotive industry in its tracks with his pronouncements regarding the future of autonomy commanding, as he does, a fleet of hundreds of thousands of connected vehicles.

Musk is the ultimate disruptor – if not outright shredder – of the automotive industry. His investments in electrification are an existential threat to 50% of the industry’s existing internal combustion-centric supply chain.

A Tesla’s engine is its microprocessor and Musk made clear his intention to use that engine in combination with crowd sourced data to refine the software necessary to go with the new chip to enable automated driving. Musk’s core message from the event was that the new chip is capable of enabling full automation, once the software is refined and deployed.

The key takeaways from yesterday’s event included:

  • Lidar is a dead-end, waste of time for autonomous vehicle development
  • High definition maps are unnecessary to enabling automated driving
  • The software code in the new processors are cryptographically signed meaning they can only run Tesla-approved/signed code
  • The new processors are already being built into Model S, X, Y, and 3 vehicles
  • Work on the next generation processor is already well under way, a couple years from completion and will offer a 3X performance gain

Post-event, a bruised Nvidia was quick to note in a blog that its own AI computing hardware offers competitive performance and is “available for the industry to build on” – unlike Tesla’s.

Musk’s pronouncements detonate in the midst of an autonomous vehicle development environment coming to grips with deferred expectations. The growing recognition of the enormity of the technical challenge appears to have caused many market participants to reconsider their public comments or their inclination to say anything at all about their methodology or strategy.

In this environment, Musk’s voice remains loud, clear and unwavering – and automotive executives know they can’t afford not to listen. We may not know for quite some time whether Musk is right on all points. But alone, among many contenders, he is outspoken about his own strategy and opinionated regarding paths – or the path – to autonomy.
Musk, like his competitors, is facing a major leap of faith and technical achievement to deliver fully automated driving. But he must face the fact that lives have been lost in his pursuit of autonomy and skeptics remain.
Only one thing is clear. Musk stands alone in the global industry with the greatest trove of automated and non-automated driving data. At the event he even went so far as to question the efficacy of using simulation software as an alternative to the data collected from human driven miles.

So Musk would and will do without lidar, high definition maps, nvidia, and simulation in his autonomous quest. It remains to be seen how tolerant consumers, investors and regulators will remain should fatalities or flaming cars continue to manifest. Musk remains focused and affirmative – unfortunately he is also fallible. We can only hope no more lives will be lost to Musk’s margin of error.

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TSMC and Samsung 5nm Comparison

TSMC and Samsung 5nm Comparison
by Scotten Jones on 05-03-2019 at 7:00 am
Categories: Foundries, Samsung Foundry, Semiconductor Services, TechInsights, TSMC
9 Comments

Samsung and TSMC have both made recent disclosures about their 5nm process and I though it would be a good time to look at what we know about them and compare the two processes.

A lot of what has been announced about 5nm is in comparison to 7nm so we will first review 7nm.

7nm
Figure 1 compares Samsung’s 7LPP process to TSMC’s 7FF and 7FFP processes. The rows in the table are:

  • Company name
  • Process name
  • M2P – metal 2 pitch, this is chosen because M2P is used to determine cell height
  • Tracks – the number of metal two pitches in the cell height
  • Cell height – the M2P x Tracks
  • CPP – contacted polysilicon pitch
  • DDB/SDB – double diffusion break (DDB) or single diffusion break (SDB). DDB requires an extra CPP in width at the edge of a standard cell
  • Transistor density – this is uses the method popularized by Intel that I have written before where two input NAND cell size and scanned flip flop cell sizes are weighted to give a transistors per millimeter metric
  • Layers – this is the number of EUV layers over the total number of layers for the process
  • Relative cost – using Samsung’s 7LPP cost as the baseline we compare the normalized cost of each process to 7PP. The cost values were calculated using the IC Knowledge – Strategic Cost Model – 2019 – revision 01 versions for a new 40,000 wafers per month wafer fabs in either South Korea for Samsung or Taiwan for TSMC
    Figure 1. 7nm comparison

     

    Looking at figure 1 it is interesting to note that Samsung’s 7LPP process is less dense than either of TSMC’s processes in spite of using EUV and having the smallest M2P. TSMC more than makes up for Samsung’s tighter pitch with a smaller track height and then for 7FFP a SDB. For TSMC 7FF without EUV moving to 7FFP with EUV reduces the mask count and adds SDB improving the density by 18%.

    Now that we have a solid view of 7nm we are ready to look forward to 5nm:

    5nm
    Both Samsung and TSMC have started taking orders for 5nm with risk production this year and high-volume production next year. We expect both companies to employ more EUV layers at 5nm with 12 for Samsung and 14 for TSMC.

    Samsung has said their 5nm process offers a 25% density improvement over 7nm with a 10% performance boost or 20% lower power consumption. My understanding is the difference between 7LPP and 5LPE for Samsung is a 6-track cell height and SDB. This results in a 1.33x density improvement.

    This contrasts with TSMC who announced a 1.8x density improvement and a 15% performance improvement or 30% lower power. I recently saw another analyst claim that Samsung and TSMC would have similar density at 5nm, that one really left me scratching my head given that the two companies have similar 7nm density and TSMC has announced a much larger density improvement than Samsung. My belief is that TSMC will have a significant density advantage over Samsung at 5nm.

    Figure 2 summarizes the two processes using the same metrics as figure 1 with the addition of a density improvement versus 5nm row.

    Figure 2. 5nm comparison

     

    From figure 2 you can see that we expect TSMC to have a 1.37x density advantage over Samsung with a lower wafer cost!

    Another interesting item in this table is TSMC reaching 30nm for M2P. We have heard they are being aggressive on M2P with numbers as low as 28nm mentioned. We assumed 30nm as a slight relaxation from the 28nm number to produce the 1.8x density improvement, TSMC had at one time said 5nm would have a 1.9x density improvement.

    Conclusion
    We believe TSMC’s 5nm process will significantly outperform Samsung’s 5nm process in all key metrics and represent the highest density logic process in the world when it ramps into production next year.

    For more information on TSMC’s leading edge logic processes I recommend Tom Dillinger’s excellent summary of TSMC’s technology forum available here.

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Webinar: ISO 26262 Compliance

Webinar: ISO 26262 Compliance
by Daniel Payne on 05-02-2019 at 12:00 pm
Categories: EDA, Events, Perforce

To me the major idea of ISO 26262 compliance is ensuring that requirements can be traced throughout the entire design and verification process, including the use of IP blocks. The first market application that comes to mind with ISO 26262 is automotive, with its emphasis on safety because human lives are at stake. Since necessity is the mother of all invention, we have software vendors that have focused on automating this big challenge of traceability of requirements, design data and verification results. Methodics is a software vendor focused on this area, and they are organizing a webinar:

  • Achieving a Traceable Semiconductor Design and IP Methodology for ISO 26262 Compliance
  • Tuesday, May 14, 2019 at 10AM Pacific Time
  • Registration Online

Percipient is the IP Lifecycle management tool discussed in the webinar, and it provides a fully traceable environment for tracking IP in a company while engineers go about their design and verification tasks: analog, digital, software, embedded software, final assembly. The beauty of using Percipient is that traceability is already built-in to the process.

Speakers

Michael Munsey
VP Business Development and Strategic Accounts
Methodics Inc.

Michael Munsey has over 25 years experience in Engineering Design Automation and Semiconductor Companies. Prior to joining Methodics, Michael was Senior Director of Strategy and Product Marketing for semiconductors, software life cycle management, and IoT at Dassault Systemes. Along with strategic initiatives, he was responsible for business development, partnerships, and cross-industry initiatives such as automotive electronics, and M&A in the above areas. Michael began his career with IBM as an ASIC designer before making the move over to EDA where he has held various senior and executive-level positions in marketing, sales, and business development. He was a member of the founding teams for Sente and Silicon Dimensions, and also worked for established companies including Cadence, VIEWLogic, and Tanner EDA. Michael received his BSEE from Tufts University.


Rien Gahlsdorf
Director of Application Engineering
Methodics Inc.

Rien Gahlsdorf is the Director of Application Engineering at Methodics where he endeavors to create a clear customer understanding of the product, and a clear product alignment with the customer. Rien brings over 20 years of experience in product development and support, technical sales, and analog and RF design to his role at Methodics, which he joined in 2016. Rien received his MBA from Boston University.


Vishal Moondhra
VP of Solutions Engineering
Methodics Inc.

Vishal Moondhra has over 20 years experience in Digital Design and Verification. He has held engineering and senior management positions with innovative startups including IgT and Montalvo, and large multinationals including Intel and Sun. In 2008, Vishal co-founded Missing Link Tools, which built the industry’s first comprehensive DV management solution, bringing together all aspects of verification management. Methodics acquired Missing Link Tools in 2012.

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The Evolution of the Extension Implant Part II

The Evolution of the Extension Implant Part II
by Daniel Nenni on 05-02-2019 at 7:00 am
Categories: Events, FinFET, Semiconductor Services, Threshold Systems

The use of hard masks instead of photoresist for the Extension implant is an effective way to optimize the amount of dopant that is retained along the fin sidewalls for those fins that border along photoresist edges (as discussed in Part 1 of this series).

However, hard masks do nothing to address the dominant problem driving steeper implant angles, namely the increasing height of fins and the decreasing space between them. As illustrated in figure #1, the fins get taller and closer together at each new node.


Figure #1

This configuration is advantageous because taller fins provide greater W-effective and more closely spaced fins increases transistor density per-unit area. However, tall, closely spaced fins present a serious problem for Extension implants because they dictate the use of very steep implant angles (refer to figure #2).

Such steep implant angles greatly reduce the retention of dopant on the fin sidewall due to ricocheting as illustrated in #3.

Since high-dose and uniform doping of the fin Extension regions is central to FinFET performance, this issues needs to be addressed. The solution is to take advantage of not only the wafer’s tilt during the Extension implant, but also the “twist” of the wafer.

It is important to realize that since all of the fins are formed using Self-Aligned Double patterning (SADP), or Self-Aligned Quadruple patterning (SAQP), the fins consist of a series of parallel straight lines. So it is possible to rotate, or “twist”, the wafer to alter the implant angle in addition to just tilting the wafer away from the vertical. Figure #4 illustrates the difference between wafer tilt and twist.


Figure #4

Because it is much easier to tilt a wafer rather than to tilt the angle of the implant beam, the +/- 25˚ tilt of the Extension implant is accomplished simply by tilting the angle of the wafer.

However, it is also possible to exploit the parallel line nature of the fin orientation and twist the wafer during this implant as well as tilt it. By twisting the wafer during the Extension implant a substantial advantage is gained because it allows the implant beam deeper access into the micro-canyons formed by the tall, adjacent fins.

This is accomplished by breaking down the two Extension implants into four separate implants, two for each side of the fin. The wafer is still tilted (approximately +/-25˚ for a 10nm fin) but between each of the four Extension implants the wafer is twisted, first to 335˚, then to 25˚, then to 155˚ and finally to 205˚ as illustrated in figure #5.

 


Figure #5

So now both the PMOS and the NMOS Extension implants consist of four implants with the following configurations:

To understand how this implant configuration provides an advantage when realizing the Extension implant, consider the illustration in figure #6.

Figure #6

In figure #6 the NMOS Extension implant is oriented at 25˚ from the vertical. However the wafer is twisted counterclockwise to an angle of 335˚. This allows the dopant to more easily reach into the deep micro-canyons form by the tall fins and at the same time maintain a sufficient vertical angle to minimize ricocheting of dopant off of the fin sidewalls. (Notes that for the sake of clarity figure #6 only illustrates one fin being implanted. In fact all of the fins would experience this implant.) The fact that the dopant is approaching the fin from an angle, and not from a direction that is orthogonal to the fin, is the central advantage of this methodology.

Significant shadowing will occur due to the angle of the implant in relation to the tall Gate Electrode structures, but this issue will be taken care of in the second part of this implant (refer to figure #7).


Figure #7

Figure #7 depicts phase two of the four-part NMOS Extension implant. The implant tilt angle is still 25˚, but the wafer has been twisted clockwise to an angle of 25˚. This implant will compensate for any Gate shadowing that occurred in phase one of the implant and completes the implantation of this side of the fins.

Figures #8 and #9 illustrate the opposite sides of the fins experiencing the phases three and four of the Extension implant. The wafers are twisted to angles of 155˚ and 205˚ respectively.


Figure #8


Figure #9

In figures #8 and #9 the wafer is tilted to -25˚ from the vertical and so the dopant is being implanted from the opposite side of the fin. This is a two-phase implant and the implant angle and the two different twists ensure that the opposite sides of the fins are adequately doped and that any shadowing caused by the proximity of the tall Gate Electrodes is minimized or eliminated.

This same four-step process would be repeated for the PMOS fins.

This process ensures that adequate dopant is implanted into the sidewalls of the fins during the Extension implant with a minimum of shadowing by exploiting the fact that all of the fins form straight, parallel lines and are implanted at a twist angle.

It does involve a slightly more complex process of four implants instead of two for each set of fins, but all four implants could be processed sequentially in the implanter, so the increase in cycle time would be minimal.

Information on this topic and detailed information on the entire process flows for the 10/7/5nm nodes will be presented at the course “Advanced CMOS Technology 2019” to be held on May 22, 23, 24 in Milpitas California.

Also Read: The Evolution of the Extension Implant Part I

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Complex Validation Requires Scalable Measures

Complex Validation Requires Scalable Measures
by Alex Tan on 05-01-2019 at 12:00 pm
Categories: EDA, Synopsys

The famous Olympic motto Citius, Altius, Fortius, which is the Latin words for “Faster, Higher, Stronger” to a considerable degree can be adapted to our electronics industry. Traditionally the fundamental metrics we used for measuring the quality of results (QoRs) are performance, power, and area (PPA). Amidst the current rise of AI augmented silicon content in many applications, the metrics might need to include the element of “Smartness”. Designed silicon such as cloud or edge based processors and accelerators have shown a trend of faster performance, higher capacity or bandwidth (scalability) and incorporating higher AI content. The smartness level factor may eventually become a key differentiator for the sprouting AI based silicons.

Physical Verification and DRC Rule Explosion
Within the silicon ecosystem, capturing design inceptions into transistor fine geometries involves stepping through several design abstractions and demands successive validations. In many instances, it requires both top-down planning and bottom-up build processes. The similar bottom-up approach gets repeated at the foundry side through the scheme of layered based process implementation. For advanced process nodes, foundries utilize complex front-end-of-line layer stacks and deploy multi-patterning lithography on many masks, which translates to more required masks. Increased overall mask layers (FEOL, MEOL, BEOL) normally implies higher cost and increased complexity for fabrication, backend implementation, and verification.

Elastic Scalability and Cloud Expansion
While AI silicon solution track closely to the targeted application or targeted software, in physical verification, the number of process layers and interconnection due to increased pins from emerging applications such as multi-core and AI neural networks have given rise to increased DRC rules to check. In addition, increased embedded IPs to satisfy various data transaction protocols have intensified the demand for more capacity expansion. Synopsys IC Validator physical verification has an intelligent scheduler, which is an essential feature for its elastic scalability. The smart load sharing technology regularly monitors jobs and determines job health. Based on the job needs and the compute server constraints, it will make on-the-fly adjustment to subsequent CPU cores addition or removal.

The memory-aware scheduling also estimates memory requirements in advance and schedules jobs based upon the requested hardware configurations. It enables optimal utilization of compute farms available resources for physical verification jobs, regardless of the current off-peak or max-peak state. It leaves control to designers to align with their project schedule demand. For example, given an IC validator job requiring 100 CPUs, it may take the first 10 available CPU for use and dynamically add more CPUs as they become available. Similarly, it could free-up some CPUs as the job is nearing completion if need be, as illustrated in figure 2.


IC Validator has also been enabled to be a “cloud-ready” physical signoff solution and has been deployed on the cloud for production tapeouts. The chart illustrates the runtime of a production 7nm design can be scaled down to less than a day with scaled cores on AWS.

Steps to Ensure Convergence
From the methodology standpoint, there are three approaches available to improve physical verification productivity:

• Run concurrently during the IP and block-level design capture.
Using physical verification Fusion, DRC and manufacturing issues are caught much earlier in the design cycle, reducing or eliminating late-stage surprises close to tapeout. IC Validator’s seamless integration with Fusion Compiler and IC Compiler II enables layout auto-correction interface –which identifies DRC violations such as DPT decomposition violations and initiates automatic repairs. The applied corrections are then validated with signoff foundry runsets using IC Validator Physical verification, further eliminating iterations. This will allow block owners to identify potential failures while the design is still being edited, incurring smaller validation cycle. The DRC run will take seconds to complete and available for a quick fix as the layout view tool has been streamlined with IC Validator Live DRC engine.


• Run full-chip verification on early integrated design version.
Today’s SoC’s consist of numerous blocks, spanning from mixed-signals cells, memory, third-party IP’s and I/O cells. IC Validator Explorer DRC is capable of providing a quick assessment of the full-chip design and provides actionable feedback to fix found problems. As each block may get validated in a bottom-up fashion, when compiled into a full-chip level, additional problems might surface, such as missing blockages, misalignment issue, and block revision controls to name a few.

Designers could utilize IC Validator Explorer DRC to quickly prescreen the full design using a baseline set of DRC rules to gauge the design readiness prior to a full-blown signoff check. If the outcome is relatively clean, it will continue to progressively complete all required DRC signoff checks. This full-chip approach was found to deliver 5X faster runtime at 5X fewer cores versus the traditional approach, which translates to a few needed hours for typical full chip 7nm designs with 16 or 32 cores. A dramatic improvement, even when it is still considered in ‘dirty state’.

• Run on more CPU resources.
The third option is to provide room for scalability to take place. As IC Validator scalability index indicates quite effective CPU utilization, overall job sign-off speedup could be attained through core expansion.

Integrated Analytic Facilities at Chip and Block Levels
To easily identify the macro-problems to fix (such as overlaps), IC Validator includes an error heatmap visual topological assessment. The color gradient heatmap shows various hot spots intensity starting from high (in red), progressing to cool areas (in blue) –analogous to the congestion hot-stop in P&R.

All of the above-described measures work in tandem to deliver convergence to physical design signoff. For more details on IC Validator please refer check HERE.

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Compute at the Edge

Compute at the Edge
by Bernard Murphy on 05-01-2019 at 7:00 am
Categories: AI, Ceva, IoT, IP, Mobile, Security

At first glance, this seems like a ho-hum topic- just use whatever Arm or RISC-V solution you need – but think again. We’re now expecting to push an awful lot of functionality into these edge devices. Our imaginations don’t care about power, performance and cost; everything should be possible so let’s keep adding cool features. Of course reality has to intrude at some point; edge nodes often aren’t plugged into a wall socket or even into a mobile-phone-class battery. Power and recharge constraints (as well as cost) don’t necessarily mean our imagined products are unattainable but they do require more careful thought in how they might be architected.

Start first with what we might want to build. Cameras must continue to at least keep pace with your cellphone camera so have added remote control and voice-activation. VR and AR headsets need to recognize your head and body position to correctly orient a game scene or position AR overlays in real-world scenes. Headphones are becoming increasingly smart in multiple ways, recognizing you through the unique structure of your ear canal, recognizing voice commands to change a playlist or make a call, detecting a fall or monitoring heart rate and other vital signs. Home security systems must recognize anomalous noises (such as breaking glass) or anomalous figures/movement detected on cameras around the house.

Each of these capabilities demands multiple compute resources. First and most obviously, you need communication; none of these wonderful products will be useful standalone. In some cases, communication may be through relatively short-range protocols such as Bluetooth or Wi-Fi, in other cases you may need cellular support, through NB-IoT for small packet transfers (such as from a parking meter) or through LTE or 5G for broadband support (drones or 4k/8k video streaming for example). Whichever protocol you choose, you need a modem, and for cellular it probably needs to support MIMO with beam-forming to ensure reasonably connectivity.

Modems are specialized beasts, usually best left to the experts. You could buy a standalone chip, but then your product needs at least 2 chips (one for everything else). That makes it more expensive and more of a power hog, definitely not extending to a 10-year battery life, maybe not even 10 hours. The best choice for PPA is an integrated modem with tight power management, especially for the power-amp.

Now think about compute for sensing, where a good example is a 9-axis sensor, fusing raw data from a 3-axis accelerometer, 3-axis geomagnetic sensor and 3-axis gyroscope, such as you might use in a VR/AR headset. Together these sensors can provide information on orientation and movement with respect to a fixed Earth frame, which is just what you need for a realistic virtual gaming experience or orienting virtual support information and controls against a real machine you want to manage.

This fusion requires yet more compute, heavily trigonometric along with filtering, which could be accomplished in a variety of ways but needs to be more or less always-on during use. You could make some allowance for human response times, perhaps allowing for update every 1/60[SUP]th[/SUP] of a second, but that’s still pretty continuous demand. Again you could get this through an integrated chip solution, but for all the PPA reasons mentioned earlier an ideal solution would be embedded in your one-chip SoC. And since the fusion algorithms are math-intensive, a DSP is a pretty natural fit.

One more example – AI embedded in your product. AI is ramping fast in edge-based devices in a lot of use-cases; here let’s consider just voice-control. This needs multiple components – audio beamforming, noise management and echo-cancellation, and trigger-word recognition at minimum. Beamforming, echo cancellation (especially indoors) and noise filtering are all DSP functions. Perhaps you could prove these are possible on some other platform but you’d never compete with DSP-based products. Trigger-word recognition gets into neural nets (NN), the heart of AI. And in many cases it needs to be combined with voice recognition – recognizing who is speaking rather than what is being said. Again, DSPs are a well-recognized low-power, high-performance option in the NN implementation spectrum, above CPUs, FPGAs and GPUs (and below full-custom solutions like the Google TPU).

GPUs are very well known in the AI domain, but primarily in NN training and in prototypes or cost/power-insensitive applications. Mobile VR headsets you may have seen are likely to be based (today) on these platforms but they’re expensive (~$1k for the chip alone) and deliver short battery lives (I haven’t heard the latest on the Magic Leap, but I do know you need to wear a battery on your belt and they have been cagey about time between charges – maybe a few hours at most).

Finally, full operation of your ground-breaking product requires some level of remote functionality but you probably don’t want to depend on it being up all the time. And probably you would prefer that sensitive information (health data, credit cards, face-id, etc) not travel over possibly insecure links to possibly hackable cloud-based platforms. You don’t want your semi-autonomous drone crashing into a tree because it lost line of sight with a base station or flying off to someone else who figured out how to override your radio control. That means you need more intelligence and more autonomy in the device, for collision avoidance, for path finding and for target object detection, without having to turn to the cloud. Which means need for more AI at the edge.

All of the functions I have talked about here are supported on DSP platforms and some can potentially be multiplexed on a single DSP. You probably still want a CPU or MCU as well, for administration, authorization, provisioning and whatever other algorithms you need to support. Not so much for the AI; you can get basic capabilities on CPUs/MCUs but they tend to be quite limited compared with what you can find on DSP platforms. If you want to learn more about what is possible in communication, sensor fusion and AI at the edge, check out CEVA.

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TSMC Technology Symposium Review Part II

TSMC Technology Symposium Review Part II
by Tom Dillinger on 04-30-2019 at 10:00 am
Categories: Events, Foundries, TSMC
6 Comments

TSMC recently held their annual Technology Symposium in Santa Clara. Part 1 of this article focused on the semiconductor process highlights. This part reviews the advanced packaging technologies presented at the symposium.

TSMC has clearly made a transition from a “pure” wafer-level foundry to a supplier of complex integrated system modules – or according to C.C. Wei, CEO, TSMC is a leading source for “nano-mass production innovations”. (Taiwan News, 4/23/19) This is the outcome of years of R&D investment – for example, see the discussion on 3D stacking in the “SoIC” section below.

Dr. Doug Yu, VP, Integrated Interconnect and Package R&D provided a detailed update. Dr. Yu classified the package technologies into unique categories – “front-end” 3D chip integration (SoIC) and “back-end” packaging advances (CoWoS, InFO). Additionally, he addressed the progress in pad pitch and Cu pillar/SnAg bump lithography, specifically mentioning the automotive grade reliability requirements.

Here’s a brief recap of the TSMC advanced packaging technology status.

Bumping
TSMC continues to advance bump technology, with 60-80um bump pitch achievable (for smaller die).

CoWoS
The initial TSMC 2.5D packaging offering was chip-on-wafer-on-substrate (CoWoS), which has enabled very high-performance system integration by bringing memory “closer to the processor”.

  • >50 customer products
  • TSMC is developing “standardized” configurations – e.g., 1 SoC with 2 or 4 HBMs, evolving to >2 SoCs with 8 HBM2Es (96GB @ 2.5TB/sec – wow.)

Correspondingly, TSMC will be expanding the maximum 2.5D interposer footprint from a max of 1X reticle (~50×50) to 3X (~85×85), with a 150um bump pitch.

  • The silicon interposer supports 5 metal layers and a (new) deep trench capacitor – see the figure below.

InFO
TSMC continues to evolve the Integrated FanOut (InFO) package offerings. Recall that InFO is a means of integrating (multiple) die using a “reconstituted wafer” molding compound to provide the package substrate for RDL patterning. InFO builds upon the traditional small-package WLCSP technology to enable (large area) redistribution interconnect and high bump count – see the figure below.

InFO-PoP supports stacking of a logic die and a DRAM die on top of the base, using through-InFO-vias (TIV) to connect the DRAM to the metal layers. InFO-PoP development has focused on improving the pitch and aspect ratio (vertical-to-diameter) of the TIVs.

InFO-on-Substrate offerings attach a (multi-die) InFO module to a (large area) substrate, leveraging the multiple reticle stitching technology developed for CoWoS.

SoIC (“front-end” 3D integration)
The big packaging announcement at the symposium was the introduction of the “front-end” 3D die stacking topology, denoted as SoIC (System-on-Integrated Chips).

SoIC is a “bumpless” interconnect method between multiple die. As depicted in the figure below (from an early R&D paper from TSMC), Cu pads from a base die and exposed Cu “nails” from the (thinned) top die utilize thermo-compression bonding to provide the electrical connection. (An appropriate underfill material is present at the die-to-die interface, as well.)

  • Through-silicon vias in the die provide connectivity, with a very tight pitch.
  • Both face-to-face and face-to-back die connectivity are supported. The “known good” stacked die may be different sizes, with multiple die on a stacked layer.
  • TSMC showed a mock-up of a 3-high vertical SoIC stack.
  • EDA enablement is available: physical design (DRC, netlisting/LVS), parasitic extraction, timing, IR/EM analysis, signal integrity/power integrity analysis, thermal/materials stress analysis.
  • The qualification target for the SoIC package offering is YE’2019. (My understanding from a separate TSMC announcement is SoIC volume availability will be in 2021.)

Dr. Yu also indicated, “The front-end SoIC module will be able to be integrated as part of a back-end 2.5D offering, as well.”

Summary
Both 2.5D and InFO “back-end” package offerings continue to evolve.

Yet, for me the highlight was the introduction of the tight-pitch, Cu compression-bonded full-3D stacked die of the SoIC topology. The available circuit density (per mm**3) will be very appealing. The challenges to leverage this technology will be considerable, though, from system architecture partitioning to complex electrical/thermal/mechanical analysis across the stacked die interfaces.

Moore’s Law is definitely alive-and-well, although it will require 3D glasses. 😀

-chipguy

Also read: 2019 TSMC Technology Symposium Review Part I

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2019 TSMC Technology Symposium Review Part I

2019 TSMC Technology Symposium Review Part I
by Tom Dillinger on 04-30-2019 at 7:00 am
Categories: Events, Foundries, TSMC
5 Comments

Each year, TSMC conducts two major customer events worldwide – the TSMC Technology Symposium in the Spring and the TSMC Open Innovation Platform Ecosystem Forum in the Fall. The Technology Symposium event was recently held in Santa Clara, CA, providing an extensive update on the status of advanced semiconductor and packaging technology development. This article briefly reviews the highlights of the semiconductor process presentations – a subsequent article will review the advanced packaging announcements.

First, some general items that might be of interest:

Longevity
TSMC was founded in 1987, and has been holding annual Technology Symposium events since 1994 – this was the 25th anniversary (which was highlighted prevalently throughout the Santa Clara Convention Center). “The first Silicon Valley symposium had less than 100 attendees – now, the attendance exceeds 2000.”, according to Dave Keller, President and CEO of TSMC North America.

Best Quote of the Day
Dr. Cheng-Ming Lin, Director, Automotive Business Development, describes the unique requirements of TSMC’s automotive customers, specifically with regards to continuity of supply over a much longer product lifetime. He indicated,

“Our commitment to legacy processes is unwavering. We have never closed a fab or shut down a process technology.” (Wow.)

Best Quip of the Day
Dr. Y.-J. Mii, Senior Vice President of Research and Development / Technology Development , highlighted three eras of process technology development, as depicted in the figure below from his presentation.

In the first phase, Dennard scaling refers to the goal of scaling FEOL linear lithographic dimensions by a factor of “s” (s < 1) in successive process nodes, achieving an improvement of (1 / s**2) in circuit density, measured as gates / mm**2. The next phase focused on material improvements, and the current phase centers on design-technology co-optimization – more on that shortly.

In a subsequent presentation at the symposium, Dr. Doug Yu, VP, Integrated Interconnect and Packaging R&D, described how advanced packaging technology has also been focused on scaling, albeit for a shorter duration. “For over 10 years, packages have also offered two-dimensional improvements to redistribution layer (RDL) and bump pitch lithography. With the multi-die, 3D vertical stacking package technology we’re describing today – specifically, TSMC’s SoIC offering – we are providing vast improvements in circuit density. S is equal to zero. Or, in other words, infinite scaling.” 😀 (Indeed, it is easy to foresee product technologies starting to use the metric “gates / mm**3” .)

Here is a brief recap of the TSMC advanced process technology status.

N7/N7+
TSMC announced the N7 and N7+ process nodes at the symposium two years ago. (link)

N7 is the “baseline” FinFET process, whereas N7+ offers improved circuit density with the introduction of EUV lithography for selected FEOL layers. The transition of design IP from N7 to N7+ necessitates re-implementation, to achieve a 1.2X logic gate density improvement. Key highlights include:

 

  • N7 is in production, with over 100 new tapeouts (NTOs) expected in 2019
  • Key IP introduction: 112Gbps PAM4 SerDes
  • N7+ is benefitting from improvements in sustained EUV output power (~280W) and uptime (~85%). “Although we anticipate further improvements in power and uptime, these measures are sufficient to proceed to N7+ volume ramp.”, TSMC said.
  • TSMC has focused on defect density (D0) reduction for N7. “The D0 improvement ramp has been faster than previous nodes, at a comparable interval after initial production volume ramp.”, according to TSMC.
  • TSMC illustrated a dichotomy in N7 die sizes – mobile customers at <100 mm**2, and HPC customers at >300 mm**2.
  • To my recollection, for the first time TSMC also indicated they are tracking D0 specifically for “large chips”, and reported a comparable reduction learning for large designs as for other N7 products.
  • N7+ will enter volume ramp in 2H2019, and is demonstrating comparable D0 defect rates as N7.

“Making 5G a Reality”
TSMC invited Jim Thompson, CTO, Qualcomm, to provide his perspective on N7 – a very enlightening presentation:

  • “N7 is the enabler for the 5G launch, as demonstrated in our latest Snapdragon 855 release.”
  • “5G MIMO with 256 antenna elements supports 64 simultaneous digital streams – that’s 16 users each receiving 4 data streams to a single phone.”
  • “Antenna design is indeed extremely crucial for 5G, to overcome path loss and signal blockage. There are new, innovative antenna implementations being pursued – in the end, it’s just math, although complex math for sure.”
  • “There’s certainly lots of skepticism about the adoption rate of 5G. Yet 5G is moving much faster than 4G did – at a comparable point in the rollout schedule, there were only 5 operators and 3 OEM devices supporting 4G, mostly in the US and South Korea. Currently, there are over 20 operators and over 20 OEM devices focused on 5G deployment, including Europe, China, Japan, and Southeast Asia.”
  • “And, don’t overlook the deployment of 5G in applications other than consumer phones, such as ‘wireless factory automation’. Communication to/from industrial robots requires high bandwidth, low latency, and extremely high availability. Consider the opportunities for manufacturing flexibility in a wire-free environment, enabled by 5G.”

N6
TSMC introduced a new node offering, denoted as N6. This node has some very unique characteristics:

  • design rule compatible with N7 (e.g., 57mm M1 pitch, same as N7)
  • IP models compatible with N7
  • incorporates EUV lithography for limited FEOL layers – “1 more EUV layer than N7+, leveraging the learning from both N7+ and N5”
  • tighter process control, faster cycle time than N7
  • same EDA reference flows, fill algorithms, etc. as N7
  • N7 designs could simply “re-tapeout” (RTO) to N6 for improved yield with EUV mask lithography
  • or, N7 designs could submit a new tapeout (NTO) by re-implementing logic blocks using an N6 standard cell library (H240) that leverages a “common PODE” (CPODE) device between cells for an ~18% improvement in logic block density
  • risk production in 1Q’20 (a 13 level metal interconnect stack was illustrated)
  • although design rule compatible with N7, N6 also introduces a very unique feature – “M0 routing”

The figure below illustrates a “typical” FinFET device layout, with M0 solely used as a local interconnect, to connect the source or drain nodes of a multi-fin device and used within the cell to connect common nFET and pFET schematic nodes.


I need to ponder a bit more on the opportunity use M0 as a routing layer – TSMC indicated that EDA router support for this feature is still being qualified.

N6 strikes me as a continuation of TSMC’s introduction of a “half node” process roadmap, as depicted below.


A half-node process is both an engineering-driven and business-driven decision to provide a low-risk design migration path, to offer a cost-reduced option to an existing N7 design as a “mid-life kicker”.

The introduction of N6 also highlights an issue that will become increasingly problematic. The migration of a design integrating external IP is dependent upon the engineering and financial resources of the IP provider to develop, release (on a testsite shuttle), characterize, and qualify the IP on a new node on a suitable schedule. N6 offers an opportunity to introduce a kicker without that external IP release constraint.

N5
The process node N5 incorporates additional EUV lithography, to reduce the mask count for layers that would otherwise require extensive multipatterning.

 

  • risk production started in March’19, high volume ramp in 2Q’20 at the recently completed Gigafab 18 in Tainan (phase 1 equipment installation completed in March’19)
  • intended to support both mobile and high-performance computing “platform” customers; high-performance applications will want to utilize a new “extra low Vt”(ELVT) device
  • 1.5V or 1.2V I/O device support
  • an N5P (“plus”) offering is planned, with a +7% performance boost at constant power, or ~15% power reduction at constant perf over N5 (one year after N5)
  • N5 will utilize a high-mobility (Ge) device channel

Advanced Materials Engineering
In addition to the N5 introduction of a high mobility channel, TSMC highlighted additional materials and device engineering updates:

  • super high-density MIM offering (N5), with 2X ff/um**2 and 2X insertion density
  • new low-K dielectric materials
  • metal Reactive Ion Etching (RIE), replacing Cu damascene for metal pitch < 30um
  • a graphene “cap” to reduce Cu interconnect resistivity

An improved local MIM capacitance will help to address the increased current from the higher gate density. TSMC indicated an expected single-digit % performance increase could be realized for high-performance (high switching activity) designs.

Nodes 16FFC and 12FFC both received device engineering improvements:

  • 16FFC+ : +10% perf @ constant power, +20% power @ constant perf over 16FFC
  • 12FFC+ : +7% perf @ constant power, +15% power @ constant perf over 12FFC

NTO’s for these nodes will be accepted in 3Q’19.

TSMC also briefly highlighted ongoing R&D activities in materials research for future nodes – e.g., Ge nanowire/nanoslab device channels, 2D semiconductor materials (ZrSe2, MoSe2) – see the figure below (Source: TSMC).

Manufacturing Excellence
Dr. J.K. Wang, SVP, Fab Operations, provided a detailed discussion of the ongoing efforts to reduce DPPM and sustain “manufacturing excellence”. Of specific note were the steps taken to address the demanding reliability requirements of automotive customers. Highlights of Dr. Wang’s presentation included:

“Since the introduction of the N16 node, we have accelerated the manufacturing capacity ramp for each node in the first 6 months at an ever-increasing rate. The N7 capacity in 2019 will exceed 1M 12” wafers per year. The N10/N7 capacity ramp has tripled since 2017, as phases 5 through 7 of Gigafab 15 have come online.”

“We have implemented aggressive statistical process control (measured on control wafer sites) for early detection, stop, and fix of process variations – e.g., upward/downward shifts in baseline measures, a variance shift, mismatch among tools. We have established 2D wafer profile measurement criteria, and in-line monitoring and comparison to an “acceptance” profile across each wafer.”

“The DDM reduction rate on N7 has been the fastest of any node.”

“For automotive customers, we have implemented unique measures to achieve the demanding DPPM requirements. We will ink out good die in a bad zone. And, there are SPC criteria for a maverick lot, which will be scrapped.”

“We will support product-specific upper spec limit and lower spec limit criteria. We will either scrap an out-of-spec limit wafer, or hold the entire lot for the customer’s risk assessment.” (See the figures below. Source: TSMC)



Automotive Platform
TSMC has developed an approach toward process development and design enablement features focused on four platforms – mobile, HPC, IoT, and automotive. Dr. Cheng-Ming Lin, Director, Automotive Business Unit, provided an update on the platform, and the unique characteristics of automotive customers.

Growth in semi content
Dr. Lin indicated, “Automotive systems will require both advanced logic technologies for ADAS, such as N16FFC, and advanced RF technologies for V2X communications. Although the CAGR for cars from now to 2022 is expected to be only ~1.8%, the CAGR for the semiconductor content will be 6.9%.”

He continued, “The L1/L2 feature adoption will reach ~30%, with additional MCU’s applied to safety, connectivity, and EV/hybrid EV features. There will be ~30-40 MCU’s per vehicle. “ (In his charts, the forecast for L3/L4/L5 adoption is ~0.3% in 2020, and 2.5% in 2025.)

“The adoption rate for the digital dashboard cockpit visualization system will also increase, driving further semiconductor growth – 0.2% in 2018 to 11% in 2025.”

L2+
The levels of support for automated driver assistance and ultimately autonomous driving have been defined by SAE International as “Level 1 through Level 5”. Perhaps in recognition of the difficulties in achieving L3 through L5, a new “L2+” level has been proposed (albeit outside of SAE), with additional camera and decision support features.

“An L2+ car would typically integrate 6 cameras, 4 short-range radar systems, and 1 long-range radar unit, requiring in excess of 50GFLOPS graphics processing and >10K DMIPS navigational processing throughput.”

N16FFC, and then N7
The 16FFC platform has been qualified for automotive environment applications – e.g., SPICE and aging models, foundation IP characterization, non-volatile memory, interface IP. The N7 platform will be (AEC-Q100 and ASIL-B) qualified in 2020. “Automotive customers tend to lag consumer adoption by ~2-3 years, to leverage DPPM learning – although that interval is diminishing. We anticipate aggressive N7 automotive adoption in 2021.”,Dr. Lin indicated.

“The TSMC RF CMOS offerings will be used for SRR, LRR, and Lidar. The 16FFC-RF-Enhanced process will be qualified for automotive platforms in 2Q’20.”

IoT Platform
The TSMC IoT platform is laser-focused on low-cost, low (active) power dissipation, and low leakage (standby) power dissipation. Dr. Simon Wang, Director, IoT Business Development, provided the following update:

Process Roadmap

  • 55ULP, 40ULP (w/RRAM): 0.75V/0.7V
  • 22ULP, 22ULL: 0.6V
  • 12FFC+_ULL: 0.5V (target)
  • introduction of new devices for the 22ULL node: EHVT device, ultra-low leakage SRAM

The 22ULL SRAM is a “dual VDD rail” design, with separate logic (0.6V, SVT + HVT) and bitcell VDD_min (0.8V) values for optimum standby power.

The 22ULL node also get an MRAM option for non-volatile memory.

Note that a new methodology will be applied for static timing analysis for low VDD design. The stage-based OCV (derating multiplier) cell delay calculation will transition to sign-off using the Liberty Variation Format (LVF).

The next generation IoT node will be 12FFC+_ULL, with risk production in 2Q’20. (with low VDD standard cells at SVT, 0.5V VDD).

RF
TSMC emphasized the process development focus for RF technologies, as part of the growth in both 5G and automotive applications. Dr. Jay Sun, Director, RF and Analog Business Development provided the following highlights:

  • For RF system transceivers, 22ULP/ULL-RF is the mainstream node. For higher-end applications, 16FFC-RF is appropriate, followed by N7-RF in 2H’20.
  • Significant device R&D is being made to enhance the device ft and fmax for these nodes – look for 16FFC-RF-Enhanced in 2020 (fmax > 380GHz) and N7-RF-Enhanced in 2021.
  • New top-level BEOL stack options are available with ‘elevated’ ultra thick metal for inductors with improved Q.
  • For sub-6GHz RF front-end design, TSMC is introducing N40SOI in 2019 – the transition from 0.18um SOI to 0.13um SOI to N40SOI will offer devices with vastly improved ft and fmax.

Summary
There was a conjecture/joke going around a couple of years ago, suggesting that “only 7 customers will be able to afford to pursue 7nm designs, and only 5 customers at 5nm”.

Clearly, the momentum behind N7/N6 and N5 across mobile communication, HPC, and automotive (L1-L5) applications dispels that idea. TSMC is investing significantly in enabling these nodes through DTCO, leveraging significant progress in EUV lithography and the introduction of new materials.

Part 2 of this article will review the advanced packaging technologies presented at the TSMC Technology Symposium.

-chipguy

Also read: TSMC Technology Symposium Review Part II

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Free Webinar: Analog Verification with Monte Carlo, PVT Corners and Worst-Case Analysis

Free Webinar: Analog Verification with Monte Carlo, PVT Corners and Worst-Case Analysis
by Tom Simon on 04-29-2019 at 4:00 pm
Categories: EDA, Events, MunEDA

The letters “PVT” roll of the tongue easily enough, belying the complexity that variations in process, temperature and voltage can cause for analog designs. For semiconductor processes, there are dozens of parameters that can affect the viability of a design. It would be easy enough to optimize a circuit with only one or two varying parameters. However, the high number of varying parameters operating on each device in a design creates a huge multidimensional problem.

The baseline approach is to use Monte Carlo, randomly selecting process variables based on the distribution function for each. This brute force approach can require enormous amounts of time and compute resources, so over the years more sophisticated methods have been developed to shorten the process.

MunEDA is a leading provider of solutions for analyzing variability and its effects on circuit operation and yield. They have developed highly effective solutions based on statistical analysis theory that are practical and save time. With the high volumes involved with modern consumer devices, even failures on the order of parts per million are unacceptable. So, it is vitally important that designers have the right tools to perform analysis up to and beyond six-sigma.

MunEDA will be presenting a free live webinar on the topic of Analog Verification with Monte Carlo, PVT Corners and Worst-Case Analysis on May 8[SUP]th[/SUP] at 10AM PDT, there will also be presentations for the Asia and European time zones, to make viewing convenient.

The webinar will be moderated by MunEDA’s Andreas Ripp, and the presenter will be Dr. Michael Pronath, also from MunEDA. The webinar is intended for full-custom circuit designers, project leaders and managers responsible for design verification and full custom design for yield. They will discuss the pros and cons of a range of techniques to predict circuit yield and robustness. Also, they will highlight the applicability of the techniques to actual circuit design problems.

It will definitely be worthwhile to sign up for this webinar and to lean about this important topic.