SemiWiki – Page 258 – The Open Forum for Semiconductor Professionals

June 28, 2022July 2, 2022

Intel Foundry Services Puts PDKs in the Cloud

Intel Foundry Services Puts PDKs in the Cloud
by Daniel Nenni on 06-28-2022 at 10:00 am
Categories: Foundries, Intel Foundry
3 Comments

Intel announced today that they are partnering with cloud and EDA companies to better enable their foundry business. This is a natural extension of the Accelerator ecosystem program announced earlier. More and more chip designs are being done in the cloud and from my experience cloud based designs are better. Some companies use the cloud for reduced time-to-market, some for lower cost, and other companies rely on the seemingly unlimited compute resources for optimum PPA and to ensure first time silicon for complex designs.

While I have not had a personal experience with IFS I have heard some very good things by others who are engaged. I’m also very appreciative that IFS is participating in conferences including DAC and SEMICON WEST. In fact, IFS is the ONLY foundry at DAC this year so I expect their booth will be busy.

At the Intel 4 briefing I was amazed at the transparency which Scott Jones noted in his write up: Intel 4 Deep Dive. The dozen or so comments are worth reading, absolutely. Let’s hope this leads to a whole new level of technology transparency for foundries.

IFS will be using the Intel 16 (an optimized version of Intel 22nm, which was the first FinFET process to hit production), Intel 3, and 18A. You can see the latest IFS slide deck from the 2022 Investor Meeting HERE.

Here are the quotes associated with the press release. I know most of these people and have high regards for what they say so this is worth reading:

“By leveraging the scalability of cloud-based design environments, the IFS Cloud Alliance will enable broader access to Intel’s advanced process and packaging technologies. Our partnerships with leading cloud providers and EDA tool suppliers will provide a flexible and secure platform where customers can scale compute requirements instantly on production- proven design environments in the cloud.” Randhir Thakur, president of Intel Foundry Services

“We are excited to be collaborating with Intel in the launch of the IFS Cloud Alliance. We share a common goal to make semiconductor design and verification more scalable, and more accessible to a wide range of design teams, with the security and performance needed for reduced IC time-to-market and increased quality.” David Pellerin, director of Semiconductor Industry Solutions, Amazon Web Services

“Our close collaboration with Intel Foundry Services has brought together advanced node manufacturing with cloud computing and collaboration technologies, to establish a foundation for the next round of growth in the semiconductor industry. By joining Intel Foundry Services’ Cloud Alliance, Microsoft is proud to expand on that collaboration to provide a secure and scalable path to advanced silicon manufacturing. This is the latest chapter in the partnership between Intel and Microsoft that stretches back more than 40 years.” William Chappell, CTO, Mission Engineering, and vice president, Mission Systems, Microsoft Corp.

“Ansys’ comprehensive suite of interoperable, scalable multiphysics solutions plays a key role in IFS’ first design flow supported in the cloud. We look forward to continuing our long-standing collaboration with Intel to advance semiconductor design by ensuring that chip designers can access Ansys’ gold standard multiphysics solution via the cloud regardless of their chosen EDA workflow.” John Lee, vice president and general manager of the Semiconductor, Electronics, and Optics Business Unit, Ansys

“Cadence has longstanding leadership providing EDA solutions in the cloud and has successfully enabled thousands of customers to accelerate their innovation with our proven cloud solutions. Using the industry-leading, production-proven Cadence Cloud portfolio, which features highly flexible business models, customers have increased engineering productivity, significantly decreased turnaround times and improved overall cost efficiency. By joining the Intel Foundry Services Cloud Alliance, we’re enabling our mutual customers to leverage the scalable compute power of the cloud with our production-proven portfolio along with Intel’s advanced process and packaging technologies in a secure design environment.” Mahesh Turaga, vice president, Cloud Business Development, Cadence

“Siemens EDA has been optimizing tools for large-scale compute environments for more than 15 years. As part of the IFS Cloud Alliance ecosystem, Siemens EDA will work closely with cloud vendors, customers and Intel Foundry Services to leverage that experience to simplify the path to higher quality of results in less time. Siemens EDA is pleased to join the IFS Cloud Alliance ecosystem, and we look forward to extending the benefits of our industry-leading products and services to companies of all sizes who use Intel’s manufacturing services.” Craig Johnson, vice president, EDA Cloud Solutions, Siemens EDA

“Chip design is moving to the cloud at lightning speed. The Intel Foundry Services Cloud Alliance program will further accelerate the semiconductor industry’s adoption of cloud-based design, ensuring that engineers can continue to use the best technology, tools and flows as they move design to the cloud. We are collaborating with IFS as part of the Cloud Alliance, to enable our mutual customers to deploy our tools quickly and efficiently on the public cloud and help them deliver better products faster while meeting increasingly complex design and verification challenges.” Sandeep Mehndiratta, vice president, Enterprise Go-To-Market & Cloud, Synopsys.

Also read:

Intel 4 Deep Dive

An Update on In-Line Wafer Inspection Technology

0.55 High-NA Lithography Update

June 28, 2022January 11, 2023

Imec Buried Power Rail and Backside Power Delivery at VLSI

Imec Buried Power Rail and Backside Power Delivery at VLSI
by Scotten Jones on 06-28-2022 at 6:00 am
Categories: Events, Semiconductor Services, TechInsights
2 Comments

At the VLSI Technology Symposium Imec presented on Buried Power Rails (BPR) and Backside Power Delivery (BSPD) in a paper entitled: “Scaled FinFETs Connected by Using Both Wafer Sides for Routing via Buried Power Rails”. I recently had a chance to interview one of the authors, Naoto Horiguchi about the work. I have interviewed Naoto several times in the past and presented alongside him at conferences and I always enjoy our conversations, he is very knowledgeable and easy to talk to.

Power Delivery is a growing problem at the leading edge. Two key issues addressed in this work are:

On the metal 2 level there are power and ground rails at the top and bottom of standard logic cells. These rails are wider than routing lines to minimize the IR drop. Because half of each line is in the standard cell the wide lines limit cell scaling. As we transition to nanosheets this issue must be addressed to get to cells with less than 6-tracks.
The upper metal layers of a process are very wide and provide global routing of power, but with 16 or more metal layers becoming common, there is a big IR drop bringing the power down through the chain of vias between each metal layer.

In this work the first problem is addressed with BPR, BPR replaces wide-thin power rails in metal 2, with tall-narrow power rails buried in the substrate. This technique reduces the area lost at the cell boundaries and for nanosheets can enable a 5-track or smaller cell.

The second piece is BSPD where the global power routing is done on the back of the wafer and then routed through the wafer with nano-Through Silicon Vias (nTSV). In order to minimize the IR drop the wafer must be very thin and the impact of extreme wafer thinning on the devices is explored in this work.

Figure 1 summarizes the scenarios:

Figure 1. Power Delivery Scenarios.

The addition of BPR reduces the dynamic IR drop by 26% and the addition of BSPD improves the IR drop by an additional 75%, see figure 2.

Figure 2. Dynamic Power Drop.

Static IR drop is reduced by 23% by BPR and an additional 95% by adding BSPD, see figure 3.

Figure 3. Static Power Drop.

In previous BPR work Imec has used Ruthenium (Ru) for the BPR metal but in this work, they used Tungsten (W). Naoto said that Ru will be necessary at some point to support further scaling but at the scale of this work W was fine and is a well known metal in fabrication with well-defined cleans.

In figure 4, cross sections of the resulting structure and connections are shown. What I find amazing in this work is how incredibly thin the wafer is at less than one-micron. This enables low resistance for the nTSV.

Figure 4. Cross Section and Device Connections.

In figure 5 the process is illustrated for BPR and BSPD.

Figure 5. BPR and BSPD Process.

Some comments about the process flow:

An epitaxial process is used to deposit a silicon-germanium (SiGe) layer used as an etch-stop layer and then on top of that the silicon device layer is formed.
The W BPR is formed in the wafer.
The devices are fabricated.
The wafer is bonded to a carrier wafer.
Backgrind followed by a wet etch stopping on the SiGe layers is used to thin the wafer.
nTSVs are formed.
The BSPD is formed.
The wafer is annealed to recover performance.

I asked Naoto about the material used to bond the wafers together because the BSPD temperatures are likely too high for most temporary bonding materials. He said a Chemical Vapor Deposited (CVD) dielectric is used. This is based on the wafers not being separated after the process, this means signal lines would have to be routed in from the backside along with power.

Authors note: another question I recently looked into is how you precisely align the nTSV to the front side so they land on the BPR. I had a conversation with a contact at ASML and they said with the wafer this thin the aligners can “see” the front side alignment marks through the wafer. There are some distortion issues, but they are manageable. Long term there is interest in landing nTSV right on source/drains and that will require more work on alignment accuracy.

The bulk of this work was to evaluate device performance and the impact of extreme wafer thinning on the devices. Naoto said in some tests they thinned wafers until they hit the shallow trench isolation and they still got good device performance after annealing the wafer.

Authors note, both Intel and TSMC have announced BSPD for 2nm generation processes, clearly that is an emerging technology.

I told Naoto my sense is companies are hesitant to implement BPR because they must embed metals in the wafer prior to device formation. Intel has announced their BSPD with TSV’s they call PowerVia, they do not use BPR at least for their 20A and 18A process. TSMC is less clear to me, but I think they are avoiding BPR also. Naoto said he thought it wouldn’t be used in first generation BSPD but should be considered for further scaling.

This paper didn’t cover this, but BSPD also offers the possibility to add more functionality to the back of the wafer such as ESD devices, MIM capacitors, etc.

In conclusion, Imec has shown that BPR and BSPD can address the power delivery IR drop problem without degrading devices. This is important work for continued logic scaling.

Also read:

ASML EUV Update at SPIE

The Lost Opportunity for 450mm

Intel and the EUV Shortage

June 27, 2022July 22, 2022

Time is of the Essence for High-Frequency Traders

Time is of the Essence for High-Frequency Traders
by Dave Bursky on 06-27-2022 at 10:00 am
Categories: Achronix, eFPGA, IP, Silicon Creations
2 Comments

Figure Simplified block diagram of Multiprotocol PMA from Silicon Creations

In the world of financial trading, nanoseconds count. The faster a trade can be accomplished, the more money a trader can make. Getting a trade in before a competitor also results in improved profits. What does this have to do with the partnership deal recently inked between Silicon Creations and Achronix? Plenty. The two companies are parleying their expertise in analog and mixed-signal technology (Silicon Creations) and high-speed programmable logic (Achronix Semiconductor) to deliver Silicon IP supporting higher performance ASIC solutions with more design flexibility by creating interfaces with lower delays. The joint efforts focus on optimizing the data path from the Silicon Creations SerDes interface to and from the Achronix embedded field-programmable gate arrays (eFPGAs), which are both part of a larger system-on-chip (SoC) solution.

The combined efforts by the two companies are filling a need by suppliers of high-frequency trading systems (HFTS). Such HFTS are typically proprietary designs that demand the highest-performance, lowest-latency ASIC solutions. To push more performance and design flexibility into the HFTS, Silicon Creations and Achronix provide silicon IPs that enable their customers to optimize the data path from the SerDes interface to and from the eFPGA IP. That will allow trading system designers to add flexibility and achieve topnotch performance in algorithmic trading applications.

HFTS are typically proprietary designs that demand the highest-performing, lowest-latency silicon available. While ASICs are often a key component of such designs, eFPGA IP weaved into ASICs can deliver the performance and programmability that leading-edge systems require. Silicon Creations, a leading supplier of high-performance analog and mixed-signal intellectual property (IP), saw the synergy with programmable silicon, and that led to the partnership with Achronix Semiconductor Corporation, a leader in high-performance FPGAs and embedded FPGA (eFPGA) IP.

SerDes PMAs from Silicon Creations are optimized for ultra-low-latency optical connections, which are ideal for HFT Ethernet interfaces with in-PMA latency below 1.3 ns for 10G Ethernet. The SerDes PMAs also fit well in multiprotocol applications that support Ethernet 10G-KR, PCIe4, and many other protocols (see the figure). Multiprotocol SerDes PMA designs from Silicon Creations support over 30 protocols including CEI 6G & 11G SR, MR, LR, DisplayPort, Ethernet 10GBASE-X/S/K/R, PCIe Gen1/2/3/4, V-by-One HS/US, CPRI, PON, OTN/OTU, 3GSDI, JESD204A/B/C, SATA1-3, XAUI, SGMII. They have programmable (de)serialization widths of 8, 10, 16, 20, 32, or 40 bits. The transmit ring PLL includes fractional multiplication, spread spectrum and jitter cleaner function for Sync-E and OTU. Additionally, the PMAs offer out-of-band, electrical-idle signaling capability for SAS, SATA, and PCIe.

“We’re ready to provide tailored IP for HFT ASICs fabricated using 12/16 nm FinFET technology,” said Randy Caplan, co-founder and executive VP at Silicon Creations. “Engineers who need to stay at the front of today’s latency race must make a critical architectural decision: FPGA or ASIC? We think our partnership with Achronix to embed programmable logic in an ASIC offers the perfect blend of both technologies to drive improvements in programmable algorithmic trading.

Echoing a similar opinion, Steve Mensor, VP of Marketing and Strategic Planning at Achronix sees the partnership with Silicon Creations able to deliver a UDP-to-TCP loopback latency of under 10 ns, which is not possible with standalone FPGAs. “Together, we enable customers to create significant differentiation in their HFT systems by leveraging Achronix Speedcore eFPGA IP and Silicon Creations SerDes IP integrated into a customer’s ASIC.”

Read the full press release here: https://www.achronix.com/company/newsroom/news

For more information, visit www.siliconcr.com, and www.achronix.com

Also Read:

Creating Analog PLL IP for TSMC 5nm and 3nm

Essential Analog IP for 7nm and 5nm at TSMC OIP

Keeping Pace With 5nm Heartbeat

June 27, 2022July 23, 2022

TSMC 2022 Technology Symposium Review – Advanced Packaging Development

TSMC 2022 Technology Symposium Review – Advanced Packaging Development
by Tom Dillinger on 06-27-2022 at 6:00 am
Categories: Events, Foundries, TSMC
2 Comments

TSMC recently held their annual Technology Symposium in Santa Clara, CA. The presentations provide a comprehensive overview of their technology status and upcoming roadmap, covering all facets of the process technology and advanced packaging development. This article will summarize the highlights of the advanced packaging technology presentations – a previous article covered the process technology area.

General

TSMC has merged their 2.5D and 3D packaging offerings into a single brand – “3D Fabric”. The expectations are that there will be future customers that pursue both options to provide dense, heterogeneous integration of system-level functionality – e.g., both “front-end” 3D vertical assembly, combined with “back-end” 2.5D integration.

Technically, the 2.5D integration of SoCs with “3D” high-bandwidth memory HBM stacks is already a combined offering. As illustrated above, TSMC is envisioning a much richer mix of topologies in the future, combining 3D SoIC with 2.5D CoWoS/InFO as part of very complex heterogeneous system designs.

As with the process technology presentations at the Symposium, the packaging technology updates were pretty straightforward – an indication of successful, ongoing roadmap execution. There were a couple of specific areas representing new directions that will be highlighted below.

Of particular note is the TSMC investment in an Advanced System Integration fab, which will support the 3D Fabric offerings, providing full assembly and test manufacturing capabilities.

2.5D packaging

There are two classes of 2.5D packaging technologies – “chip-on-wafer-on-substrate” (CoWoS) and “integrated fanout” (InFO).

(Note that in the figure above, some of the InFO offerings are denoted by TSMC as “2D”.)

The key initiative for both these technologies is to continue to expand the maximum package size, to enable a larger number of die (and HBM stacks) to be integrated. As an example, the fabrication of the interconnect layers on a silicon interposer (CoWoS-S) requires “stitching” multiple lithographic exposures – the goal is to increase the interposer size in term of multiples of the maximum reticle dimensions.

CoWoS

CoWoS has expanded to offer three different interposer technologies (the “wafer” in CoWoS):

CoWoS-S
- uses a silicon interposer, based on existing silicon wafer lithographic and redistribution layer processing
- in volume production since 2012, >100 products for 20+ customers to date
- the interposer integrates embedded “trench” capacitors
- 3X max reticle size in development – to support a design configuration with 2 large SoC’s and 8 HBM3 memory stacks, with eDTC1100 (1100nF/mm**2)
CoWoS-R
- uses an organic interposer for reduced cost
- up to 6 redistribution layers of interconnect, 2um/2um L/S
- 2.1X reticle size supporting one SoC with 2 HBM2 stacks in a 55mmX55mm package; 4X reticle size in development, with 2 SoCs and 2HBM2 in an 85mmX85mm package
CoWoS-L
- uses a small silicon “bridge” inserted into an organic interposer, for high density interconnects between adjacent die edges (0.4um/0.4um L/S pitch)
- 2X reticle size supports 2 SoCs with 6 HBM2 stacks 2023); 4X reticle size in development to support 12 HBM3 stacks (2024)

TSMC highlighted that they are working with the HBM standards group on the physical configuration of HBM3 interconnect requirements for CoWoS implementations. (The HBM3 standard appears to have settled on the following for the stack definition: capacity of 4GB w/four 8Gb die to 64GB w/sixteen 32Gb die; 1024-bit signal interface; up to 819GBps bandwidth.) These upcoming CoWoS configurations with multiple HBM3 stacks would provide tremendous memory capacity and bandwidth.

Also, in anticipation of much greater power dissipation in upcoming CoWoS designs, TSMC is working on appropriate cooling solutions, both improved thermal-interface-materials (TIM) between die and package, as well as transitioning from air to immersion cooling.

InFO

After accurate (face-down) placement orientation on a temporary carrier, die are encapsulated in a epoxy “wafer”. Redistribution interconnect layers are added to the reconstituted wafer surface. The package bumps are then connected directly to the redistribution layers.

There are InFO_PoP, InFO_oS, and InFO_B topologies.

As shown below, InFO_PoP denotes a package-on-package configuration, and is focused on integration of a DRAM package with a base logic die. The bumps on the DRAM top die utilize through-InFO vias (TIV) to reach the redistribution layers.

InFO_PoP primarily for the mobile platform
over 1.2B units shipped since 2016

An issue with the InFO_PoP implementation is that currently the DRAM package is a custom design, and only able to be fabricated at TSMC. There is an alternative InFO_B topology in development, where an existing (LPDDR) DRAM package is added on top, with assembly to be provided by an external contract manufacturer.

InFO_oS (on-substrate) enables multiple die to be encapsulated, with the redistribution layers and their microbumps connected to a substrate with TSVs.

in production for over 5 years, focus is on HPC customers
5 RDL layers on the substrate, with 2um/2um L/S
the substrate enables a large package footprint, currently at 110mm X 110mm with plans for greater sizes
130um C4 bump pitch

As depicted above, InFO_M is an alternative to InFO_oS, with multiple encapsulated die and redistribution layers, without the additional substrate + TSVs (< 500mm**2 package, production in 2H2022).

3D packaging

InFO-3D

There is a 3D stacked package technology that utilizes micro-bumped die integrated vertically with redistribution layers and TIVs, focused on the mobile platform.

3D SoIC

The more advanced vertical-die stacked 3D topology packaging family is denoted as “system-on-integrated chips” (SoIC). It utilizes direct Cu bonding between the die, at an aggressive pitch.

There are two SoIC offerings – “wafer-on-wafer” (WOW) and “chip-on-wafer” (COW). The WOW topology integrates a complex SoC die on a wafer providing deep trench capacitor (DTC) structures for optimal decoupling. The more general COW topology stacks multiple SoC die.

The process technologies qualified for SoIC assembly are shown in the table below.

Design Enablement for 3DFabric, including 3Dblox

As illustrated in the upper right corner of the 3D Fabric image above, TSMC is envisioning complex system design-in-package implementations, combining both 3D SoIC and 2.5D technologies.

The resulting complexity in the design flow is great, as highlighted above, with advanced thermal, timing, and SI/PI analysis flows required (which can also deal with the model data volume).

To enable the development of these system-level designs, TSMC has collaborated with EDA vendors on three major design flow initiatives:

improved thermal analysis, using a coarse-grained plus fine-grained approach)

hierarchical static timing analysis
- individual die are represented by an abstracted model, to reduce the total (multi-corner) data analysis complexity

front-end design partitioning

To help accelerate the front-end design partitioning of a complex system, TSMC has pursued an initiative denoted as “3Dblox”.

The goal is to break down the overall physical package system into modular components, which are then integrated. The module categories are:

bumps/bonds
vias
caps
interposers
die

These modules would be incorporated into any of the SoIC, CoWoS, or InFO package technologies.

Of specific note is that TSMC is driving an effort to enable 3D Fabric designs to use various EDA tools – that is, to complete physical design with one EDA vendor tool, and (potentially) use different EDA vendor products for support for timing analysis, signal integrity/power integrity analysis, thermal analysis.

3Dblox appears to take the concept of “reference flows” for SoCs to a new level, with TSMC driving interoperability between EDA vendor data models and formats. The overall 3Dblox flow capability will be available in 3Q2022. (A preliminary step – i.e., automated routing of redistribution signals on InFO – will be the first feature released.)

Clearly, TSMC is investing extensively in advanced packaging technology development and (especially) new fabrication facilities, due to the anticipated growth in both 2.5D and 3D configurations. The transition from HBM2/2e to HBM3 memory stacks will result in considerable performance benefits to system designs utilizing CoWoS 2.5 technology. Mobile platform customers will expand the diversity of InFO multi-die designs. The adoption of complex 3DFabric designs combining both 3D and 2.5D technologies will no doubt increase, as well, leveraging TSMC’s efforts to “modularize” the design elements to accelerate system partitioning, as well as their efforts to enable a broad set of EDA tools/flows to be applied.

-chipguy

Also Read:

TSMC 2022 Technology Symposium Review – Process Technology Development

Three Key Takeaways from the 2022 TSMC Technical Symposium!

Inverse Lithography Technology – A Status Update from TSMC

June 26, 2022July 18, 2022

Multiphysics, Multivariate Analysis: An Imperative for Today’s 3D-IC Designs

Multiphysics, Multivariate Analysis: An Imperative for Today’s 3D-IC Designs
by Daniel Nenni on 06-26-2022 at 6:00 am
Categories: Ansys, Inc., EDA, Events

Semiconductor manufacturers are under constantly increasing and intense pressure to accelerate innovative new chip designs to market faster than ever in smaller package sizes while assuring signal integrity and reducing power consumption. Three-dimensional integrated circuits (3D-ICs) promise to answer all these demands but, at the same time, they introduce a new level of design complexity that is challenging traditional tools and processes.

Manufactured by stacking dies and interconnecting them so they perform as a single device, 3D- ICs create new risks, including thermal build-up caused by greater density. Because they’re significantly larger than a typical system-on-a-chip (SoC), with longer interconnects, they need to be rigorously tested for faulty integration points as well as system-level failures.

However, most semiconductor development teams simply aren’t equipped to manage the difficult job of 3D-IC analysis and design validation. They’re burdened by a historical approach to SoC simulation that relies on a serial, step-by-step process, in which single-physics simulation tools are applied one by one. When engineers apply these disparate tools, and this serial process, to complex 3D-IC designs, they’re missing system-level interactions, connection points, consolidated thermal effects and other considerations for something to go seriously wrong.

As 3D-ICs become more common for advanced semiconductor applications, engineering teams need a new analytic approach that’s equally innovative. They need a single, open and proven platform to conduct concurrent, multivariate simulation and analysis across the entire product design. They need to consider multiple physics, quickly and simultaneously, at both the component and system levels.

An Open Platform for Optimizing Every Performance Aspect

Ansys’ industry-leading solutions for 3D-IC simulation and analysis provide engineering teams with best-in-class capabilities for optimizing every aspect of performance, including power integrity, reliability, electromagnetics (EM), thermal, computational fluid dynamics (CFD) and mechanical stress.

This is a resistance heatmap of a chip-package system with pin resolution The IR drop map and electromigration map can also be generated for power integrity and reliability sign-off of 3DIC system.

The comprehensive Ansys toolkit positions semiconductor engineering teams to assess stand-alone performance aspects like thermal conductivity, while simultaneously looking at every other critical metric. The entire 3D-IC design can be subjected to realistic operating conditions as an integrated system, beginning at the earliest design stage.

This is a temperature contour map of a chip-package system with die, interposer and package modeled by RHSC ET. The nodal temperature at each layer of the system can be displayed to identify the hotspot location for applying thermal integrity solutions.

Ansys provides a unified 3D-IC simulation platform incorporating our best-in-class solutions. For example, Ansys RedHawk-SC Electrothermal can be leveraged to verify the thermal hotspots, melting risk, local failure modes of each welding site, based on the electrical current load at that specific point. Ansys CFD capabilities can optimize the performance of fans and heat sinks as they generate airflows to cool the assembly. Ansys solutions can also analyze advanced performance aspects, such as low-frequency power oscillations, and predict their impact on the larger design.

Shown here is an analysis of mechanical stress/warpage, as well as thermal gradients, in a 3D-IC multi-die package. This is an example of a complex real-world problem that can only be solved quickly via a multiphysics, multivariate approach.

Not only does Ansys address all of these individual engineering challenges through best-in-class solvers, but it equips semiconductor development teams to conduct these studies simultaneously. Only Ansys supports this type of multiphysics, multivariate, concurrent approach that reveals critical design trade-offs at the system level, rapidly and at an early stage.

In Your Rush to Market, Don’t Shortchange Your Analysis

Faced with worldwide chip shortages, increasing performance demands, a lack of engineering talent, and an urgent need for low-cost innovation, semiconductor manufacturers may be tempted to focus on their existing set of serial processes and isolated, single-physics simulation tools. But these outdated methods are insufficient to capture the complexity of 3D-IC designs and their equally complex failure risks.

Different engineers, using different simulation and analysis tools, may actually work at cross-purposes. For instance, one team’s efforts to resolve a signal-integrity issue might inadvertently create a timing failure or thermal risk that needs to be resolved by another team — which then hands it back to the signal-integrity team. The result? The dreaded ping pong effect with costly delays, resource-intensive handoffs, and significant rework.

In contrast, the robust and comprehensive Ansys simulation platform supports synergistic, collaborative, and cross functional analysis. It’s fast and intuitive for the multidisciplinary design team to look at the holistic 3D-IC design and concurrently analyze novel physics, to optimize performance aspects from electrical reliability to mechanical and thermal stability.

Collaboration-Driven Innovation: The Wave of the Future

The world’s semiconductor leaders are realizing that true 3D-IC innovation requires a new level of collaboration and vertical integration. Only by removing traditional functional boundaries — and eliminating a single-physics, serial approach — can development teams accelerate the design cycle, drive down costs, and produce game-changing new performance innovations.

Ansys’ open, extensible, and powerful simulation platform for multiphysics 3D-IC simulation is purpose-built to realize this vision. By leveraging a unified platform with proven, best-in-class solutions for multiphysics and multiscale analysis, semi development teams can launch new designs quickly and collaboratively, without sacrificing analytic rigor or product confidence. Costly handoffs and rework are reduced as the cross functional team shares the same understanding of performance trade-offs and ultimate goals.

While it can be difficult to break down cultural and organizational barriers to collaboration and vertical integration, the rewards are well worth it, including faster time-to-market and higher levels of innovation. Replacing sequential analysis and a disparate toolkit with the Ansys platform to support concurrent, multiphysics, system-level design simulations is a critical first step.

Visit Ansys at DAC 2022

If you’re hoping to fully capitalize on the incredible promise of 3D-IC designs, you owe it to yourself to learn more about the Ansys platform for multivariate, multiphysics simulation. Visit Ansys at Booth #1539 at the Design Automation Conference (DAC), in San Francisco July 11-14. Request a meeting or product demo now to start supporting a new level of 3D-IC design optimization.

Also read:

A Different Perspective: Ansys’ View on the Central Issues Driving EDA Today

Unlock first-time-right complex photonic integrated circuits

Take a Leap of Certainty at DAC 2022

June 25, 2022June 28, 2022

The Evolution of Taiwan’s Silicon Shield

The Evolution of Taiwan’s Silicon Shield
by Craig Addison on 06-25-2022 at 6:00 am
Categories: China
1 Comment

The original Silicon Shield theory, as described in my 2001 book, stated that Taiwan’s role as producer of 90 per cent of the world’s IT products (at that time) protected it from an attack by China because the United States, acting in its own self interest, would come to the island’s defense. A similar scenario – involving oil, not electronics – occurred in 1990 when the US intervened after Iraq invaded Kuwait.

Fast forward a decade after the book, and much of Taiwan’s electronics production, including laptops and mobile phones, had moved to China – although it was still controlled by Taiwanese-owned companies like Compal, Foxconn and Quanta. (The transfer of Taiwanese chip technology to China was restricted, and still is).

The 2009 Silicon Shield documentary reflected this shift by arguing that China would refrain from attacking Taiwan because of the harm it would inflict upon itself. In other words, a Cold War-style mutually assured destruction (MAD) scenario would keep the peace.

So what is the Silicon Shield today?

Both of the above still apply in their own way, but some pundits now believe the Silicon Shield may even increase the risk of Taiwan being forcibly taken by China. The “Broken Nest” theory states that Taiwan should adopt a scorched earth policy and destroy TSMC et al in the event of an attack, thus reducing the island’s value to the invaders.

While the Broken Nest has its fair share of critics, a similar scenario was foreshadowed by one of the people interviewed for the 2009 documentary. Chih-Yuan Lu, former head of Taiwan’s Submicron Project and since then president of Macronix International, said Taiwan’s semiconductor industry could be compared to jade, the precious mineral valued by the Chinese.

“If you have valuable jade in your pocket and you cannot defend yourself, there are many robbers who will target you,” Lu said at the time. In the case of two parties fighting over ownership, “at the last moment they even want to break the jade” to prevent the other from having it, he explained.

Since the outbreak of the pandemic, semiconductors have been elevated from relative obscurity to an industry of keen interest to mainstream media and the general public. The same goes for Taiwan and its role in the hi-tech supply chain. These developments motivated me to revive the original Silicon Shield documentary for a new audience.

The result is “Silicon Shield 2025” – the year being a reference to the date Taiwan’s defense minister believes China will have the ability to invade. The new version, available for streaming on Vimeo On Demand, uses the same voice-over narration and video interviews from the 2009 production, but the content has been digitally remastered and updated with HD b-roll footage as well as new material to reflect recent events. Indeed, it is remarkable how much of the original documentary narrative from 13 years ago is relevant today, perhaps more so.

SemiWiki members choosing the “rent” option on Vimeo On Demand can watch “Silicon Shield 2025” free of charge by using the promo code CHIPS, which is valid until July 25.

In addition, be sure to check out The Chip Warriors podcast – the most recent episode being on Taiwan’s Chip Warriors, featuring the above mentioned C.Y. Lu, as well as legends like TSMC founder Morris Chang.

For those interested in how Taiwan got into this situation in the first place – caught between two superpowers – check out the Nixon’s China Choice podcast. Nothing about semiconductors here, but it is a fascinating look into the minds of Nixon, Kissinger and Halderman as they sought rapprochement with Communist China while trying not to sacrifice Taiwan in the process. Nixon failed in the latter, but that set back – along with the loss of US diplomatic recognition under Carter in 1979 – provided the impetus for Taiwan’s leaders to take the enormous risk of betting their national survival on semiconductors.

Also read:

US Supply Chain Data Request Elicits a Range of Responses, from Tight-Lipped to Uptight

Losing Lithography: How the US Invented, then lost, a Critical Chipmaking Process

Why Tech Tales are Wafer Thin in Hollywood

Podcast EP90: A Tour of Cadence’s Cloud Solutions with Mahesh Turaga

Podcast EP90: A Tour of Cadence’s Cloud Solutions with Mahesh Turaga
by Daniel Nenni on 06-24-2022 at 10:00 am

Dan is joined by Mahesh Turaga, VP of Cloud Business Development at Cadence Design Systems. Mahesh brings extensive customer-facing experience to Cadence in business development, strategy, pre-sales, and consulting. He provides an overview of the cloud solutions provided by Cadence. The various business models, technical details and target customer profiles are all discussed.

Mahsh holds an MBA from Northwestern University – Kellogg School of Management and Ph.D in aeronautics, structural mechanics, composites and fluid dynamics from Purdue University.

The views, thoughts, and opinions expressed in these podcasts belong solely to the speaker, and not to the speaker’s employer, organization, committee or any other group or individual.

June 24, 2022June 24, 2022

ASML EUV Update at SPIE

ASML EUV Update at SPIE
by Scotten Jones on 06-24-2022 at 6:00 am
Categories: Events, Lithography, Semiconductor Services, TechInsights
5 Comments

At the 2022 SPIE Advanced Lithography Conference, ASML presented an update on EUV. I recently had a chance to go over the presentations with Mike Lercel of ASML. The following is a summary of our discussions.

0.33 NA

The 0.33 NA EUV systems are the production workhorse systems for leading edge lithography today. 0.33 NA systems are in high volume production for both logic and DRAM. Figure 1 illustrates the number of EUV layers for logic and DRAM (bars) and wafers exposed per year (area). Authors note, the 2021 values for logic are typical of foundry 5nm processes at 10+ EUV layers and 2023 logic would be in-line with foundry 3nm processes at ~20 layers, DRAM usages is currently ~5 layers. I asked mike about future DRAM exposures, he pointed out there are ~8 critical layers on a DRAM and eventually some of those layers could need multi-patterning bringing EUV exposure up to 10 per wafers.

Figure 1. EUV Adoption.

Through Q1 of 2022 ASML has shipped 136 EUV systems and ~70 million wafers have been exposed, see figure 2.

Figure 2. Number of EUV Wafers Exposed.

System availability continues to improve, it is at a little less than 90% today. The new NXE:3600D is better than the NXE:3400C and provide ~93% availability. EUV system availability is getting close to DUV system levels (~95%).

Figure 3. Availability.

NXE:3600D systems can produce 160 wafers per hour (wph) at 30mJ/cm², 18% better than the NXE:3400C. The NXE:3800E systems in development will provide >195 wph at 30mJ/cm² initially, and 220 wph with throughput upgrades. The NXE:3600E will have incremental optical improvements in aberration, overlay and throughput.

Figure 4. Throughput Improvements.

Matched machine overlay for the NXE:3400C was 1.5nm and is 1.1nm for the NXE:3600D. The NXE:3600D uses the same new 12 wavelength alignment system as the newest DUV systems with just a few material differences due to vacuum use.

The ASML roadmap includes the NXE:4000F with >220wph around 2025, see figure 5.

Figure 5. System Roadmap.

Pellicles now achieve greater than 90% transmission and manufacturing has been transferred to Mitsui. I run into people from time to time who think Pellicles are a future EUV item, but Pellicles have been in production use on select layers for over a year.

Figure 6. Pellicle Performance.

Finally for the 0.33 NA system ASML is working on reducing the energy required for each exposure by increasing throughput and decreasing total energy.

Figure 7. Energy Per Exposure.

We discussed the ultimate resolution limits for 0.33 NA systems, in theory 0.33 NA can produce 26nm in a single exposure, currently Imec is working on 28nm single exposure, but it isn’t in production yet.

0.55 NA (High NA)

As described in the previous section 0.33 NA EUV is in high volume production. Leading edge foundry processes have now reached the 3nm “node” and double patterning with 0.33 NA EUV is becoming necessary. By raising the NA from 0.33 to 0.55 double patterned layers can be replaced with single exposures.

Figure 8 illustrates how DUV layers counts grew driven by process complexity and multipatterning until 0.33 NA EUV took over eliminating a lot of multipatterning. As 0.33 NA EUV multipatterning use grows 0.55 NA EUV can eliminate some multipatterning reducing layer counts again.

Figure 8. Mask Count Trends.

High-NA provides a better image log slope, stochastic defects are 3D and high-NA helps with defect reduction. ASML is working on attenuated phase shift masks for EUV to improve contrast and depth of field. They will be implemented for 0.33 NA first and then 0.55 NA later.

ASML’s roadmap has the first High NA system (EXE:5000) being installed in a lab at the ASML factory run jointly with Imec in 2023 for initial evaluation. EXE:5000 systems should be delivered to customers in 2024 and the production EXE:5200 system should be delivered to customers for production use around 2025, see figure 9.

Figure 9. High-NA System Roadmap.

The optics for High-NA are significantly larger than for 0.33 NA and require a unique design approach. 0.55 NA systems will have an anamorphic lens system with a 4x reduction ratio in one direction (the same as 0.33 NA) and an 8x reduction ratio in the orthogonal direction. Due to the size of the reticle and the 8x reduction, the printable field size is cut in half to 16.5nm in the scan direction, see figure 10.

Figure 10. Anamorphic Lens System.

Simulations show no direction differences between a half-field and full field exposure. Half-field exposures can be aligned to full field exposures so that existing DUV and 0.33 NA EUV systems can be used in a mix and match strategy with 0.55 NA systems. If necessary for large die, 0.55 NA half-field exposures can stitched together, possibly with a small stitch boundary for global connections.

Using research tools at The Center for X-Ray Optics at Berkely and Paul Scherrer Institut, ASML has been able to demonstrate High-NA EUV resolution down to 8, see figure 11.

Figure 11. 8nm Line/Spaces.

The 0.55 NA system design is broken up into 4 independently testable sub systems (see figure 12) and assembly of the first exposure tool to go into the ASML/Imec lab in 2023 has begun (see figure 13).

Figure 12. High-NA Sub Systems.

Figure 13. 0.55 NA System Integration.

ASML continues to work on increasing source power and has recently demonstrated >500 watts in research. Historically it has taken ~2 years for research developments to reach production. Figure 14 illustrates source power over time.

Figure 14. Source Power Trends.

0.7 NA

In a recent article Tom Dillinger discussed an interview with Mark Phillips of Intel and Mark mentioned 0.7 NA as a successor to 0.55 NA. I was surprised by this, I thought ASML had ruled out developing anything after 0.55 NA due to the high investments ASML has had to make on EUV. Mike said ASML hasn’t ruled out a 0.7 or greater NA system, they are looking at it. He said they have ruled out shorter wavelengths than the current 13.5nm (authors note, at one time there was some discussion of a shorter wavelength system 6.xnm). They do want any new system to be air shippable which limits how much bigger the system can be than the 0.55 NA systems.

Conclusion

0.33 NA EUV systems are now production work horse systems with continuously improving availability and throughput. 0.55 NA systems are expected to enter production in 2025 with higher resolution enabling process simplification. Beyond 0.55 NA ASML is looking at even higher NA systems. EUV is well positioned to continue to drive lithography resolution for the next decade.

Also Read:

Obscuration-Induced Pitch Incompatibilities in High-NA EUV Lithography

The Electron Spread Function in EUV Lithography

Double Diffraction in EUV Masks: Seeing Through The Illusion of Symmetry

June 23, 2022July 18, 2025

Using STA with Aging Analysis for Robust IC Designs

Using STA with Aging Analysis for Robust IC Designs
by Daniel Payne on 06-23-2022 at 10:00 am
Categories: EDA, Synopsys

Our laptops and desktop computers have billions of transistors in their application processor chips, yet I often don’t consider the reliability effects of aging that the transistors experience in the chips. At the recent Synopsys User Group (aka SNUG), there was a technical presentation on this topic from Srinivas Bodapati, an engineer at Intel.

Device Aging

As transistors are switched on and off the drain currents can over time slowly decrease, this in turn changes path delays that make the chip speed slow down, and even fail to meet specifications. Device aging is now a first order problem when designing leading edge processor chips and GPUs. To manage power dissipation, many SoC design employ Dynamic Voltage Frequency Scaling (DVFS) techniques, yet the stress from running with a high VDD begins to impact circuit operation when in low VDD mode.

Gate Level Aging: Specification Failure

Device aging is dependent on workload, Voltage, Temperature and Frequency, and the two effects that cause transistor performance to shift over age are:

Bias Temperature Instability (BTI)
Hot Carriers Injection (HCI)

The device aging mechanisms for HCI and BTI are summarized in this table as a function of each factor:

Device Aging Mechanisms

At 14nm the main aging contribution was from BTI, but at 10nm it was from HCI effects. At the same time the End Of Life (EOL) drive currents increased by 1.65X, going from 14nm to 10nm.

Use Condition Problems

With DVFS circuits during the high VDD frequency mode there is stress to the transistors, which then impacts the circuit operation in low VDD mode. The delay of gates can become slower through aging, even to the point of getting out of specification, causing a timing failure.

During Static Timing Analysis (STA), the challenge is to model the workload dependency of aging, and consider that input slope plus output load impact aging. Consider an SoC example where there is a high performance core (PCore), an efficiency core (Ecore), fabric, and system IP blocks. These four types of IP have very different supply voltage ranges, and also temperatures. Trying to use the same static guard band for each IP block would be overly pessimistic for some scenarios, so using an existing aged library cannot really capture all of the various stress scenarios.

Aging for different circuits

STA Aging Model Complexity

In the example below there’s a launch path, and a capture path, but each path has a unique switching activity which then changes their aging degradation to be different amounts. For each path the effects of both BTI and HCI also need to be taken into account, as aging degradation depends on each

Launch path, Capture path

Old and New Approaches

The older approach was to use STA with Aged Libraries and then have path simulation for derates. The drawbacks of the older approach are that DVFS usage is not accounted for, the BTI vs HCI effects are not separated, and it required handcrafted paths. The other challenge is the productivity bottleneck, as the STA and simulation are typically handled by different expert teams, modeling aging involves multiple cycles of identifying paths, running simulations, and analyzing results to come up with derates, which can then be used for modeling aging, however, these derates can often be pessimistic.

The new approach is an aging-aware STA methodology, which has automated workload dependency, simulates actual paths, takes into account BTI and HCI tradeoffs, works within a single simulation structure, and supports scalability of aging mission profiles without trading off for accuracy and enabling them to find the actual worst-case.

Aging-Aware STA Flow

The Synopsys tool for this aging-aware flow is called PrimeShield, and there are two components:

Aging STA
Aging-aware SPICE simulation

Intel used the aging-aware SPICE simulation component, where the circuit designer specifies a set of paths for simulation in Simlink. This enabled the specify and create stress conditions and simulates with HSPICE creating a degradation file that is used to generate playback with fresh conditions to measure the aging impact. Aging-aware Simlink enables easier stress conditions creation and automates the impact of aging at various other stress condition, based on initial inputs.

Aging-Aware STA Flow

On the other hand aging-aware STA flow eases the methodology further by using aged libraries with mission profile information to calculate the impact of aging on the actual paths using the Synopsys PrimeTime’s PBA methodology. It also enables designers to configures the stress waveform by setting the cycle count, an activity factor, a signal probability, age time, and stress voltage ratio.

Results

Using the aging-aware flow they wanted to see the workload dependency of slack degradation, and the reference case is called slack2, where both the launch clock and capture clock have an activity factor of 0.2, shown in the table below:

Workload dependency of slack degradation

Slack2 is the reference scenario, with equal activity factors for launch and capture clocks. The other three scenarios have a variety of activity factors for launch and capture clocks, and the yellow table shows how the slack degradation increases for each scenario, with scenario slack82 having the worst case slack degradation. These results depend on the effects of HCI and BTI.

Running and plotting many paths to compare normalized degraded slack versus normalized reference slack is shown in the next plot. The legend shows four types of results:

Launch clock at 0.2, capture clock at 0.2 (l2c2)
Launch clock at 0.8, capture clock at 0.8 (l8c8)
Launch clock at 0.8, capture clock at 0.3 (l8c2)
Launch clock at 0.2, capture clock at 0.8 (l2c8)

Normalized results

This helps designers identify worst case corners for each IP block in a path aging flow.

Conclusions

Running STA with aging effects is quite complex, especially when using DVFS design techniques, and aging depends on workloads to get accurate answers. Intel designers working with Synopsys tools and AEs have developed an aging-aware STA flow that uses PrimeShield, Simlink and HSPICE together for path simulations. Reliability issues are now first order, so having automation for aging analysis in a STA flow is a must have feature.

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June 23, 2022July 21, 2022

Scaling Safety Analysis. Reusability for FMEDA

Scaling Safety Analysis. Reusability for FMEDA
by Bernard Murphy on 06-23-2022 at 6:00 am
Categories: Arteris, Automotive, IP

It is common when a new type of analysis is introduced in almost any domain that it works well enough for a while. Until it begins to struggle with growing problem size, prompting refinements to the methodology to allow continued scaling. We see this routinely in analytics for SoC design, so it should not be a big surprise that safety analysis, in the form of failure modes, effects and diagnostic analysis (FMEDA), is starting to look a little creaky. Which is no small concern. FMEDAs are the contracts passed up from IP developers to SoC integrators, providing assurance that safety weaknesses have been fully analyzed and mitigated. This is not a requirement we want to short-change because the analysis problem becomes too messy.

Configurability – the root cause

Most IPs are configurable, even in-house IPs, because to be useful as reusable components, they must be able to adapt to a variety of different SoC applications. There is no IP more configurable than a network-on-chip (NoC). The whole structure of the NoC will change depending on how many components it must connect. And what quality of service goals it must meet, how it should adapt to minimize congestion and so on.

All this configurability is essential to meet SoC design goals, but it comes with a downside. FMEDA is a flat characterization based on fault simulation, run on the component as configured. There is generally no way to analyze a parametrized IP before configuration. SoC integrators must run the analysis per IP, even on commercial components. IP suppliers will provide as much help as they can in the form of templates and advice, but the burden of final and lengthy FMEDA remains with the integrator. The SoC team must repeat this analysis if the configuration changes, all adding up to a lot of extra work.

The core problem is a lack of reusability in FMEDA. If this could be restructured to support reuse, then IP suppliers could provide a means to generate not only a configured IP but also an FMEDA for that IP. Integrators could avoid most of the effort in repeating flat analyses in this case

Redesigning FMEDA for reuse

FMEDAs, as they stand, are not parametrizable, but they could be generated through a combination of low-level safety models and a compiler which could read those models together with the configured IP RTL to determine how root causes will propagate to effects. Arteris IP has written a thought leadership paper on putting these ideas into practice. Cutting out much of the unnecessary rework in rebuilding FMEDAs. Conceptually this makes sense to me. Failure modes don’t change on configuration. There may be more or less of a certain type in some cases, added or subtracted in predictable ways. How these can propagate to effects also won’t change much except as perhaps you could analyze through interpolation between a few carefully selected configurations. Allowing a tool to compute the influence on the likelihood of failure. The concept seems very reasonable.

You could extend automated generation not only to generating IP FMEDAs but also to generating the SoC FMEDA. Apparently, leading semis in the automotive space already do something like this internally. The SoC generator must aggregate FMEDAs from the IPs. Applying in-context requirements and assumptions of use to abstract failure modes to those relevant to system behavior. Adding this functionality with IP FMEDA generation could take a lot of the pain out of safety analysis for SoC integrators.

You can learn more about this topic in this Arteris IP presentation HERE.

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