SemiWiki – Page 257 – The Open Forum for Semiconductor Professionals

July 3, 2022July 6, 2022

Supply Chain Verification: Critical Enabler for Next-Generation Medtech Innovations

Supply Chain Verification: Critical Enabler for Next-Generation Medtech Innovations
by Bob Smith on 07-03-2022 at 6:00 am
Categories: Events

Chip design verification has long been a key component of any design project developing silicon intended to go into manufacturing. As designs become more complex, so does the manufacturing risk, and the focus on thorough verification becomes ever more critical.

Another dimension of complexity coming into play and considered throughout the entire electronic system. The shift toward chiplet-based design, 3D-IC and other innovative packaging technologies are driving the need for verification beyond the individual chip. System design verification that spans multiple devices, subsystems and even software code is becoming the norm for ensuring that an electronic system can be manufactured and perform as intended.

And yet, not all markets have the same requirements. Consider the differences between a low-cost consumer electronic product and an electronic medical system or device implanted in a human body. For example, the consumer product may have an expected lifetime of flow years and, if it malfunctions, it is annoying, but not life-threatening. Conversely, a medical electronic system may require an operating lifetime of more than 10 years and malfunctions are not tolerable as they may lead to serious health consequences, including death. In the case of both examples, rigorous verification is required. In the case of the medical electronic system, requirements for full system verification are much more stringent.

Yes, system design verification is more important now because of more use cases, applications and extended lifecycles. The requirement for functional verification runs through the entire electronic product design manufacturing supply chain. Without thorough verification, the supply chain can be compromised.

Given these scenarios, the ESD Alliance, a SEMI Technology Community, is drawing attention to the challenges and opportunities available throughout the entire electronic product design and manufacturing supply chain. It is sponsoring a panel discussion at SEMICON West on how supply chain verification is becoming a critical need in medical technology applications. “Supply chain verification” implies that thorough verification is required across the entire system of chips, components, and packaging. Our panel brings together experts in chip design, system design and verification, and advanced packaging technologies who will discuss supply chain verification challenges that must be undertaken in developing electronic medical devices and products where safety and reliability are the most important factors.

We invite you to join us for “Supply Chain Verification –– Critical Enabler for Next-Generation MedTech Innovations” Tuesday, July 12, 2022, 11:35 a.m. – 12: 25 p.m. in the Meet the Experts Stage, Moscone South, Exhibition Level, Room 2.

Our session moderator is Lucio Lanza of Lanza techVentures and our panelists are:

Mike Chin –– Intel

Lu Dai –– Qualcomm

Dave Kelf –– Breker Verification Systems

Jan Vardaman –– TechSearch International

Conference passes to both SEMICON West and the co-located Design Automation Conference can be used to attend this panel discussion.

The ESD Alliance will host a reception Wednesday, July 13, from 6 p.m. until 7:30 p.m. at Moscone Center South, Level 2, North Terrace. SEMICON West or DAC badges are required for entry.

SEMICON West 2022 Hybrid will be held July 12-14 at the Moscone Center in San Francisco. Registration is open. The Design Automation Conference (DAC), the premier gathering focused on the design and design automation of electronic circuits and systems, will be co-located with SEMICON West 2022 Hybrid. Registration is open.

About the ESD Alliance

The ESD Alliance, a SEMI Technology Community, serves as the central voice to communicate and promote the value of the semiconductor design ecosystem as a vital component of the global electronics industry. We have an ongoing series of networking and educational events, programs and initiatives. Additionally, as a SEMI Technology Community, ESD Alliance member companies can join SEMI at no extra cost. To learn more about the ESD Alliance, visit the ESD Alliance website. Or contact me at bsmith@semi.org if you have questions or need more information.

Engage with the ESD Alliance at:

Website: www.esd-alliance.org

ESD Alliance Bridging the Frontier blog

Twitter: @ESDAlliance

Facebook

Also read:

The Lines Are Blurring Between System and Silicon. You’re Not Ready.

Multiphysics, Multivariate Analysis: An Imperative for Today’s 3D-IC Designs

ASML EUV Update at SPIE

July 2, 2022March 26, 2023

Micron kicks off the down cycle – Chops 2023 capex – Holding inventory off street

Micron kicks off the down cycle – Chops 2023 capex – Holding inventory off street
by Robert Maire on 07-02-2022 at 10:00 am
Categories: Semiconductor Advisors, Semiconductor Services
2 Comments

-Micron reports weak outlook for fiscal Q4
-2023 capex to be down versus 2022 capex of $12B & Q3’s $2B
-Company keeping inventory off street to support pricing
-Memory is usually the first shoe to drop in a down cycle

Sharp drop in demand at end of Q3…..

Micron reported a sharp drop in demand at the end of its fiscal Q3, which is similar to what we have been hearing and what we reported in recent newsletters. This is a demand side driven imbalance as demand has fallen sharply in the face of supply growth remaining relatively steady. DRAM was 73% of revenues and prices for both DRAM and NAND declined in the quarter. Obviously the industry is bracing for a bit of a storm ahead in the fall.

Holding back inventory

Micron is holding inventory off the street in order to both shore up near term pricing as well as supplement next years product availability while it slows down production rates. This obviously is a strong implication that its current production ramp rate will slow significantly.

Capex was $12.5B in fiscal 2022 – could easily get cut in half

The capex run rate in the just reported Q3 was $2.5B in the quarter or an annual run rate of $10B. We would not at all be surprised to see next years capex cut down to half or less of 2022’s which could be in the range of $6B or $1.5B a quarter or less. The company indicated that its advanced process technology devices were ahead of schedule so they can easily take their foot off the spending gas and coast for a while.

Memory is usually the first to get whacked in a down cycle

We have been suggesting that memory is more consumer centric than other semiconductor parts and as such is more susceptible to declines in consumer spend which is what Micron management was calling out. So it should come as no real big surprise that Micron reported it first. Memory is obviously the ultimate commodity semiconductor product with little to no differentiation despite protests to the contrary.

Samsung will probably echo Micron

We would expect Samsung to repeat what Micron has said as they are in the exact same markets with the exact same products and can’t escape the weakness in demand and pricing. We would hope that Samsung follows Micron and holds product off market to stabilize pricing or things will get very ugly very fast. We would expect a similar slow down in memory capex spend at Samsung but larger in actual dollars as Samsung is a bigger player. Samsung’s spend for logic/foundry should hold up a little better but will likely slow as well

Intel’s warning in line with memory dive

Intel’s warning a few weeks ago was probably in the same timeframe that Micron saw business weaken, likely in similar end markets. We would certainly imagine that this relates to AMD as well. We would certainly be concerned about pricing in the processor market between Intel and AMD as that is already a bone of contention and the fight could worsen if the pie shrinks.

Bigger impact on Semiconductor Equipment

The second order derivative play is that when the chip companies catch a cold the equipment companies get pneumonia. In this case the poster child for memory makers is Lam, followed not too far behind by Applied. KLA is less vulnerable and ASML is more or less immune. Any litho scanners that Micron doesn’t take will likely be snapped up in foundry/logic (at least until that sector rolls over…)

CHIPS for America gets another nail in the coffin

Its a bit hard to argue that the semiconductor industry needs more capacity when demand is falling off and product is being held off the market. If Micron cuts its capex by half, its hard, if not embarrassing for them to hold out their hand for help from the government especially in light of stock buy backs they are doing. It would be a textbook example of “corporate welfare” and why the government shouldn’t help out. It would be throwing gasoline on the fire of excess supply in light of declining demand. While the case can still be made for “on shoring” of chip capacity the argument of shortages just went out the window.

The Stocks

Obviously Micron will get hit as will the broader SOX index especially among the semiconductor equipment companies who could see that declining capex directly. We don’t think this is in any way a Micron specific issue but at the very least a memory market issue that will likely spread. Earnings season could get very ugly indeed as more shoes could drop in the tech and chip sectors

About Semiconductor Advisors LLC
Semiconductor Advisors is an RIA (a Registered Investment Advisor), specializing in technology companies with particular emphasis on semiconductor and semiconductor equipment companies. We have been covering the space longer and been involved with more transactions than any other financial professional in the space. We provide research, consulting and advisory services on strategic and financial matters to both industry participants as well as investors. We offer expert, intelligent, balanced research and advice. Our opinions are very direct and honest and offer an unbiased view as compared to other sources.

Also read:

Semiconductor Hard or Soft Landing? CHIPS Act?

CHIPS for America DOA?

Has KLA lost its way?
‌

July 2, 2022March 26, 2023

Semiconductor Hard or Soft Landing? CHIPS Act?

Semiconductor Hard or Soft Landing? CHIPS Act?
by Robert Maire on 07-02-2022 at 6:00 am
Categories: Semiconductor Advisors, Semiconductor Services
6 Comments

-Chip cycle will come down. Only question is landing impact
-What does cyclical end do to re-shoring & build out plans?
-Is it less demand, excess supply or both? Does it matter?
-CHIP Act rescue efforts get desperate switching to threats

Any landing you can walk away from is a good one

For those of us who have been in the semiconductor industry long enough to live through multiple cycles, we know an end to a cycle is inevitable, the main question is how bad the down cycle is?

In the bad old days, down cycles were a disaster where most in the industry lost money and reduced staff and tried to ride it out.

More recently, down cycles have been more like benign pauses in an otherwise constant up cycle. Increasing and widening demand for chips has been cushioning short periods of excess supply and reduced demand.

In addition, the industry, primarily on the memory side, has been more rational and incremental in its capex spending and expansion plans which has moderated past over supply cycles.

Why is this cycle different from all other cycles?

1) We are coming off a cycle in which the lack of semiconductors did serious damage to other industries and got people’s attention. Previous chip cycles came and went and no one outside the industry was aware, let alone cared about the semiconductor industry – We got noticed in a negative way.

2) Everyone woke up to the realization of the concentration of production that is Taiwan and TSMC. It’s one of those things that just creeps up on you until its there and then its a big surprise. Customers finally got the memo that there is a giant single point of failure in a high failure risk geopolitical area. No one realized that the entire tech industry and a huge chunk of the global economy was based on an embattled island that most of the world doesn’t even recognize.

3) The supply chain became a major issue. Covid showed how both interconnected and vulnerable the global chip supply chain is. Having chips transit through 10 countries on their way to end users is no longer acceptable. People now care where their chips come from. Everybody now wants their own , independent chip fabs. Not because we need the capacity but because we need independence from the global supply chain. We want to keep things within out borders or at least minimize the exposure of the chain.

4) China got serious on being a player in semiconductors. China realized that it needs to become dominant in semiconductors to beat the US, not only economically but militarily and in intelligence related assets. China became the biggest CAPEX spender and fastest most aggressive semiconductor grower, not driven by economics but by global dominance aspirations which trumps and upsets rational economic drivers.

These four major differences will impact how the industry reacts as well the depth and length of any cycle. All four factors will likely cause the industry to spend much, much more on capex and building out new facilities than it really needs to just satisfy normal demand.

These four factors taken together suggest significantly excess spending in semiconductor capacity due to 1) economic risk 2) single point of failure risk 3) supply chain risk 4) strategic imperatives.

This is compared to more “normal” previous cycles where all the industry was trying to do was balance global supply and global demand.

We have the serious makings of a potential supply glut that the industry has never seen before

Demand is good but inflation and global risks will dampen overall growth

Demand for semiconductors has never been better or more widespread. Chips are in absolutely everything become as pervasive as the air we breath. Demand and new applications seems to grow by the day.

The problem is that macro economic issues, such as inflation and geopolitical issues like Ukraine seem likely to significantly slow the overall economy to the point where even semiconductors and tech in general slows from their torrid pace.

Aside from inflation fears we also have the potential of artificial restrictions specifically on the semiconductor industry like cutting Russia and China off from chip purchases that will artificially curb demand.

Is it weak demand or excess capacity or both that turns the cycle? It doesn’t matter

Like many other industries its not just supply and not just demand that make for health but rather the balance between the two. An imbalance in either direction is no good in the long run. Obviously its even worse when both are going in the wrong direction, increasing excess supply coupled with demand falling. Although we are not quite in the “double whammy” mode quite yet we see vectors pointing in the wrong direction.

Off a cliff without skid marks – No one ever sees it coming

Most all previous semiconductor cycles seem to be going along just fine until they aren’t. The surest sign seem to be inexperienced analysts and company management saying that the industry is no longer cyclical, run for the doors!

Just a few short years ago Samsung put the brakes on and virtually halted all CAPEX spend for a few quarters seemingly out of the blue. Semiconductor makers have become relatively fast at reacting to perceived changes. Intel spoke about years of short supply of chips until recently when it appeared to warn on demand. That was clearly a shock. The industry turns on the proverbial dime.

CHIPS Act desperation is starting to show

It seems quite clear that the CHIPS Act has now gone into desperation mode. You know that’s the case when everyone changes from what great benefits the Act will have to what a disaster things will be without it. Intel is threatening to cancel its groundbreaking in Ohio if the CHIPS Act doesn’t pass.

Pat Gelsinger on Ohio delay & CHIPS Act

US Commerce Secretary, Gina Raimondo said that a $5B Texas wafer fab, that will employ over 1000 people won’t happen if the CHIPS Act doesn’t pass.

Gina Raimondo CHIPS Act comments link

The Semiconductor Industry Association has also ramped up recent efforts to get the CHIPS Act passed.

Not everyone is on board with the CHIPS Act. Legislators seem to be raising more questions. The highly respected and regarded Robert Reich, who is bi-partisan and worked for Presidents Ford, Carter, Clinton and Obama has written a scathing rebuke of CHIPS for America as “corporate welfare”

Robert Reich CHIPS Act link

The problem we see is time is running out. We are a month away from summer congressional recess and after that we get into full blown election mode during which nothing of substance will get done.

January 6th has sucked most of the oxygen out of the room, including away from Ukraine and even inflation. Chips are so far down the list they are forgotten about. It would be a Hail Mary if the CHIPS Act gets passed at this point

The Stocks

Obviously the potential end of the cycle and reduced demand coupled with potentially excess supply is not a good thing.

The CHIPS Act which was likely more important for its investment tax credit than the paltry $10B a year in pork barrel aid doesn’t help matters and hurts the US specifically.

Obviously semiconductor equipment makers are on the end of the whip as usual. What’s bad for chip makers is usually way worse for chip equipment makers. No surprise here.

In terms of chip makers, we think TSMC remains the best positioned overall and in command of the entire industry. The second and third tier chip makers will suffer the most and have the most risk.

TSMC has the margin and ability to set pricing in the market such that its factories remain full while smaller less capable competitors who live under TSMC’s price umbrella will see their utilization fall and impact their earnings. Global Foundries that could only get to break even and profitability during the biggest chip shortage and associated demand is likely most at risk if demand weakens as customers go back to TSMC where they came from.

SMIC likely continues to do well even though they are second tier they have a captive audience in China.

Apple, Qualcomm, Broadcom, Nvidia, AMD and Intel will still depend on TSMC.
We think there could be significant downside potential on the memory side as memory tends to be a bit more consumer related.

We could see significant impact at both Samsung and Micron and have already heard about memory weakness in H2 2022.

The lack of the CHIPS Act could disadvantage US companies and projects and generally will weaken the US competitive positioning.

Its unclear if the CHIPS Act could be brought back to life after the fall election before the end of the year if it doesn’t get passed in the next 4 weeks. Its more likely that it will either go away entirely or get pushed deep into next year especially especially if there is a change in control of the legislative branch which will have bigger priorities.

Overall there seems to be a lot more near term downside than upside risk. The longer term certainly remains great but things could get even choppier in the next few quarters.

Also read:

CHIPS for America DOA?

Has KLA lost its way?

LRCX weak miss results and guide Supply chain worse than expected and longer to fix

Chip Enabler and Bottleneck ASML

Podcast EP92: The Impact of a Specification-Driven Correct-by-Construction Approach on Design and Verification with Agnisys

Podcast EP92: The Impact of a Specification-Driven Correct-by-Construction Approach on Design and Verification with Agnisys
by Daniel Nenni on 07-01-2022 at 10:00 am

Dan is joined by Anupam Bakshi, founder and CEO of Agnisys. Anupam has more than two decades of experience implementing a wide range of products and services in the high tech industry. Prior to forming Agnisys, he held various management and technical lead roles at companies such as Avid Technology Inc., PictureTel, Blackstone, Cadence and Gateway Design Automation.

Anupam discusses the Agnisys specification-driven development flow, in which users describe registers and sequences for system-on-chip (SoC) and intellectual property (IP) projects, and then automatically generate the RTL design and verification suite. The benefits of this approach and where it is applicable are discussed.

The views, thoughts, and opinions expressed in these podcasts belong solely to the speaker, and not to the speaker’s employer, organization, committee or any other group or individual.

July 1, 2022July 18, 2022

The Lines Are Blurring Between System and Silicon. You’re Not Ready.

The Lines Are Blurring Between System and Silicon. You’re Not Ready.
by Daniel Nenni on 07-01-2022 at 8:00 am
Categories: Ansys, Inc., EDA, Events
4 Comments

3D-ICs bring together multiple silicon dies into a single package that’s significantly larger and complex than traditional systems on a chip (SoCs). There’s no doubt these innovative designs are revolutionizing the semiconductor industry.

3D-ICs offer a variety of performance advantages over traditional SoCs. Because of their integrated, stacked design, they eliminate the reticle limits that define the maximum size of a single die. They deliver faster signal speeds with lower power consumption requirements. Stacking memory chiplets directly on top of logic minimizes delays. 3D-ICs enable design innovation, by allowing a combination of different silicon process technologies to be applied in a single integrated system.

With their potential for lower power, greater integration density, and faster data rates, 3D-ICs are poised to help deliver on the promise of 5G and 6G networks, the Industrial Internet of Things (IIoT), product autonomy, vehicle electrification, and other emerging technology trends. Based on the degree to which they can outperform any single chip, 3D-ICs represent the future of the global semiconductor industry.

But is your team prepared for that future? Along with their significant benefits, 3D-ICs deliver some daunting challenges for product development organizations that have built their success on single-die designs.

Changing IC Design: The Cultural Impact

One of the biggest challenges is cultural. As 3D-ICs revolutionize the marketplace, they’re also quietly revolutionizing foundational product development processes across the worldwide semiconductor industry.

The 3D-IC revolution is blurring the lines between system and silicon, as three traditionally separate design disciplines — chip design, package design, and board design — are now merging. Successfully designing and fabricating a 3D-IC requires significant synergy between all three disciplines.

As design spans multiple dies, the packaging of these chips becomes an integral part of a larger system, which means that chip and package designers must optimize their solutions collaboratively and simultaneously. For example, as logic blocks are dispersed across two or more dies, they communicate through wiring positioned in the package substrate or interposer layer — merging package design with the floorplanning of the chip. Chiplets stacked vertically on top of other chiplets, and connected through direct microbump contacts, further blur the lines between package and die. The interconnect routing on a large 3D-IC substrate — which is a complex mixture of chip and board strategies like non-Manhattan routing, river routing, and electromagnetic modeling — also demands a crossfunctional, concurrent design approach.

The complex, stacked design of 3D-ICs continues to blur the lines between silicon and system. As the packaging of each individual chip becomes part of a larger system, chip, board, and package designers must work together collaboratively and concurrently to optimize overall product performance. The Ansys simulation platform is built to manage this type of multiphysics, interdisciplinary engineering analysis, delivering best-in-class physics capabilities along with seamless workflows and design automation.

While every company’s process for managing these complex engineering problems is different, the easy separation between chip, package, and board is now being definitively erased.

The problem? Suddenly it’s unclear who is responsible for what, and who is accountable for the ultimate success of a given 3D-IC design. Whose priorities are more important? Who gives the final signoff? And how exactly should cross functional collaboration happen? In many organizations, entirely new competencies and roles are being added to the traditional product design team. Even more challenging, today, those groups typically don’t even exist in the same company.

In the new 3D-ICs world , cross functional and interdisciplinary experts now need to work together as a close-knit team that actively collaborates on every aspect of design on a daily basis. Together, they need to optimize the board, the package, and the silicon simultaneously. Functional silos and a serial design process, characterized by handoffs among disciplines, must be replaced by cohesion, concurrent design, and teamwork.

Equally Important? The Technology Impact

How can semiconductor manufacturers support this new level of collaboration? A key requirement is to address their second big challenge: embracing of new technology approaches that are purpose-built for the kind of concurrent, system-level design required by 3D-ICs. Today product development teams not only need to optimize designs at the system level — considering component interactions and connection points — but they also need to consider novel physics that they’ve never analyzed before.

As just one example, power dissipation is a primary constraint in 3D-IC design, and optimizing this performance aspect requires a true multiphysics approach. Mechanical analysis, including modeling the stress and warpage of the package, must be considered from the earliest stage. It must be analyzed concurrently with floorplanning because the suboptimal placement of hot and not-so-hot components can have disastrous implications for stress, warpage, and ultimate power dissipation. Another novel, multivariate challenge is the crossfunctional analysis required to eliminate low-frequency power supply oscillations between components on the substrate.

Traditional single-physics simulation tools, applied by different functions in a serial approach, are simply not up to the challenge of 3D-IC design.

. In today’s fast-paced, hypercompetitive environment, neither option supports success.

The Ansys Platform: A New Approach

There is good news. Ansys has developed a purpose-built platform for collaborative and concurrent 3D-IC design. The Ansys platform is a modern concept, built for the 3D-IC .

Backed by 50 years of industry leadership, Ansys delivers gold-standard revolution simulation solutions necessary for designing an optimal 3D-IC design. These include power integrity, reliability, electromagnetics (EM), thermal, computational fluid dynamics (CFD) and mechanical analyses. Now Ansys delivers these capabilities via an open, flexible, extensible, and high-capacity design platform that enables product development teams to subject the entire 3D-IC design to real-world operating parameters and simultaneously optimize the multiple physics.

While large, well-resourced corporations benefit from a vertically integrated culture that enables interdisciplinary collaboration — and they can more easily introduce bespoke silicon designs — smaller, more horizontally integrated companies may struggle to achieve the level of teamwork and crossfunctional collaboration needed to optimize 3D-ICs.

By leveraging the unified Ansys platform, every product development team can easily collaborate across functions in a shared, multiphysics design ecosystem. Design automation, synergistic workflows, and a best-in-class multiphysics portfolio from Ansys support 3D-IC innovation and speed new designs to market, without sacrificing analytic rigor.

The Ansys platform enables multiple physical effects, multiple integration points, and system-level performance to be considered quickly and cost-effectively. It encapsulates and delivers the required expertise, including novel physics, in an intuitive, easy-to-use solution that’s accessible to the entire cross functional design team.

As the lines continue to blur between silicon and system, Ansys helps to make these challenges manageable, focusing on fast, easy component and system-level analysis and verification.

Learn More About the Ansys Platform at DAC 2022

Want to adopt a revolutionary new design approach that positions you for leadership in the 3D-IC revolution? Learn more by visiting Ansys at Booth #1539 at the upcoming Design Automation Conference (DAC), held in San Francisco July 10-14. Request a meeting or product demo now and prepare for success in today’s new environment of blurred lines and concurrent design. Reserve your space for Ansys’ DAC Breakfast event, 3D-IC Design in a 2D World cohosted with Synopsys, and moderated by yours truly.

Also Read:

Multiphysics, Multivariate Analysis: An Imperative for Today’s 3D-IC Designs

A Different Perspective: Ansys’ View on the Central Issues Driving EDA Today

Unlock first-time-right complex photonic integrated circuits

July 1, 2022June 28, 2022

Cadence Execs Look to the Future

Cadence Execs Look to the Future
by Dave Bursky on 07-01-2022 at 6:00 am
Categories: Cadence, EDA, Events

Everything is becoming digital, and everything digital requires semiconductors. Cadence’s President and CEO, Dr. Anirudh Devgan, highlighted this at the recent CadenceLIVE user conference and discussed many of the company’s accomplishments and future directions. Dr. Devgan also sees the emergence of data—especially unstructured data as another major trend. Such data also affects compute, the cloud, and the edge and is transformational in many ways.

About 45% of Cadence’s customers are system companies that possess both hardware and software and are developing their custom semiconductor solutions. Even traditional semiconductor companies are turning into system companies, as the complexity of their design requires software and system-level hardware to deliver a solution. Mechanical and electrical systems are also converging—mechatronics—and Cadence must ensure it has solutions that cater to the emerging trend. Cadence is partnering with well-established leaders such as Dassault on the mechanical front to link the spheres of mechanical and electronics. As this trend continues, Cadence sees advanced packaging and PCB design playing a more critical role.

Cadence is investing about 40% of its revenue in R&D—one of the largest percentages of any large public company. Cadence has more than 9,500 employees, and more than 8,100 are engineers. As Dr. Devgan stated, the challenge has been to improve productivity and make the design easier to implement, from the transistor level to the cell level to design reuse with intellectual property (IP). One of the tools that the company introduced was the Fidelity CFD software, which provides a streamlined CFD workflow for design, multi-disciplinary analysis, and optimization in a single environment.

The next big frontier will be using AI-based EDA tools to aid in productivity and optimization. A lot of EDA is optimization—place-and-route, layout, and other aspects; however, in the systems space, Cadence wants to ensure the simulation is state of the art; there remains much room in optimization to automate design. At this year’s CadenceLIVE event, Cadence introduced the Optimality Intelligent System Explorer, which delivers very impressive results with its AI-driven multidisciplinary analysis and optimization (MDAO) technology for optimal system design and accuracy. The company also has hardware platforms—Palladium Z2 and Protium X2—that provide a hardware acceleration solution from debug to full software evaluation.

The next step—Cadence OnCloud—a cloud-based design solution where all a designer needs is a web browser to launch Cadence software. It is a flexible consumption-based model with a monthly subscription license and a set number of CPU hours. Designers can purchase more hours as their compute needs increase.

Following Dr. Devgan’s keynote, Tom Beckley, Senior Vice President and General Manager of the Custom IC & PCB Group at Cadence, outlined his group’s tool developments and some future directions. He highlighted the significant increase in the number of mechanical engineers (MEs) that Cadence has hired—about 200 MEs were brought on board to deal with future packaging and thermal design challenges.

Mr. Beckley sees a perfect storm coming in electronics, which is really about the shortage of semiconductors impacting many industries. Additionally, he sees “industry 4.0” unfolding—factories, manufacturing, and delivery are all increasingly electrified, intelligent, and automated. This will result in smart products and an increase in the use of artificial intelligence (AI) and machine learning (ML), which generate large amounts of data.

Over the last few decades, the semiconductor industry has been driven by Moore’s Law, which guided improvements to achieve higher performance, lower power, smaller area, and until recently, lower cost. Additional innovations, roughly grouped as “More-than-Moore,” adds techniques such as new transistor structures, chip stacking, the use of chiplets, and other packaging approaches to improve system integration further. Such packaging approaches also allow the mixing and matching of technologies—optical, RF, high voltage, analog, and digital in a single package.

Cadence is investing heavily in its multiphysics system analysis portfolio. Its solvers are distributed and parallelized, providing higher capacity and performance. The company also enables cross-platform design and analysis for better system optimization. For example, Cadence integrates its Celsius Thermal Solver for package and PCB electrothermal analysis with its Voltus IC Power Integrity Solution, which does IC power integrity signoff so power models can be exchanged in real-time. System heat dissipation always involves both conduction and convection, which is part of the IC package to PCB interface. Finite element analysis can be used to solve the dissipation issues, but then the enclosure and airflow is a fluidics challenge, which is why Cadence is integrating its Fidelity CFD solvers with Voltus and Celsius.

Everything has to be fully modeled and simulated. Cadence has developed several new solutions extending the current Allegro and Virtuoso platforms to support the next generation of wafer-level 3D packaging. The Integrity 3D-IC Platform includes system-level planning, full design, and the company’s analysis, extraction, and verification technologies. Cadence has also partnered with Dassault to connect the Allegro PCB Design software with Dassault’s 3D Experience platform. This transforms the basic electromechanical product development and establishes the first cloud-based end-to-end mechatronic solution. The company has integrated SOLIDWORKS with OrCAD and Allegro to target the mainstream companies.

To handle next-generation RF and millimeter-wave design solutions, tools from Cadence will enable designs in the 30-to-300GHz frequency bands for systems beyond current 5G standards. This will be necessary for the next generation of applications, such as the metaverse, which needs rapid data transmission. Telecom, automotive radar, remote sensing, image security screening, and defense applications will drive the mmWave market with an expected growth of 25% to 30% over the next decade.

Cadence is also partnering with Ericsson on RF and mmWave solutions for complex MIMO antenna arrays and beamforming designs. Such designs demand changes to how RF ICs are designed—the power amplifiers, transceivers, and other circuits. The RF circuits are very sensitive to physical layout, which forces designers to control transmission line widths and lengths during design to achieve the desired impedance values for the circuit. Cadence has integrated Virtuoso for custom ICs with Allegro PCB design to have a single “golden” schematic for RF. The company is also integrating Cadence AWR Microwave Office with Virtuoso Platform, allowing MMIC, TIMIC, and filter designs to move from Microwave Office into Virtuoso for RF SoC design. The SoCs can then move back into Microwave Office for module design or to Allegro for PCB design.

Finally, Mr. Beckley detailed the AI enablement of the Cadence system analysis portfolio. This is expected to deliver a 10X improvement in design productivity plus optimized designs. With the Optimality Explorer, designers can select multiple performance goals to optimize—from the package through to the PCB and back to the package and the chip. With the AI-enabled Optimality Explorer software, designers can allow the software, the cloud, and the processors to do the heavy lifting. All of Cadence’s best-in-class solvers can run on the Optimality engine in parallel. The software can simultaneously address multiple objectives with more than 100 parameters using deep learning technology.

Also read:

Refined Fault Localization through Learning. Innovation in Verification

224G Serial Links are Next

Tensilica Edge Advances at Linley

Podcast EP91: A Tour of Agile Analog’s Ground-Breaking Technology with its New CEO, Barry Paterson

Podcast EP91: A Tour of Agile Analog’s Ground-Breaking Technology with its New CEO, Barry Paterson
by Daniel Nenni on 06-30-2022 at 10:00 am

Dan is joined by Barry Paterson, Agile Analog’s new CEO. Barry has held senior leadership, engineering and product management roles at Wolfson Microelectronics and Dialog Semiconductor. He has been involved in the development of custom mixed-signal silicon solutions for many of the leading mobile and consumer electronics companies across the world and has a technical background in Ethernet, audio, haptics and power management.

Barry discusses Agile Analog’s unique IP portfolio and supporting software that facilities migration and optimization for any process node. Barry also covers the breadth of IP available, typical applications and plans for upcoming shows.

The views, thoughts, and opinions expressed in these podcasts belong solely to the speaker, and not to the speaker’s employer, organization, committee or any other group or individual.

June 30, 2022October 15, 2023

Using IP-XACT, RTL and UPF for Efficient SoC Design

Using IP-XACT, RTL and UPF for Efficient SoC Design
by Daniel Payne on 06-30-2022 at 6:00 am
Categories: Defacto Technologies, EDA

The ESD Alliance collects and reports every quarter the revenue trends for both EDA and Semiconductor IP (SiP), and the biggest component for the past few years has been the SiP, as IP re-use dominates new designs. For Q4 of 2021 the total SiP revenue was $1,314.3 Million, enjoying a 24.8% growth in just one year. Here’s a chart to better show the IP trend:

How are engineers re-using all of this IP in their designs? EDA, IP and systems companies created the SPIRIT Consortium back in 2003 to address IP reuse, and by 2009 this group merged with Accellera, so there’s a long history to standardize how IP is defined and reused with IP-XACT, an XML format. The first IEEE standard for IP-XACT was named 1685-2009, then in 2014 it was superseded by IEEE 1685-2014. Defacto Technologies has been offering EDA tools to use IP-XACT more efficiently for 10 years now.

SoC Compiler

To integrate all of the IP blocks used in a new SoC design requires a methodology, and Defacto supports a front-end design flow that handles RTL, IP-XACT, UPF, LEF/DEF and SDC formats, getting your design ready for logic synthesis. SoC Compiler is the EDA tool from Defacto used for:

Design extraction and reuse for existing projects
IP connectivity insertion
SoC creation and assembly
Packaging at IP, subsystem and SoC levels
Generation of RTL, IP-XACT and other design collaterals

SoC Compiler Design Flow

SoC Compiler fully supports both the 2009 and 2014 versions of IP-XACT, so it works with all IP provided by vendors. A new feature in SoC Compiler is the ability to automatically extract the system memory map. Here’s an example of how RTL blocks on the left are turned into a memory map on the right, saving you time by not requiring any manual updates.

Extracting System Memory Map

Connectivity Insertion

During SoC assembly there is connectivity insertion, where all of the IP blocks are connected, then creating connections between different ports. An input port for source and destination port for recipient need to be connected. This process is now highly complicated because of the number of connections that are expected. Using SoC Compiler manages automatically the interconnect used between AMBA AXI and other standard interfaces, just by reading RTL and IP-XACT.

UPF

The Unified Power Format – UPF, started in 2006 and has been used to define the power control intent for chip designs. In the SoC Compiler tool flow it will create a UPF file that is correct-by-construction, allowing you to validate power intent consistency.

UPF Flow

The new ability added to SoC Compiler for UPF are:

Promotion – merge power-intent into higher scope
Demotion – split or propagate power-intent into lower scope

So it’s easy to restructure your IP, then automatically update the UPF files without resorting to manual and tedious editing.

UPF – promotion, demotion

DFT

To reach the highest test coverage goals, and reduce test time, an ATPG tool can propose a list of Test Points, but the problem is that this happens too late in the design flow, after logic synthesis. A new feature in SoC Compiler is for Test Point exploration, where you define the target coverage, type and number of Test Points, and the location of inserted Test Points, then it creates a new design with Test Points added. This allows you to quickly trade-off the number of Test Points to be used vs coverage.

Test Point Exploration

DAC 2022

When visiting San Francisco from July 10-14 at Moscone Center, West Hall, make sure to stop by the Defacto Booth on the first floor, #1543. Ask to see Bastien Gratréaux or Chouki Aktouf.

Innova Advanced Technologies

A new spin-off from Defacto was founded in November 2020, Innova Advanced Technologies, and that company is focused on a design flow, resource and project management portal. This approach replaces in-house tools to manage design flows.

Innova PDM

Summary

SoC design with IP reuse is a big challenge, because of the scale and complexity involved, so using the most efficient EDA tool flow makes economic sense. Defacto Technologies has been addressing this challenge through automation in SoC Compiler using standard formats like IP-XACT, UPF and RTL. The new features with each release are designed to save your precious SoC design time by eliminating manual tasks.

Related Blogs

June 29, 2022June 28, 2022

Using an IDE to Accelerate Hardware Language Learning

Using an IDE to Accelerate Hardware Language Learning
by Daniel Nenni on 06-29-2022 at 10:00 am
Categories: AMIQ EDA, EDA, RISC-V

Indian Institute of Technology IIT Bhubaneswar

Recently, in one of my regular check-ins with AMIQ EDA, I was pleased that they linked me up with an active customer. The resulting post summarized my discussion with three engineers from Kepler Communications Inc. They talked about using one of the AMIQ EDA products in the design of FPGAs for space-borne Internet connectivity. I told Cristian Amitroaie, CEO and co-founder of AMIQ EDA, that I enjoyed the experience and would be glad to talk to other users any time.

Cristian told me that they work with more than 150 companies in more than 30 countries, and then he mentioned that they also have many users in universities. I really like it when hardware and software vendors provide free or deeply discounted products to educational institutions. It gives students access to advanced technology that their schools cannot afford to buy at commercial prices and provides them with experience highly relevant for employment opportunities when they graduate. This system benefits the vendors as well; if the students like the products they use in college they may wish to buy them and continue using them when they are practicing engineers.

Naturally, I asked Cristian if he could arrange a discussion with one of their educational users. He kindly arranged for me to talk with Dr. Srinivas Boppu, Assistant Professor at Indian Institute of Technology (IIT) Bhubaneswar. The following covers the key points in our conversation.

Thank you for joining me today, Dr. Boppu. Anyone in engineering knows the excellent reputation of IIT. Can you please tell us a bit about the Bhubaneswar campus and your role there?

I’ll be glad to. Bhubaneswar is a city of about a million people and the capitol of the Indian state of Odisha. IIT Bhubaneswar was founded in 2008 during a major expansion of the IIT system, which now has 23 locations. I joined the faculty in 2017 to focus on IC design research and IP development. In addition to teaching classes, I currently have two PhD students, two Master’s students, and seven Bachelor’s students.

How did you get involved with AMIQ EDA?

Starting in 2011, I was a hands-on user while pursuing my PhD at Friedrich-Alexander-University of Erlangen-Nürnberg in Germany. I was writing VHDL while designing processor arrays for accelerating nested loops in computer programs. I had experience with integrated development environments (IDEs) for software and I wondered whether there might be a similar solution for hardware languages such as Verilog and VHDL. I discovered AMIQ EDA and requested an educational license for their Design and Verification Tools (DVT) Eclipse IDE.

How did you like the tool?

I found it really useful. It autocompleted the names of variables and other design elements, generated templates when I was instantiating new constructs in the code, and had great check and debug features. It saved me a lot of time and I remembered that when my students began writing Verilog code for projects at IIT. I started working with AMIQ EDA again, and they provided us all the educational licenses that we requested. I really appreciate that.

What sort of things are your students designing?

Let me start with the undergraduate courses. When we teach our advanced digital system design course, we require our students to complete a non-trivial final project. They write register transfer level (RTL) code for the hardware and develop a simple testbench, all in Verilog. They generally choose to design some sort of processor—Java Virtual Machine, IP block implementing the Google Bfloat16 floating-point spec, MIPS CPU, etc. The students also have to synthesize their design for FPGAs and demonstrate its operation in the lab, so this is indeed a significant project.

How does DVT Eclipse IDE help them?

For most students, this course is their first exposure to Verilog, which is rather different from a programming language such as C/C++ or Java. For example, they often have a hard time understanding blocking versus non-blocking assignments. Because the IDE provides templates and offers menus of options, they don’t have to learn every subtle detail of Verilog syntax and semantics. In a way, the IDE is almost like a coach, guiding them as they write code and nudging them in the correct direction with auto-fix suggestions when they make mistakes. I think that it greatly accelerates learning a new hardware language, and even for us long-time users it continues to have high value.

What about your graduate students? Do they have similar experiences?

Yes, I would say so. They often know Verilog fairly well already, but the designs they create are much larger and more complex. Last year I had a student who designed a vectorized floating-point processor comprising about 10K lines of Verilog code in 90 source files. Another student designed a 10×10 processor array that spanned six FPGA devices. Most of the students in my group use DVT Eclipse IDE for their code development and management. My graduate students typically use the IDE for 9-12 months, whereas students in undergraduate classes use it for only a month or two.

What are the benefits seen by you and your students?

I’ve already mentioned faster learning and faster coding, even for experienced users. We like the way that the IDE manages a whole project, which is especially important for the larger designs. Its incremental compilation and instant checking capabilities improve code quality and correctness, and they help my teaching assistants and me review the student designs. We are able to open the documents and reports at any time.

DVT Eclipse IDE helps users understand code that they didn’t write themselves, and it supports mixed languages. Both of these features are proving vital in a mixed-precision floating-point design, where the graduate student inherited some VHDL IP but is writing new code in Verilog.

How has your experience been working with AMIQ EDA?

They have been tremendously supportive. They’re great to work with and are responsive to suggestions for new features.

Could you give an example of something you wish DVT Eclipse IDE did?

We have some interest in using the Bluespec language because it is higher level than Verilog and is used for some RISC-V projects. We have asked AMIQ EDA to consider adding support and they are looking into it.

What’s next for you and your students?

I don’t expect our hardware design courses to change a lot, but the graduate projects are constantly evolving and growing. We have one design underway that will likely have a million gates. We also have some new PhD work in collaboration with other universities, and a common IDE will help keep the teams in sync.

We plan to try DVT IDE for Visual Studio (VS) Code, which AMIQ announced recently. Many of our students have experience with VS Code for software languages so we expect them to have interest in Verilog support as well. Finally, AMIQ EDA has directed my attention to some diagram generation features that we have not used much, so I plan to check those out soon.

Thank you very much for your time. It is good to know that AMIQ EDA is able to help educate the next generation of hardware engineers.

Thank you as well.

Also read:

AMIQ EDA Adds Support for Visual Studio Code to DVT IDE Family

Automated Documentation of Space-Borne FPGA Designs

Continuous Integration of RISC-V Testbenches

June 29, 2022February 25, 2023

Stalling to Uncover Timing Bugs. Innovation in Verification

Stalling to Uncover Timing Bugs. Innovation in Verification
by Bernard Murphy on 06-29-2022 at 6:00 am
Categories: AI, Cadence, EDA

Artificially stalling datapaths and virtual channels is a creative method to uncover corner case timing bugs. A paper from Nvidia describes a refinement to this technique. Paul Cunningham (GM, Verification at Cadence), Raúl Camposano (Silicon Catalyst, entrepreneur, former Synopsys CTO and now Silvaco CTO) and I continue our series on research ideas. As always, feedback welcome.

The Innovation

This month’s pick is Deep Stalling using a Coverage Driven Genetic Algorithm Framework. The paper published in the 2021 IEEE VLSI Test Symposium. The authors are from Nvidia.

Congestion is most likely to expose problems which can lead to deadlocks, ordering rule violations and credit underflow/overflow problems. Finding such problems requires creating a method to randomly stall FIFOs and pipelines to tease out those timing corner cases. Stalls create backpressure which is most likely to trigger such problems.

Verifiers can select which FIFOs to stall, and when. Given many FIFOs in a design, randomization is the default method to (weakly) optimize coverage in analysis. On the other hand, it creates concerns that it may miss many potential problems. The authors show how they apply genetic algorithms to learn how to improve coverage, using FIFO fill and RAM occupancy statistics as coverage metrics.

Paul’s view

This is a tight paper, easy to read, and provides a clear contribution. It tackles a very specific but important problem: how to most efficiently cover FIFO stalls in functional verification. The authors share that their GPU testbenches have special code to artificially force a FIFO to report full. This code is controlled by some randomized parameters: the probability of triggering the force, and the time window over which the force is held. There is a set of such parameters for each FIFOs in the design.

They use a genetic algorithm to select the best values of these parameters to maximize coverage. Each iteration of the genetic algorithm requires re-running all tests, which limits both initial population size and evolution cycles for the algorithm. To get around this limit, they train a neural network to predict functional coverage based on parameter settings and use this neural network for natural selection in their genetic algorithm rather than actually re-running tests. Using this neural network they are able to achieve a 60x increase in genetic algorithm capacity.

Results are solid – on a key system level coverage metric for the number of stalled GPU shader threads, the authors method can push up to 126 out of a theoretical maximum of 128 versus a baseline of only 90 without using the genetic algorithm and neural network. Using only the genetic algorithm but no neural network achieves 113.

In their introduction the authors note that there is no parameter in their testbench to directly control simultaneous stalling of multiple FIFOs. I can’t help but feel that such a parameter could be very effective to build up “backpressure” from multiple FIFOs being stalled and drive up corner case coverage. Identifying the appropriate groups of FIFOs to stall simultaneously to achieve the necessary backpressure could be well suited to the genetic algorithm proposed by the authors.

Raúl’s view

When a FIFO is full it stalls; it backpressures the transmitter trying to send a value to it. In well-designed systems this rarely occurs. To be able to simulate what happens if FIFOs fill, Nvidia inserts artificial stalls to generate backpressure. They generate stall lengths in Monte Carlo simulation to meet a given coverage goal.

The authors accelerate this process in two ways:

Using a Genetic Algorithm framework that evolves stall parameters using elitism, Roulette Wheel Selection and Standard Crossover. This boosts coverage, normalized by simulation time, by 163% for a design called UnitA and by 88% for UnitB. Looking at individual coverage objectives, most of them get a boost. One example showed 472%, although 4 out 11 don’t get any boost. In one case there was slight drop because the multi-objective evolutionary algorithm was trading this objective to maximize others.
A Deep Learning model learns the relationship function between the stalling parameters and the coverage metric. The DL model used is a “5-layered MultiLayer Perceptron (MLP) with batch normalization, dropout and RELU applied to all hidden layers. It uses a sigmoid activation function for the final layer.” It ran on 30,000 tests to generate data to train and validate the model. The model predicts the values for both the test data with an accuracy of 85% for the top 1,000 sorted tests and 57% for all 10,000 tests.

The authors conclude that they could intelligently tune stall parameters to significantly boost coverage metric over purely random stalling. This seems reasonable for the GA part. Although it may miss cases covered by a purely random approach as it favors certain parameter values. The DL model is an intriguing addition which presumably needs further development to rise above 57% accuracy.

It is a well written paper and easy to follow,. It focuses totally on the application and just states which genetic algorithm and deep learning model are used. I think this will appeal to designers and EDA tool builders who have added deep learning and genetic algorithms to their portfolio.

My view

In reading around this topic, I noticed multiple articles on backpressure routing in NoCs. This method may possibly have value there also.