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Coverage Analysis in Questa Visualizer

Coverage Analysis in Questa Visualizer
by Bernard Murphy on 08-10-2022 at 6:00 am
Categories: EDA, Siemens EDA

Questa coverage

Coverage analysis is how you answer the question “have I tested enough?” You need some way to quantify the completeness of our testing; coverage is how you do that. Right out of the gate this is a bit deceptive. To truly cover a design our tests would need to cover every accessible state and state transition. The complexity of that task routinely invokes comparisons with the number of protons in the universe so instead you use proxies for coverage. Touching every line in the RTL, exercising every branch, every function, every assertion and so on. Each a far cry from exhaustive coverage., but as heuristics, they work surprisingly well.

Where does coverage-based analysis start?

Granting that testing cannot be exhaustive, it should at least be complete against a high-level specification, it should be reasonably uniform (no holes), and it should be efficient.

Specification coverage is determined by the test plan. Every requirement in the specification should map to a corresponding section in the plan, which will in turn generate multiple sub-requirements. All functional testing starts here. Coverage at this level depends on architecture and design expertise in defining the testplan. It can also often leverage prior testplans and learning from prior designs. Between expertise and reuse product teams build confidence that the testplan adequately covers the specification. This process is somewhat subjective, though traceability analytics have added valuable quantification and auditability in connecting between requirements and testplans.

Testing and coverage analysis then decomposes hierarchically into implementation test development, which is where most of us start thinking about coverage analysis. Each line-item in the testplan will map to one or more functional tests. These will be complemented by implementation-specific tests around completeness and sequencing for control signal, registers, test and debug infrastructure and so on.

Refining implementation coverage

Here is where uniformity and efficiency become important. When you start writing tests, you’re writing them to cover the testplan and the known big-ticket implementation tests. You’re not yet thinking much about implementation coverage. At some point you start to pay attention to coverage and realize that there are big holes. Chunks of code not covered at all by your testing. Sure, exhaustive testing isn’t possible, but that’s no excuse for failing to test code you can immediately see in a coverage analysis.

Then you add new tests, or repurpose old tests from a prior design. You add constrained random testing, all to boost coverage however you choose to measure it (typically across multiple metrics: function, line, branch for example). The goal here is to drive reasonably uniform coverage across the design to an achievable level, with no unexplained gaps.

Efficiency is also important. Fairly quickly (I hope) you get to a point where adding more tests doesn’t seem to improve coverage much. Certainly you want to find the few special tests you can add that will further advance your coverage, but you’d also like to know which tests you can drop. Because they’re costing you expensive regression runtime without contributing any advantage in coverage improvement.

Questa Visualizer adds coverage analysis

It should be apparent that coverage analysis is the guiding metric for completeness in verification. Questa recently released coverage visualization in their Visualizer product to guide you in coverage analysis and optimization, during the course of verification and debug. Check it out.

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Intel and TSMC do not Slow 3nm Expansion

Intel and TSMC do not Slow 3nm Expansion
by Daniel Nenni on 08-09-2022 at 10:00 am
Categories: Foundries, Intel Foundry, TSMC
7 Comments

Pat Gelsinger and CC Wei SemiWiki

The media has gone wild over a false report that Intel and TSMC are slowing down 3nm. It is all about sensationalism and getting clicks no matter what damage is done to the hardworking semiconductor people, companies and industry as a whole. And like lemmings jumping off a cliff, other less reputable media outlets perpetuated this false report with zero regard for the truth.

By the way, lemmings only jump off cliffs when they become overpopulated and migrations end badly. So maybe that is what has happened here, media outlets have become over populated.

For the record:

-Q2 2022 Taiwan Semiconductor Manufacturing Co Ltd Earnings Call

“CC Wei: Next, let me talk about the tool delivery update. As a major player in the global semiconductor supply chain, TSMC work closely with all our tool supplier to plan our CapEx and capacity in advance. However, like many other industries, our suppliers have been facing greater challenges in their supply chains, which are extending toward delivery lead times for both advanced and mature nodes. As a result, we expect some of our CAPEX ($4B of $44B) this year to be pushed out into 2023.”

And an update on N3:

“CC Wei: Now let me talk about the N3 and N3E status. Our N3 is on track for volume production in second half of this year with good yield. We expect revenue contribution starting first half of 2023, with a smooth ramp in 2023, driven by both HPC and smartphone applications. N3E will further extend our N3 family with enhanced performance, power and yield. N3E will offer complete platform support for both smartphone and HPC applications. We observed a high level of customer engagement at N3E, and volume production is scheduled for around 1 year after N3. Our 3-nanometer technology will be the most advanced semiconductor technology in both PPA and transistor technology when it is introduced. Thus, we are confident that our N3 family will be another large and long-lasting node for TSMC.”

Yes, Intel had a challenging quarter and it will be a difficult year but my sources say that Meteor Lake, the first disaggregated chip with an Intel 4 CPU, TSMC N3 GPU, and a TSMC N5 base die and SoC is on track. Saphire Rapids I do not know. Since this involves stitching multiple Intel CPU tiles together there could be challenges but this seems to be a design/integration issue versus a process yield problem.

Pat Gelsinger has fixed the Intel process issues by changing the methodology to match what TSMC does, half nodes versus full nodes for advanced yield learning. As a result, I have complete confidence in Intel 4 and 3 moving forward as planned, absolutely.

-Q2 2022 Intel Conference Call Comments

Pat Gelsinger: For example, regaining our leadership begins with Moore’s Law and the capacity to deliver it at scale. Over the last 18 months, we’ve taken the right steps to establish a strong footing for our TD roadmap. We are well into the ramp of Intel 7, now shipping in excess of 35 million units. Intel 4 is ready for volume production in second half of this year and Intel 3, 20A and 18A are all at or ahead of schedule.

Pat also reorganized Intel design groups and decentralized them for increased autonomy. This will take time to see the results but I can assure you it was the correct thing to do.

I know having chicken little in the semiconductor hen house is fun to watch but it really is getting old. Check your sources and if they have zero semiconductor experience I would take it for what it is worth, entertainment.

And for those of you who want to know what really caused the automotive chip shortage:

“In the past two years they call me and behave like my best friend,” he told a laughing crowd of TSMC partners and customers in Silicon Valley recently. One automaker called to urgently request 25 wafers, said Wei, who is used to fielding orders for 25,000 wafers. “No wonder you cannot get the support.” CC Wei, TSMC Technical Symposium 2022.

Also read:

Future Semiconductor Technology Innovations

3D Device Technology Development

The Turn of Moore’s Law from Space to Time

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Fast EM/IR Analysis, a new EDA Category

Fast EM/IR Analysis, a new EDA Category
by Daniel Payne on 08-09-2022 at 6:00 am
Categories: Diakopto, EDA

IR Drop min

I’ve watched the SPICE market segment into multiple approaches, like: Classic SPICE, Parallel SPICE, FastSPICE and Analog FastSPICE. In a similar fashion the same thing just happened to EM/IR analysis, because after years of waiting we finally have a different approach to EM/IR analysis that works at the top-level of an IC that I’m calling Fast EM/IR analysis. I came to this conclusion after a video call with Maxim Ershov, CEO at Diakopto and Kelvin Khoo, COO at Diakopto.

EM/IR analysis has traditionally been approached at the transistor-level, or the cell-level, producing very accurate results, but at the expense of long run times as the design is assembled from sub-blocks, and then ultimately run on the top-level. The run times have got “out of control” in FinFET technologies as the size of the designs, and the number, magnitude and impact of parasitic elements have grown exponentially. As a result, it has become impractical to analyze EM/IR at the top-level because such simulations could easily take weeks.

In addition, traditional EM/IR tools are notorious for being very complicated and tedious to set up, use and interpret the results. They can also be used only very late in the design stages, when layouts are mostly complete and hard to change.

Diakopto’s PrimeX was developed in response to customers’ need for a new category of Fast EM/IR tools, that are capable of verifying top-level power nets, which is not feasible with other EM/IR tools. PrimeX delivers on this promise by trading off some accuracy for dramatic gains in speed, capacity, and ease of setup. But what makes PrimeX shine is the ease-of-use for novice users, along with insightful debugging capabilities that identify the few areas and elements (out of a sea of millions or billions) that cause EM/IR problems.

The majority of critical EM/IR problems are caused by “silly” layout mistakes, such as missing or insufficient number of vias, long narrow metal lines, cutouts in metal planes, poor connection of pad (cells) to the power nets, and insufficient number or sub-optimal placement of power switches. Design teams should not need to waste a couple of weeks by running fully accurate EM/IR analysis to detect and find these mistakes.

PrimeX enables a very fast resistance, EM and IR drop analysis, thanks to a novel “approximate computing” methodology. This “approximate computing” methodology includes a variety of different techniques, such as utilizing the design intent information, design hierarchy, simplifications using physics-based considerations.

This allows users to perform multiple quick iterations and to clean up layout mistakes early in the design phase. It also allows design teams to perform EM/IR analysis for very large power nets at the top-level in a few hours, instead of weeks, to detect the overwhelming majority of layout issues that cause EM/IR problems.

As an example, all power nets for a high-speed SerDes (112-224 Gbps) implemented in 5nm technology were analyzed in an overnight run using PrimeX.

PrimeX Flow

The tool also offers powerful debugging capabilities beyond what is commonly found in traditional EM/IR tools. It provides deep insight into EM/IR problems, and reports root causes in a top-down manner:  by net, by layer, power switches, and by polygon and colors over the layout.

In addition to speed and insights, PrimeX was designed from the start to be easy to use and set up. This means that it can be used by any design or layout engineer, without the need for lengthy training or for them to be experts in an EM/IR tool. In addition, PrimeX requires minimal configuration and set up, so there is no need for a dedicated expert or CAD group to bring up, maintain and support the tool and flow.

Another drawback of the traditional IC design flow is that EM/IR analysis happens quite late in the process, only after DRC/LVS for each block and for the top hierarchy level has become clean, requiring long iteration cycles, and long simulation times to get the current sources information. By this time, it is almost too late to make layout ECOs, and designers are in panic mode right before a tapeout deadline. The new methodology offered by PrimeX allows designers to analyze EM/IR earlier in the IC flow, and often prior to LVS clean, to pinpoint bottlenecks and choke points, and to clean up the design/layout much earlier.

IR drop distribution in power net VDD
Current density distribution in power net VDD

According to Diakopto, PrimeX has been adopted by 8 customers, several of which have made the tool their sign-off flow for the top-level EM/IR verification. PrimeX builds on the success of Diakopto’s flagship product, ParagonX, which has been adopted by over 40 customers for debugging IC designs sensitive to layout parasitics.

The headquarters for Diakopto is in San Jose, a strategic location for a smaller EDA vendor to be located, because of the density of IC firms in Silicon Valley. You can run the Diakopto tools on any Linux box (CentOS or Red Hat). PrimeX runs fast enough on a single core so far, that they haven’t done much on a parallel approach, but stay tuned. One CPU is sufficient right now.

Summary

EM/IR analysis tools have been around for over two decades now, and the limitations of capacity, slow run times, and LVS clean, are well understood by users. What’s new is that Diakopto has pioneered a new approach of Fast EM/IR analysis that complements the traditional EM/IR tools, allowing the fastest results, especially at the top-level of an SoC using leading edge nodes. PrimeX is disruptive, and should be welcomed by IC design teams.

Related Blogs

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EUV’s Pupil Fill and Resist Limitations at 3nm

EUV’s Pupil Fill and Resist Limitations at 3nm
by Fred Chen on 08-08-2022 at 10:00 am
Categories: Lithography
2 Comments

EUV Pupil Fill and Resist Limitations at 3nm p1

The 3nm node is projected to feature around a 22 nm metal pitch [1,2]. This poses some new challenges for the use of EUV lithography. Some challenges are different for the 0.33NA vs. 0.55NA systems.

0.33 NA

For 0.33 NA systems, 22 nm pitch can only be supported by illumination filling 4% of the pupil, well below the 20% lower limit for nominal throughput (Figure 1).

Figure 1. Allowed illumination for 22 nm pitch only fills 4% of the 0.33 NA pupil.

This means throughput could drop well below 100 wph @40 mJ/cm2 [3] due to most light being absorbed by the condenser before reaching the mask. The extra light absorption is itself a concern for component heating, for example. Consequently, 44 nm pitch patterning may be doubled to achieve 22 nm pitch, even with EUV.

0.55 NA

For 0.55 NA systems, the hope has been that single exposure can pattern both horizontal and vertical 22nm pitch features simultaneously, with pupil fill over 20%. However, some 2D features, such as 31 nm pitch staggered contacts/vias (Figure 2), are not conveniently compatible with this exposure, due to the obscuration eliminating the lowest diffracted order [4].

Figure 2. A quasar illumination shape is required for satisfying both 22 nm horizontal and vertical pitches in the layout, but 31 nm staggered features would restrict the illumination further, to below 20% of the pupil.

A smaller portion of the 22 nm pitch quasar illumination such that the lowest diffracted order avoids the obscuration is safe to use, but fills less than 20% of the pupil, again meaning extra condenser absorption and reduced throughput as in the 0.33 NA case. This pattern incompatibility has not featured in prior lithography systems, as they do not have any obscuration. But for the 0.55 NA EUV system, if this staggered 2D pattern needs to be kept along with the horizontal and vertical features, it has to be exposed separately.

Even bigger concerns for single exposure?

22 nm (or smaller) pitch 0.55 NA single exposure will require the use of ultrathin (≤20 nm) resists, due to the reduced depth of focus. For a 20 nm resist thickness, the absorption would go down to 10% for chemically amplified resists (5/um) and a third for metal-oxide resists (20/um), meaning most energy would be absorbed underneath the resist. A limited portion of this energy may be returned to the resist as returning photoelectrons and secondary electrons, since these electrons are, in fact, emitted preferentially parallel to the resist/underlayer interface [5,6] (Figure 3).

Figure 3. At resist thicknesses below 30 nm, most EUV photons (black) are absorbed underneath the resist film (orange), with photoelectrons (red) and secondary electrons (green) emitted largely parallel to the interface. Photoelectron emission is preferentially directed along the electric field direction (purple), with subsequent secondary electron emission preferentially maintaining the photoelectron direction.

EUV exposure thus becomes less energetically efficient as resists grow thinner. Moreover, stochastic effects are aggravated by the reduced absorption. Consequently, multipatterning is expected to be significantly used even for EUV at 3nm. The environmental impact of EUV use therefore should be reconsidered [7].

References

[1] https://semiengineering.com/transistors-reach-tipping-point-at-3nm/

[2] https://www.allaboutcircuits.com/news/world-first-3nm-tapeout-lithography-Cadence-Design-Systems-Imec/

[3] https://semiwiki.com/forum/index.php?threads/nxe-3400c-euv-throughput-vs-dose.13707/

[4] E. van Setten et al., “High NA EUV lithography: Next step in EUV imaging “, Proc. SPIE 10957, 1095709 (2019).

[5] https://www.linkedin.com/pulse/demonstration-dose-driven-photoelectron-spread-euv-resists-chen/; M. Kotera et al., “Extreme Ultraviolet Lithography Simulation by Tracing Photoelectron Trajectories in Resist,” Jpn. J. Appl. Phys. 47, 4944 (2008).

[6] F. Tacoggna, “Secondary Electron Emission Models for PIC Simulations”, https://htx.pppl.gov/exb2018presentations/Friday/2%20Taccogna_SEE.pdf

[7] L-A. Ragnarsson et al., “Environmental Impact of CMOS Logic Technologies,” EDTM 2022.

This article originally appeared in LinkedIn Pulse: EUV’s Pupil Fill and Resist Limitations at 3nm  

Also Read:

ASML- US Seeks to Halt DUV China Sales

ASML EUV Update at SPIE

Obscuration-Induced Pitch Incompatibilities in High-NA EUV Lithography

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What’s Wrong with Robotaxis?

What’s Wrong with Robotaxis?
by Roger C. Lanctot on 08-08-2022 at 6:00 am
Categories: Automotive
7 Comments

Whats Wrong with Robotaxis

For some reason the obsession with robotaxis persists throughout the world and throughout the transportation industry. The collective conventional wisdom appears to be that getting rid of the human drivers of taxis and letting these vehicles freely operate presumably around the clock will save money and the environment.

Tesla’s Q2 earnings report puts the lie to this ill-placed optimism. While robotaxis are putt-putting around Phoenix, San Francisco, and Shanghai, human driven Teslas have notched 35M miles in “full self-driving” (FSD) Beta mode, according to CEO Elon Musk.

Musk says on the earnings call that FSD Beta with City Streets driving capability has been deployed to more than 100,000 Tesla owners. Commenting on the latest SmartDrivingCars podcast, Princeton’s Faculty Chair of Autonomous Vehicle Engineering Alain Kornhauser expressed his admiration for Tesla’s ability to recruit human drivers (i.e. Tesla owners) to help teach the computers how to drive. Kornhauser went further, estimating the value of the 35M miles of computer-assisted driving to be approximately $100M to Tesla at $3/mile.

Kornhauser is zeroing in on the critical differentiator between Tesla and every other autonomous vehicle developer. By deploying autonomous or semi-autonomous or self-driving technology in privately owned vehicles, Tesla is allowing the humans to teach the computers how to drive.

Musk and Tesla understand that humans are good drivers, in spite of getting a bad rap. Roads from city streets to highways were designed for human operation, so it makes sense to leverage human driving skills to refine the algorithms and fuel the neural networks that are ultimately expected to take over.

In contrast, robotaxis are operating based on rules-based assumptions and a see-plan-act “mindset” that must simultaneously anticipate and react to its driving environment. Robotaxis are essentially being asked, without much help, to understand how humans drive while being mindful of obeying the driving rules.

It’s a hopeless task with little prospect of short-term success. For these and other reasons Waymo is operating in the desert – to eliminate weather concerns – and Cruise Automation is operating at night – to mitigate issues around traffic congestion.

The nearly impossible objective of achieving full self-driving, long-promised by Tesla, is more likely to be achieved by Tesla because of its decision to keep the human “in the loop.” Robotaxis operate on the assumption that the human is the problem – the fly in the self-driving ointment.

This isn’t the only flawed assumption. The second flawed assumption is that robotaxis operated by computers that never become drowsy or tired will be more efficient and therefore lead to reduced emissions and energy consumption.

Based on Waymo’s Q2 data gathered from its operations in California, 92% of the vehicle miles traveled by Waymo vehicles were spent “loitering.” Only 8% of Waymo’s Q2 VMT was consumed carrying passengers or en route to pick up passengers.

The only possible justification would be that the pursuit of robotaxi development is expected to yield valuable insights into solving as yet unidentified transportation challenges. Color me skeptical.

Robotaxis are already having a deleterious impact on urban transit with notable traffic jamming incidents instigated by Cruise in San Francisco. But it is not just the catastrophic failures that are relevant. Robotaxis operated by Cruise and others around the world are adding their own quirks to the existing urban transportation chaos which is still evolving – post-COVID – to accommodate e-bikes and e-scooters, a proliferation of delivery vehicles, delivery drones, and ever-present pedestrians.

Robotaxis are also guaranteed to be more expensive to operate than taxis, while driving more slowly, and lacking the flexibility to travel beyond the city limits via highways.

Yet, for the time being, developers will continue to throw hundreds of millions of dollars (Cruise has a nine-figure quarterly cash burn rate) at robotaxis to solve a problem already adequately addressed by public transit and traditional taxis. Robotaxis are and will continue to be more expensive to operate, slower, more polluting, with a limited operational design domain, and a fundamental inability to equal or surpass existing human driving acumen.

Other than all of that, robotaxis make perfect sense. Send in the clowns.

Also read:

Wireless Carrier Moment of Truth

DSPs in Radar Imaging. The Other Compute Platform

Accellera Update: CDC, Safety and AMS

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KLAC same triple threat headwinds Supply, Economy & China

KLAC same triple threat headwinds Supply, Economy & China
by Robert Maire on 08-07-2022 at 10:00 am
Categories: Semiconductor Advisors, Semiconductor Services

KLA Tencor

-KLA sings same cautionary song as LRCX (with Intel Chorus)
-Sees similar softening of WFE & second half
-Same Government “notice” on China/14NM – Same supply ills
-We remain concerned about share loss in patterning

Deja Vue, all over again- Great QTR & Guide amid caution & softening

KLAC reported a very good result coming in at $2.49B and EPS of $5.81 versus street of $2.43B and EPS of $5.50. Guide is for $2.6B +-$125M and EPS of $6.25+-$0.55 versus street of $2.52 and EPS of $5.81. Management cut their outlook on 2022 WFE to $95B much as we heard from Lam the day before. To a large extent the words on KLA’s call and Lam’s call were almost exact copies…..great numbers clouded by a weakening and cautionary outlook

Its like groundhog day.

Same notice from Government on China and 14NM

KLA got the same memo on China and 14NM. Obviously very lacking in details it sounds a lot like ” be prepared for tougher licensing on China, details to follow”. No details and no commentary other than no impact to numbers (for now…).

Given that China was 29% of KLA’s business we would be very concerned. We think that much like litho tools its important for the government to curtail yield management as they are the learning tools that China needs and much like ASML there aren’t a lot of other sources. This is compared to process tools where there is significant non US competition.

On the positive side we think that most any tools not shipped to China should easily be directly to eager customers not in China so while there may be short term dislocation in the long run the impact from a China embargo will be minimal.

Share loss in patterning remains a problem

Even though management talks about patterning being a lumpy business, we are waiting for a positive lump. The numbers for patterning remain unimpressive and not just due to lumpiness. Patterning was only up 15% year over year and down 20% quarter on quarter while wafer inspection was up a whopping 49% year over year and up 20% quarter over quarter. Wafer inspection was over twice patterning.

We find it very telling that in KLA’s prepared slides they talked about the impressive growth and “leadership” position of wafer inspection but no mention of patterning which is not in a leadership position nor impressive growth.

Demand remains beyond great

Demand is super strong and obviously beyond KLA’s ability to supply. Any holes or push outs or cancelations in the order book can quickly be filled by those customers further down the waiting line. While perhaps not as strong as ASML, KLA is a close second with some product pushing two years out…..

Financials fantastic

It almost goes without saying that KLA has the greatest financial performance in the industry, even better than the monopoly that is ASML. Cash flow and use is great and margins remain super strong.

Supply chain issues appear to be company’s biggest concern

Supply chain issues continue. While they may be getting better they seem more like just constant, ever changing headwinds of one sort or another. It doesn’t seem to have that much if any negative impact on KLA’s numbers but the company obviously is just concerned about getting tools out the door, more or less on time.

We don’t see this issue going away any time soon and will certainly persist for the remainder of the year and well into 2023. Its unclear when will will get back to whatever normal now represents.

Intel cutting spending during KLA’s call

It is somewhat strange that while KLA was on the call talking about potential weakness in memory that Intel was on their earnings call cutting spending. Obviously KLA’s management wasn’t listening to the Intel call but its an interesting contrast in real time.

To be fair, Intel said they were still dedicated to technology spend but we could see delays and/or push outs or other spending changes coming out of Intel and its also likely that those changes last more than a few quarters.

The stocks

If you didn’t listen to the call and just went by the results and guidance, the stock should have been up strongly in the after market, but it wasn’t, clearly the anxiety of the the triple threat of the economy (memory), China and supply chain cast a pall over what should have been a celebratory party on the great results.

The stock market hates uncertainty and we have it in spades. We continue to think that the downside beta far outweighs the upside beta. There is too much to go wrong and we already know how great things are.

There is not a lot that makes us want to go out and buy the stock. The recent bounce seems to be somewhat of a mirage that things will continue to be wonderful and we aren’t headed into a downturn.

In case you think you have seen the the exact same words above before ….you did…you saw them yesterday in our note on Lam. Our feelings on the stock and the stocks reaction are the same as for Lam.

The only difference is the added negative of the Intel bad news which only makes the situation even worse today than yesterday….

If you don’t think we are in a chip downcycle by now you have been living under a rock…..

Yesterday it was Charles Dickens

Tonight its Yogi Berra, “Its Deja Vue all over again”.

About Semiconductor Advisors LLC
Semiconductor Advisors is an RIA (a Registered Investment Advisor), specializing in technology companies with particular emphasis on semiconductor and semiconductor equipment companies. We have been covering the space longer and been involved with more transactions than any other financial professional in the space. We provide research, consulting and advisory services on strategic and financial matters to both industry participants as well as investors. We offer expert, intelligent, balanced research and advice. Our opinions are very direct and honest and offer an unbiased view as compared to other sources.
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‌Also read:

ASML Business is so Great it Looks Bad

SEMICON West the Calm Before Storm? CHIPS Act Hail Mary? Old China Embargo New Again?

 

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The Semiconductor Market Downturn Has Started

The Semiconductor Market Downturn Has Started
by Malcolm Penn on 08-07-2022 at 6:00 am
Categories: Future Horizons, Semiconductor Services

Growth Rate Trends

What we alone said would surely happen, but what was widely denied by the industry, was confirmed with June’s WSTS Blue Book report.  Right on cue with our December 2021 forecast, the current semiconductor Super Cycle is finally drawing to a close and the 17th market downturn has now well and truly started.

The Macro Evidence

At the macro level, the worldwide semiconductor momentum indicator, pictured above, passed through the ‘Death Cross’ in March 2022 signifying storm clouds on the horizon; June’s market data saw the start of the storm.

Anecdotal indication of the downturn has also started to filter into the industry consciousness, especially at the commodity end of the market, with several second-tier foundry houses and IDMs reportedly mulling scaling back or postponing their planned capacity expansions.

Already Global Foundries has warned it expects to see its capacity utilization fall in the second half of the year, due to order cuts by its fabless clients, and Samsung is reportedly suffering a similar impact too.

The downstream knock-on effect on the semiconductor equipment and materials industry has already started to bite, with some firms starting to see second-half year push backs and delays.

PC and smartphone shipments, two key semiconductor market drivers, are both showing declines in the first half of 2022, with PC shipment now reportedly at their lowest level since 2019, and Smartphone shipments expected to show negative growth in 2022.

Products that require specific manufacturing capacities, such as automotive, are still showing signs of tightness, but the end market demand for cars is likely to soften as prospective customers, now squeezed by and struggling with inflation and a massive spike in energy costs, put off buying that new car.

With demand for consumer MCUs, display drivers, power management and other mass-market chips falling, nearly all mature node fabs have seen their customers scale back wafer starts for the second half of 2022 prompting several second- and third-tier foundries to start cutting prices.  Some are even rumoured to be offering fire-sale incentives and cut-price deals for additional wafer orders to maintain their fab utilization rates.

Such actions will, however, we believe, prove fruitless given the industry-wide pressure, and customer need, to offload bloated inventories, built up over the past two years of supply shortages.

Time will tell if customers violate their long-term agreements (LTAs) to ease inventory pressure or, if they do, what actions the suppliers could in reality actually do.

Whilst TSMC is in a better position overall, due to its market dominance especially at the leading-edge – leading-edge capacity is, by definition, always in short supply – it too will not escape the effects of the downturn, given the wide diversity of the end markets it serves.

We believe TSMC will need to tread very carefully indeed here if it is to avoid an inevitable antitrust challenge by its customers and competitors of market exploitation and price gorging if it carries out its plan to raise its prices in 2023 against the prevailing market trends.

Devil’s In The Detail

At the detailed level, monthly IC unit shipments and ASPs shrank sequentially 10.6 and 14.9 percent in June, resulting in a whopping double-digit sales value decline of 23.9 percent.  The comparable numbers for the previous month were all positive at 3.3 percent, 7.8 percent and 11.4 percent respectively.

The inventory correction we cautioned was inevitable is now starting to manifest itself by way of reduced unit shipments with all sectors showing negative monthly growth vs. May.  This was in sharp reversal to May’s unit growth results, which showed all sectors still growing, other than Micro which suffered a modest 0.6 percent decline.

Reduced unit shipments will quickly translate into a sharp cutback in new orders, taking the pressure of fab capacity and eventually shorter lead times, just as the first wave of increased capacity is coming online.

In parallel, IC ASPs fell an eye-watering 14.9 percent in June vs. May, with Memory hit hardest dropping 19.0 percent.  Micro ASPs fell 8.5 percent followed by Logic at 7.2 percent and Analog at 3.7 percent.

Adding to these woes, in its July mid-year report, the IMF reported a gloomy and more uncertain global outlook, downgrading its 2022 GDP forecast from 3.6 to 3.2 percent, with the economic risks now all overwhelmingly tilted to the downside.

It is this combination of negative ASP growth, falling unit shipments, increased capacity and a weak global economy that will tip the semiconductor market into negative growth in 2023.

Market Outlook

Granted, most firms are still reporting strong second quarter results and full order books for Q3/Q4-2022, but, in the same breath, many are now starting to admit that these orders could easily vaporize.

When we published our 6.0 percent growth forecast for 2022, shrinking by 22.0 percent in 2023, in May 2022, we were still the only analyst cautioning that a downturn was imminent.  It might yet transpire even our forecast was optimistic.  Based on a forecast that the second quarter would grow 1.5 percent vs. Q1-2022, with the actual growth coming in at only 0.5 percent, our May 2022 forecast has now been pushed into bear territory.

Whilst we are not yet minded to formally downgrade our forecast, we are even more certain we called the 2022 downturn correctly when we issued our warning at the end of last year.

We will be formally revisiting the numbers for our annual mid-term Industry Forecast Update webinar on September 13 but until then suffice it to say there is now no upside to our 2022 forecast and all industry hopes of double-digit growth for 2022 have been blown out of the water.

For a full analysis, see Future Horizons’ August Semiconductor Monthly Update Report Visit www.futurehorizons.com to sign up for IFS2022-Mid-Term Webinar

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Podcast EP98: How Menta is revolutionizing embedded FPGA deployment

Podcast EP98: How Menta is revolutionizing embedded FPGA deployment
by Daniel Nenni on 08-05-2022 at 10:00 am

Dan is joined by Dr. Yoan Dupret, the Managing Director and CTO of Menta – a leader in embedded FPGA IP cores for chips and smart sensors. Yoan explores the impact Menta’s embedded FPGAs are having on current designs. The reasons for Menta’s success and where the impact will be in the future are both discussed as well.

The views, thoughts, and opinions expressed in these podcasts belong solely to the speaker, and not to the speaker’s employer, organization, committee or any other group or individual.

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How TSMC Contributed to the Death of 450mm and Upset Intel in the Process

How TSMC Contributed to the Death of 450mm and Upset Intel in the Process
by Craig Addison on 08-05-2022 at 6:00 am
Categories: Foundries, Intel Foundry, TSMC
8 Comments

450mm wafer

Pinpointing exactly when 450mm died is tricky. Intel’s pullback in 2014 has been cited as a pivotal moment because it was the main backer of the proposed transition, as it had been for the shift to 150mm (6-inch) wafers in the early 1980s.

However, the participation of global foundry leader TSMC was also seen as crucial if 450mm wafers were to become reality, as was support from Samsung Electronics and the semiconductor equipment sector, the latter having shouldered the financial burden of the 300mm transition.

Two years after Intel’s pullback in 2014, TSMC quietly wound down its participation in the Global 450 Consortium, founded at SUNY Polytechnic Institute in New York in 2011.

The reported reasons for Intel’s decision were low utilization rates and an empty fab 42 shell, but why did TSMC turn cold on 450mm?

The answer to that question – or at least one interpretation of it – can be found in a newly published oral history interview with Shang-Yi Chiang, TSMC’s vice president of R&D at the time.

Earlier this year, Chiang sat for an interview as part of the Computer History Museum’s oral history program. The transcript of the interview is now available as public record.

“It seemed a foregone conclusion that [TSMC] would go along with the next size… which was aggressively being pushed by Intel,” Chiang is quoted saying in the transcript. “Intel tried very hard to get TSMC and Samsung to join forces. Intel already started spending a couple billion dollars in preparing for 450-millimeter wafers,” he said.

After TSMC’s founder and CEO Morris Chang presented a roadmap for 450mm at an investor conference, “all of a sudden… the industry became very hot for 450mm wafers,” according to Chiang.

However, that’s when the TSMC R&D chief revealed his reservations about the commitment.

“One day in 2013, I think around March… I went to Morris Chang’s office. I said, ‘I don’t think we should promote these 450mm wafers. In the past, our competitors [were] UMC, SMIC, and those guys are much smaller than we are. [If] we promote 450mm, we take advantage of them. But right now, we only have two competitors, Intel and Samsung. Both are bigger than we are.”

Chiang argued that 450mm would tie up too many of TSMC’s R&D staff, reducing its ability to pursue technology advancements in other areas. However, Intel – with a bigger R&D budget – would be less affected. Therefore, the main reason for going to larger wafers was so “a big guy can squeeze the small guy out”, Chiang said.

Subsequently, Morris Chang called more than 10 internal meetings to discuss the matter, but he also dispatched Chiang to consult with equipment vendors, including Applied Materials, Lam Research and KLA.

In the end, the TSMC founder decided not to support the transition to 450mm. However, the problem was how to communicate that decision without sounding “negative”.

“If you just say directly that TSMC will not do that, it is a negative image because you are not looking at the future,” according to Chiang’s interview transcript. Instead, it was decided that the decision would be framed as a shift in priorities. Instead of 450mm, TSMC would focus on “advanced technology”.

Chiang also recounted how he conveyed the decision to Intel’s technology and manufacturing chief Bill Holt. It was at a private meeting at SEMICON West 2013, hosted by ASML and attended by two representatives from Samsung Electronics as well as two each from Intel and TSMC.

Holt opened the meeting by saying he believed the industry should be aggressive in moving to 450mm, and that all the players should share the costs, according to Chiang’s recollection.

Samsung’s representatives did not say anything. When Chiang’s turn came, he gave Holt the bad news, but the Intel manufacturing chief did not take it well.

“He was very upset and walked away,” according to Chiang’s recollection.

Holt, who began his Intel career in DRAM development in 1974, retired from Intel in June 2016.

Chiang, a US citizen whose most recent assignment was with TSMC’s mainland Chinese rival SMIC, retired from the industry last year and now resides in Silicon Valley.

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LRCX – Great QTR and guide but gathering China storm

LRCX – Great QTR and guide but gathering China storm
by Robert Maire on 08-04-2022 at 10:00 am
Categories: Semiconductor Advisors, Semiconductor Services
2 Comments

Lam Research Headquarters

-Lam reports record QTR and great guide amid growing anxiety
-Weakness has not yet trickled down to Lam’s order book
-Company contacted by US government on new China restrictions
-Combination of supply issues/China/economy cut WFE view

Numbers are great

Lam reported revenues of $4.64B and EPS of $8.83 which represented a very strong beat. Even more importantly , guidance for September is for $4.9B +- $300M and EPS of $9.50 +- 0.75. Deferred revenue was up slightly from $2.07B to $2.2B.

These are record levels of business…..but despite these records the company cut its year WFE spending view from $100B to $90 to $95B range….obviously this is a strange contradiction, business is great, better than ever yet the company is getting more cautious on the overall yearly outlook.

The triple threat- China embargo, Down cycle & Supply Chain

The problem is that we have three relative unknowns hanging over the industry’s and Lam’s head. The supply chain continues to be a problem even though Lam appears to have done a good job in mitigating those issues. There clearly is a down cycle happening in the memory segment as reported by several chip makers in the memory market. Lam being a memory centric provider is more susceptible than other tool makers to a memory downturn. We have not seen similar signs in foundry/logic…..yet. And last, but not least in the triple threat is China….

Lam has been contacted by the US government on China embargo

Lam management said;

“we were recently notified that there was like – there was to be a broadening of the restrictions of technology shipments to China for fabs that are operating below 14-nanometer. And so that’s the change I think that people have been thinking might be coming. And our – we’re prepared to fully comply. We’re working with the U.S. government and any impact on Lam’s business it’s contemplated in the September guidance that we just gave.”

So the impact, reductions, in Lams business, have already been calculated into September guidance and the company also said that China impact is part of their reduction of overall annual WFE spend.

Management said fabs operating below 14NM which is only SMIC and then not really in any volume. We think management misspoke, we think the impact is on tools capable of below 14NM not fabs as it would be stupid for the government to allow some fabs in China to get sub 14NM tools while others can’t.

With China representing 31% of Lam’s business, that could be a significant impact. China is by far, Lam’s biggest market with Korea second at only 25% and the US a distant fourth after Taiwan. However it sounds like the details remain fuzzy as to the full impact and the company did not clarify further.
This would obviously impact higher revenue, higher value and higher margins tools sold in China.

We are sure the company is fighting and lobbying this issue as it will have a huge impact. We view this as a much bigger threat than supply chain issues which will eventually work out and perhaps even a cyclical downturn which will eventually resolve. An embargo on China could be very long lasting as it was in the past (which few remember).

This also reflects exactly what we have been saying for a long time…that the US can’t ask ASML not to ship tools to China while US companies continue to ship….This will clearly impact Applied Materials and KLA as well and likely KLA to a greater extent given what they sell is aimed at improving yields and getting down the Moore’s Law curve faster. Do as I say not as I do…doesn’t work.

All the words & body language points to a down cycle (at least in memory)

A large part of Q&A seemed aimed at “what if” a down turn rather than “what if” continued growth….It feels like everyone knows there’s a down cycle coming, we just haven’t seen any hard evidence of it yet, in the form of cancelations or push outs and if there have been any weakness it has been covered up by the continued momentum of strong demand.

If we were only talking about a foundry/logic semiconductor industry, we don’t think the tone would be the same as most all the reported issues have been in memory. The big question is will the economic headwinds get strong enough to slow foundry/logic as well? Or could a China embargo be the catalyst of the foundry/logic slowdown that would join the coming memory slow down? Maybe its both.

It seems a bit like the Borg…..resistance is futile….the down cycle is coming

Supply chain remains an issue but least of our concerns

The company still has supply chain issues but has also clearly made progress. While it continues to weigh on the September and WFE outlook its more of a delay and minor headwind than a cyclical down turn or technology embargo.

We don’t want to make light of it as the management likely spends most of its time on supply chain issues as there is not a lot they can do directly on China or a global macro economic down turn….but it is something they can and do impact

The stocks

If you didn’t listen to the call and just went by the results and guidance, the stock should have been up strongly in the after market….but it wasn’t ….clearly the anxiety of the the triple threat of the economy (memory), China and supply chain cast a pall over what should have been a celebratory party on the great results.

The stock market hates uncertainty and we have it in spades.

We continue to think that the downside beta far outweighs the upside beta. There is too much to go wrong and we already know how great things are. There is not a lot that makes us want to go out and buy the stock. The recent bounce seems to be somewhat of a mirage that things will continue to be wonderful and we aren’t headed into a downturn.

We think perhaps the most important data point on the call wasn’t in the prepared remarks and was glossed over…perhaps on purpose….that Lam was “notified” by the US government about China…..words you never want to hear “notified by the government”.

We can only imagine that now Applied and KLA will have to answer that same question on their calls and will likely give the same answer that they too were “notified” and that it is negatively impacting their outlook

It may take investors some time to figure out that AMT and KLA will say similar things on their calls, so their stocks should be off in sympathy as even higher percentages of their business are from China.

We see this as more negative news for the group and the beginning of confirmation of some of our concerns re China as Lam was the first to talk about it.

I can’t help but think back to my grammar school Charles Dickens, reading a “Tale of Two Cities”….”it was the best of times (for revenue and earnings) it was the worst of times (for anxiety and fear of a downturn).

About Semiconductor Advisors LLC
Semiconductor Advisors is an RIA (a Registered Investment Advisor),
specializing in technology companies with particular emphasis on semiconductor and semiconductor equipment companies. We have been covering the space longer and been involved with more transactions than any other financial professional in the space. We provide research, consulting and advisory services on strategic and financial matters to both industry participants as well as investors. We offer expert, intelligent, balanced research and advice. Our opinions are very direct and honest and offer an unbiased view as compared to other sources.

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SEMICON West the Calm Before Storm? CHIPS Act Hail Mary? Old China Embargo New Again?