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A Look at the PCIe Standard – the Silent Partner of Innovation

A Look at the PCIe Standard – the Silent Partner of Innovation
by Mike Gianfagna on 07-26-2022 at 6:00 am

A Look at the PCIe Standard – the Silent Partner of Innovation

Let’s face it. Standards aren’t always exciting, and the process of ratifying new versions can be time-consuming and tedious. Regardless, we all know standards are the glue that bind many ecosystems and without them the technology world would be good measure more chaotic. Standards come in many versions, with various amounts of reach and impact. In this post I will explore the Peripheral Component Interconnect Express standard, or PCIe for short. This standard has far-reaching consequences, it is truly the silent partner of innovation in our world.

What is It, Why Does It Matter?

PCIe is a high-speed serial computer expansion bus standard. Its mission is to deliver high bandwidth, low latency, and low power communication between components in a computer system. Devices that use this standard include graphics cards and GPUs, all forms of storage including SSDs, network interfaces, WiFi and Bluetooth interfaces. Essentially, many of the technologies that fuel next-generation innovation.

The PCI Special Interest Group has done a remarkable job at keeping the standard evolving and vibrant. The group has delivered a doubling of PCI Express speeds around every three years ever since the introduction of the spec in 2003.  The latest version, PCIe 6.0, overhauls the signaling technology to achieve bandwidth gains while maintaining low latency. The new architecture also maintains compatibility with all previous generations of PCIe. This is not easy to do but will certainly help with adoption for existing designs.

Each generation of the standard also supports multiple data lanes, from 1 to 16. This allows the standard to be used in all kinds of applications, from hand-held devices to server-class computing. Data Center, Artificial Intelligence/Machine Learning, HPC, Automotive, IoT, and Military/Aerospace are all markets that have benefitted from the PCIe standard.

And How Does It Impact the World Around Us?

Standards are nice; a working implementation of the standard is what drives innovation, however. When it comes to implementing high-performance channels, my go-to organization is Samtec. They are always at the forefront of high-speed channels. Their products are essentially the cohesive force for any new idea. Without the ability to move data, any idea is interesting but not practical. You can learn more about Samtec’s products and people on SemiWiki here.

As I dug into the latest information on its website, I found what I was looking for; real hardware solving real problems. The first item I found was a demo that uses the PCIe 6.0 standard. This is real cutting-edge stuff as the standard was just released earlier this year.  It normally takes quite a while to see real implementations of a new standard and this demo was done right around the time of the standard’s release. 

The demo showcases a PCIe Gen 6.0 AI hardware design based on the GenZ PCIe enclosure compatible form factor (PECFF). Working with Synopsys, a GENZ motherboard is combined with GENZ Add-In-Cards with top card connectivity. This design emulates industry standard AI acceleration hardware platforms.  The Synopsys PCIe 6.0 PHY generates up to four 64 GT/s PAM4 differential signals in the demo. You can see a short, very informative video of this demo here.

I also found a Samtec demonstration based on PCIe Gen 4.0. This demo highlighs Samtec’s PCIe®-Over-Fiber FireFly™ Adapter Card (PCOA Series), developed by its partner, Dolphin.  The PCOA series utilizes Samtec’s PCI Express®-Over-Fiber FireFly™ Optical Cable Assemblies (PCUO series). It turns out Samtec is the only company in the world offering reset functionality and cable present sidebands in this form factor.

One of the new features of the adapter card is the capability to do a surprise hot add. A surprise hot add feature allows a new resource to be added to a system that is already running. The resource can be a storage device, camera, a GPU or an FPGA. This allows a new resource to be added and be available without shutting down the server. Without the surprise hot add, the host needs to be rebooted to enumerate and find the PCIe devices attached to the server, a much more cumbersome process. You can also see a short and informative video of this demo here.

The Momentum Keeps Building

There is significant momentum building for PCIe deployments. The PCI-SIG Developers Conference series for 2022 just kicked off in Santa Clara this past June. In case you missed it, there are more events happening around the world in later this year in Asia, Israel and Europe. You can learn more about Samtec’s support for PCIe here and download an overview of its various solutions here. PCIe is definitely creating big opportunities. It is truly the silent partner of innovation in our world.

Also read:

A MasterClass in Signal Path Design with Samtec’s Scott McMorrow

Passion for Innovation – an Interview with Samtec’s Keith Guetig

Webinar: The Backstory of PCIe 6.0 for HPC, From IP to Interconnect

 


Calibre, Google and AMD Talk about Surge Compute at #59DAC

Calibre, Google and AMD Talk about Surge Compute at #59DAC
by Daniel Payne on 07-25-2022 at 10:00 am

Google Cloud vendor of the year min

In 2022 using the cloud for EDA tasks is a popular topic, and at DAC this year I could see a bigger presence from the cloud hardware vendors in the exhibit area, along with a growing stampede of EDA companies. Tuesday at DAC there was a luncheon with experts from Siemens EDA, Google and AMD talking about surge compute. I already knew Michael White of Siemens EDA who was moderator, while Peeyush Tugnawat of Google, and Philip Steinke of AMD were new faces to me. There was an award presented from Google Cloud for Industry Solutions Partner of the Year 2020,  and Michael Buehler-Garcia graciously received it for Siemens EDA.

Michael Buehler-Garcia, VP at Siemens EDA

Cloud for Surge Compute, Why Now?

The relentless pursuit of Moore’s Law brings us ever-small nodes, which then dramatically increase the computation requirements for EDA tools, like: physical verification, circuit simulation, DFM, DFT, functional verification, and more. The CPU cycles with most on-premise design teams isn’t enough to meet timelines, so that’s when cloud capacity comes to the rescue.

Technology Challenges

Google’s View

Peeyush opened by sharing that Google has some $257B in revenue, from 9 services, attracting 1B+ active users, and that their Cloud Business revenue is $20B, so yes, cloud is a priority. Silicon design has huge CPU needs across compute, storage and network. He showed a cool diagram of the chip design process, and denoted which segments were compute intensive or data intensive.

IC Design Tasks

Google Cloud offers three VMs for general purpose, and three VMs for workload-optimized, so there’s a lot of flexibility for EDA users to choose the best VM for the task at hand. Scaling happens by deploying up to 1,000 instances with a single call. Google Cloud also partners with the most popular file systems: NetApp, Dell Powerscale, DDN EXAScaler, IBM Spectrum Scale, Intel DAOS. The internal Google Cloud network is global, and secure, built without public hubs to increase security.

AMD’s View

Google Cloud has VMs that are powered by AMD EPYC processors, that enable complex EDA workloads to run faster. Phil mentioned that having Google Cloud as a partner has enabled their HW teams to tackle the biggest processor designs while meeting aggressive TTM goals. The specific instances with AMD EPYC processors were N2D, C2D and T2D. The SoC design example was the AMD Raden MI50 GPU, having an impressive 13.2B transistors, a high-performance compute engine, scalable interconnect, end-to-end ECC enablement, fabricated at TSMC on the N7 node.

AMD MI50 GPU

Siemen’s EDA View

Michael White presented how Calibre PERC was run on a large design in Google Cloud with AMD servers, comparing the performance of N2D and C2D, where 16 to 816 CPUs were used. With just 16 CPUs the run time was about 5 days on the 2nd generation N2D, while using 816 CPUs the run time shrunk to just 8 hours on the 3rd generation C2D. Using more CPUs enables a design team to get 2 iterations per day, so that’s a big time savings using surge compute.

Caliber PERC Run Times

The memory footprint for Calibre PERC was smaller than competitors tools, and pretty much flat with more cores added, making the approach quite efficient. Even full-chip P2P checks on the I/O ring could now be run overnight using surge compute on the MI50 GPU design. Data was shared on how Calibre nmDRC was run on the MI50 GPU design with up to 1,500 CPUs, enabling 6 iterations per day.

Calibre nmDRC run times

Summary

Yes, Moore’s Law is still alive, and these leading-edge process nodes are dramatically increasing CPU requirements for EDA tools, calling in to question the sole reliance of on-premise computing. Using the power of the cloud really is meeting the compute challenges, and the collaboration between AMD, Google Cloud and Siemens EDA has worked out quite well. EDA jobs that used to take multiple days, can now be iterated several times per day by using the cloud.

There is some circular reinforcement going on here, because AMD designers are using AMD hardware to design the next generation of AMD hardware, thanks to the infrastructure of Google Cloud combined with the software from EDA vendors like Siemens EDA.

Related Blogs


Intel Lands Top TSMC Customer

Intel Lands Top TSMC Customer
by Daniel Nenni on 07-25-2022 at 2:30 am

Intel Foundry and MediaTek

Most people will be surprised by this but after working in Taiwan for many years I quite expected it. Intel Announced that MediaTek will use Intel Foundry Services for FinFET based smart edge device chips. MediaTek will start with Intel 16nm technology which originated from the legendary 22nm, the first commercial FinFET process. It’s equivalent to TSMC 16nm. Once Intel 14nm capacity frees up I would expect it will become available to foundry customers as well. The current version of Intel 14nm is equivalent to TSMC 10nm. Intel 10nm is now called Intel 7 which competes with TSMC N7. It is nice that that foundry process names are finally syncing up, much less confusing for the mass media.

In the early days of the fabless transformation having multiple foundry sources was key to getting capacity and competitive wafer pricing. One time I worked on a chip that was taped-out at TSMC then moved to UMC, SMIC, and Chartered for high volume manufacturing. Qualcomm and MediaTek were both experts at multi sourcing chips up until the FinFET era. Qualcomm moved a lot of capacity to Samsung with mixed results. MediaTek, on the other hand, partnered closely with TSMC and gained serious SOC market share over Qualcomm. In fact, the last numbers I saw had MediaTek beating Qualcomm at their own game in the smartphone market.

Having worked with both Qualcomm and MediaTek during my 40 year semiconductor career I can tell you these are two very different companies. The advantage MediaTek has is they are exceptionally good at pivoting. MediaTek is also great at customer collaboration, especially in China, which explains their lead in the smartphone market.

“As one of the world’s leading fabless chip designers powering more than 2 billion devices a year, MediaTek is a terrific partner for IFS as we enter our next phase of growth,” said IFS President Randhir Thakur. “We have the right combination of advanced process technology and geographically diverse capacity to help MediaTek deliver the next billion connected devices across a range of applications.”

NS Tsai, corporate senior vice president of Platform Technology & Manufacturing Operations at MediaTek, said, “MediaTek has long adopted a multi-sourcing strategy. We have an existing 5G data card business partnership with Intel, and now extend our relationship to manufacturing smart edge devices through Intel Foundry Services. With its commitment to major capacity expansions, IFS provides value to MediaTek as we seek to create a more diversified supply chain. We look forward to building a long-term partnership to serve the fast-growing demand for our products from customers across the globe.”

I would consider this great customer win to be part of the “Not TSMC” market which Samsung has been living off for the past few years. Moving forward the Not TSMC market will continue to grow for Intel Foundry with the stumbling of Samsung and the tight capacity and higher wafer pricing at TSMC. In order for the chip business to thrive there must be multiple manufacturing sources at the leading edge. No one knows this better than Qualcomm and MediaTek so I quite expect Qualcomm to be another big customer to collaborate with Intel Foundry, absolutely. We can make a list of other potential IFS customers in the comments section, absolutely.

Intel and MediaTek Form Foundry Partnership

About IFS

IFS was established in 2021 to help meet the surging global demand for advanced semiconductor manufacturing capacity. IFS is differentiated from other foundry offerings with a combination of leading-edge process and packaging technology, a world-class IP portfolio, and committed capacity in the United States and Europe. IFS customers will reap the benefits of Intel’s recently announced factory expansions at existing sites, as well as plans for major new investments in greenfield sites in Ohio and Germany.

Also read:

3D Device Technology Development

Intel Foundry Services Puts PDKs in the Cloud

Intel 4 Deep Dive


ASML Business is so Great it Looks Bad

ASML Business is so Great it Looks Bad
by Robert Maire on 07-24-2022 at 6:00 am

ASML Systems 2022

-ASML reports strong quarter- Orders up 20% Qtr/Qtr
-Customers rush delivery which delays revenue recognition
-Chip makers need hard to get litho tools most of all
-Warning on concerns about consumer chip demand

Good numbers that are even better in reality

ASML reported revenues of Euro5.4B and EPS of Euro3.54. Most importantly orders came in at Euro8.5B versus street expectations of about Euro7B and jumped over 20% quarter over quarter. The company shipped 14 EUV tools.

Rush to get equipment masks outperformance

As we had previously heard from ASML, the company is doing rush deliveries of incomplete tools, due to supply chain constraints, which are then finished at customer sites. Customers are obviously very desperate to get their hands on tools and don’t want to step out of the order queue lest they get back on the end of a 2 year (or longer) line.

The financial issue is that ASML can’t take full revenue recognition as the tools that are rush shipped are incomplete. This obviously masks what would have otherwise been strong performance. The slight benefit is that the delayed revenue does come back in later quarters at 100% gross margin.

The percentage of rush tools and therefore partial revenue is likely to increase going forward which will depress revenues in near term. ASML predicts that the delay impact will grow from about Euro1B to about Euro2.8B and push into 2023. We don’t see this situation changing any time soon as supply chain issues appear to be longer term in nature.

ASML will be last to see chip weakness

We have heard warnings from Micron and LG about a semiconductor down cycle coming in memory. Perhaps a down cycle will be focused on memory and other consumer specific semiconductor devices. In any event, ASML will be the last semiconductor equipment company to see any impact.

Process tools , such as etch and deposition tend to be more of a turns business which can usually ship relatively quickly even though lead times are currently stretched, they are not near as long as litho tools.

Additionally, there are multiple suppliers of etch and deposition tools so there is competition which tends to keep supply times shorter or allows for alternatives if delays grow too long. ASML remains a monopoly in EUV with no alternatives. The bottleneck in critical lens supply remains in Zeiss which limits increasing supply.

Supply chain remains problematic

Company management is guiding for further issues in the supply chain that appear to be worsening which will limit revenue growth to roughly 10% in 2022.

The company expects to ship 55 EUV systems in 2022 but only 40 of which will be revenue recognized in 2022 with 15 systems slipping into 2023 for revenue recognition purposes.

Increases in costs in the supply chain also impacts cost of sales which obviously impacts gross margin but ASML will likely either share or pass increase costs onto customers.

Keeping an eye on Zeiss and Germany

Although its not a problem now, in the summertime, we are keeping an eye on Russian gas supply to Germany. If gas gets cut off in the coming winter businesses will get curtailed first and consumers last. We would hope that Zeiss is making plans for the highly sensitive lens systems in long term production in Germany that may be exposed to such a shut down.

ASML likely to ride through a chip cycle downturn due to backlog

Given the existing strong and long backlog in ASML’s order book, we think there is less than zero risk to 2022 and likely close to zero risk in 2023.
We don’t expect any cyclical downturn to last more than a year or so. The last time that Samsung put the brakes on capex it was for a relatively short few quarters.

We think it would take a very significant macro economic downturn to lengthen a semiconductor down cycle given the breadth of demand we are seeing.

China

We also see little impact on ASML from any potential embargo on China as there are many other customers outside of China who would gladly take their place in line and take their tools. As we have said multiple times, in the long run, semiconductors are a long term zero sum game. If anything, taking China out of the equation could keep supply short and limit down cycles and keep pricing for chips higher. In summary we don’t see much of a risk out of the China situation other than rearranging the shipping destination of tools.

The stocks

Obviously this is a very positive report for ASML. Business is as strong as ever if not stronger than before. Customers remain desperate to get ASML tools. Financials remain solid and technology moves on. So we see nothing but positive for the stock of ASML.

This could be the point where short sellers who have seen ASML’s stock price get cut in half should likely abandon ship and close out their short positions. One investor famously said they had a $1B short position in ASML. If we get a bit of a short squeeze we could see a bottom and a bounce of ASML’s stock price, and a turn in the otherwise down trajectory.

While there may be some sympathetic positive reaction from other semiconductor equipment stocks, we think the negative talk of consumer chip concerns are more of a risk to the process tool makers such as Applied Materials and Lam. KLAC is impacted to a lesser extent as their tools have longer lead times, though not as bad as ASML, and they have a strong market position in most, but not all, markets and that keeps their backlog stronger.

We will wait and see what others have to say but clearly there is weakness showing in the chips market but we don’t have a clear picture as yet as to how deep and wide that weakness is. Will the down cycle be limited to memory or memory and consumer facing logic or across the entire breadth of the chip industry? We just don’t know as much of the depth and breath of a down cycle depends on the less predictable macro economic and geo political issues which are still evolving.

About Semiconductor Advisors LLC
Semiconductor Advisors is an RIA (a Registered Investment Advisor), specializing in technology companies with particular emphasis on semiconductor and semiconductor equipment companies. We have been covering the space longer and been involved with more transactions than any other financial professional in the space. We provide research, consulting and advisory services on strategic and financial matters to both industry participants as well as investors. We offer expert, intelligent, balanced research and advice. Our opinions are very direct and honest and offer an unbiased view as compared to other sources.

Also read:

Micron kicks off the down cycle – Chops 2023 capex – Holding inventory off street

ASML- US Seeks to Halt DUV China Sales

SEMICON West the Calm Before Storm? CHIPS Act Hail Mary? Old China Embargo New Again?


Podcast EP95: An Overview of Axiado’s Transformative Security Technologies

Podcast EP95: An Overview of Axiado’s Transformative Security Technologies
by Daniel Nenni on 07-22-2022 at 10:00 am

Dan is joined by Gopi Sirineni, the President & CEO of Axiado, a company that is spearheading unique security technologies with AI in hardware. He is a Silicon Valley veteran with over 25 years of successes in the semiconductor, software and systems industries.

Gopi explains what’s different about the Axiado approach to security and its impact in real world situations.

The views, thoughts, and opinions expressed in these podcasts belong solely to the speaker, and not to the speaker’s employer, organization, committee or any other group or individual.


CEO Interview: Jaushin Lee of Zentera Systems, Inc.

CEO Interview: Jaushin Lee of Zentera Systems, Inc.
by Daniel Nenni on 07-22-2022 at 6:00 am

Jaushin Lee large

Dr. Jaushin Lee is the founder and CEO of Zentera Systems. He is the visionary architect behind the award-winning Zentera CoIP (Cloud over IP) platform that enables enterprises to dramatically accelerate their journey to Zero Trust security. Jaushin brings 20 years of management and executive experience in networking and computer engineering.

Before Zentera, he was the founder and CEO of Imera Systems, which provided enterprise secure collaboration solutions. He built Imera from the ground up, raised three rounds of funding, and successfully acquired a number of Global 2000 enterprise customers with a multi-million dollar run rate. Earlier, he managed Cisco’s network search engine program, supporting numerous critical product lines, such as the CRS-1 router, Catalyst 4K, and Catalyst 6K, among others.

Jaushin has held management positions with Terawave Communications and Silicon Graphics, as well as an assistant professorship with the EE Department at the University of Virginia. Jaushin earned a PhD from the University of Illinois at Urbana-Champaign, an MS from Columbia University, and a BS from National Taiwan University, all in EE. He has published numerous international conference and journal papers, has been granted a number of U.S. patents, and was recognized as the 2017 CIE Entrepreneur of the Year.

What’s Zentera’s backstory?
I have been involved in many secure collaboration projects during my time at Silicon Graphics, Cisco, and Imera. Many of these projects involved design and technology challenges that required teams from different companies and ecosystems to work together in one environment for optimal productivity.  Each project had unique requirements, we always had to wait for the IT and security teams to provide a customized network environment for each project, which could take months, and sometimes never materialized. I saw some companies create permanent physical chambers for collaboration, but this was only marginally better – developers still had to move their design tools and data into and out of those chambers, which was painful and impacted productivity.  No one seemed to have a solution that was a win-win for everyone!

When I founded Zentera, I set out to fix this problem. We built a virtual chamber that drops around enterprise applications and data to protect them, and incorporated secure access solutions that connect users to their authorized chambers and applications with tight security controls. Everything was software-defined so it could be implemented in minutes, rather than months, and provide a seamless experience for developer collaboration that exceeds corporate security requirements.

Since those early days, we’ve filled out the product offering and refined the security features through deep engagements with EDA powerhouses like Siemens and Cadence, fabless vendors like Ambarella, and manufacturing giants like Delta Electronics. We have built the industry’s most powerful and battle-tested solution for securing sensitive intellectual property.

Recently, the security industry has adopted a lot of the principles we pioneered as part of the Zero Trust security paradigm, and we are seeing application for a wider range of enterprise challenges.  But even today, our CoIP Platform technology is unique in its completeness, especially for protecting enterprise critical intellectual property and applications.

What market segments are you targeting?
Almost all high-tech companies have developed core IP and technology that needs to be protected.  Often, our customers know exactly what they want to protect, but have complex business constraints that often necessitate unpleasant tradeoffs.

You see examples of critical IP throughout the semiconductor value chain: chip design files, verification plans and test vectors, driver source code, or even yield analysis data sets and equipment parameter settings. The complexity of advanced technology designs means that companies can’t do everything in-house; they need a combination of employees, external contractors, and third-party IP or technology vendors to ship on time and on budget. Effectively, this means that third parties in the ecosystem supply chain collaborate on and get access to the crown jewel intellectual property – yet the large corporate network and the fluid nature of projects means most companies don’t have strong controls over who gets access to what.  We solve this problem by helping companies seamlessly contain and control access to intellectual property, regardless of where it’s stored in the company network.

We also work with companies in other market segments outside of high-tech/semiconductors, such as manufacturing, health care, and financial services. While they are each unique, they share a lot of related pain points.

What keeps your customers up at night?
For public companies, cyber security is a common risk item in SEC filings, and not having a good answer for the board if asked whether the corporate IP is secure from cyber attack is a major concern.  Many of our customers have experience with data leak prevention (DLP) solutions, but most of these solutions are “after the fact.”  They may be able to detect data leaving the company, but at that point it’s too late – the data is already gone.  Our customers tell us they selected us because they wanted to block attacks and leaks, not just get a notification or watermark data.

Stealing tech is one level – it’s pervasive enough that the heads of the FBI and MI5 issued a joint statement warning businesses about this.  A next-level fear is that sensitive information, in the wrong hands, could guide a malicious actor to identify attacks to use on devices in the field.  Once shipped, hardware vulnerabilities are nearly impossible to update.

What makes your products unique?
The fundamental challenge for securing intellectual property with traditional network security method is that it relies on discrete boxes in the network.  It’s high touch, very difficult, and expensive to change. CoIP Platform technology is software-defined and doesn’t touch the existing network. It deploys non-disruptively as an overlay to secure IP, whether it’s in a lab, in a datacenter or in the cloud. Whether a customer needs to secure access to data at rest in existing filers, while it’s being processed in the LSF cluster, or as it’s being edited by external contractors, we have solutions to prevent its loss or theft that don’t require IT teams to blow up the engineering datacenter.

What’s next for the company?
The global supply chain concerns of the last few years have highlighted the critical nature of semiconductor manufacturing and its outsized impact on the global economy.  This makes semiconductor manufacturing a target for ransomware groups; and we have already seen some manufacturers being targeted.

Our solutions are powerful not only for protecting EDA tool, semiconductor, and board design, but also for protecting manufacturing and industrial operations, which may include fully-depreciated production lines running outdated operating systems such as Windows XP and Server 2003.  Today our solutions apply to protect smart manufacturing and intelligent industry environments, and we are continuously investing heavily to bring new features to market to make it even easier to adopt Zentera for ransomware protection.

How do customers engage with you? 
Customers who are interested in learning more about how to protect sensitive intellectual property against leaks, theft, and ransomware can contact us through our website (www.zentera.net), or through email (sales@zentera.net) to find a local distributor/reseller.

Also Read:

CEO Interview: Barry Paterson of Agile Analog

CEO Interview: Vaysh Kewada of Salience Labs

CEO Interview: Chuck Gershman of Owl AI


The Silent Revolution is Underway, and Semifore is at its Epicenter

The Silent Revolution is Underway, and Semifore is at its Epicenter
by Mike Gianfagna on 07-21-2022 at 10:00 am

The Silent Revolution is Underway and Semifore is at its Epicenter

There is a major shift in innovation occurring all around us. We see the results every day.  We can interact with them in an easier, more intuitive way. They deliver insights about our health and our daily habits. All this can be categorized as a move towards Smart Everything – ubiquitous machine-assisted intelligence for the good of the planet and its inhabitants. While all this is true, there are some fundamental problems to be solved to get us there. That topic is the focus of this post. Read on to understand how the silent revolution is underway, and Semifore is at its epicenter.

Who is Semifore?

Answering this question requires us to step back a bit in the system engineering process. Today, a “system” is a blend of advanced software algorithms and hardware that implement those algorithms. It is quite clear that software now defines the user experience and those who can deliver the best version of that user experience will win. If you’re looking for an example of how this works, do some research on Apple’s acquisition of PA Semi. This was a key part of a seminal strategy where Apple decided iOS was its lead differentiator, and building a custom processor that would deliver that best experience was the way forward. The company acquired PA Semi, explained the new rules (the software defined the hardware architecture, not the other way) and history was made.

A short time after that decision, Apple surpassed Exxon Mobile as the most valuable company in the world. Today, its lead is unchallenged. So, what is the key technology that drove all this?

There are many. One that stands out is the critical interface between the dedicated hardware that implements the user experience and the software that controls that hardware. This hardware/software interface (HSI) is key to success of any Smart Everything project. The details of how to implement this interface are daunting. The complexity of what’s involved should give every design team pause. How can you get all this right, and not introduce subtle errors that could put future products out of reach?

This is a very real problem. If the HSI contains bugs that are released to the field, those bugs could manifest when a software upgrade is released. Or a new feature, one that is needed for competitive reasons, simply won’t work. The stakes are high. Getting the HSI right is a primary focus of Semifore.

What Semifore Does

When systems were simpler and custom-built processors were rare, the HSI was still complex and important, but easy to keep track of.  Design teams would build spreadsheets to document the control/status registers (CSRs) involved in the process. The values contained in these registers were linked to specific aspects of the hardware’s performance. Once the protocol was specified, it became a matter of tracking the implementation so everyone followed that protocol.

Today, custom-built processors are everywhere, and the complexity of the HSI has exploded. Designs can contain half a million or more CSRs with over a million fields defining various parts of the communication protocol between software stacks and the hardware being controlled. Many of those home-grown spreadsheets have attempted to keep up, but the problem has become too large for do-it-yourself solutions.

The industry has responded to these developments with standards to help define how everything works in a robust and consistent way. While quite useful, each of these standards has its shortcomings. A true, robust executable specification for the HSI is still out of reach in the public standards realm.

Semifore addresses these challenges head-on. Its CSRSpec™ language delivers a robust description of the HSI. Its CSRCompiler™ reads this language, along with the industry standards and creates a correct-by-construction HSI, along with all the formats needed for things like validation, test and documentation. The whole team is in sync with a known-good HSI. This leaves a lot more time to create The Next Big Thing vs. worrying about if it will work.

You can learn more about Semifore on SemiWiki here.

A Customer’s View

Semifore recently published a white paper that details how a large system OEM addressed the challenges of building a robust HSI. The paper goes into detail on the challenges faced, the methodology employed, and the results achieved. I found the piece to be direct, informative, and grounded in reality. If you are struggling with HSI problems, I highly recommend taking a look. You can download a copy of the white paper here.

You will learn that the silent revolution is underway, and Semifore is at its epicenter.

Also read:

Webinar: Semifore Offers Three Perspectives on System Design Challenges

Register Management is the Foundation of Every Chip

CEO Interview: Rich Weber of Semifore, Inc.


EasyVision: A turnkey vision solution with AI built-in

EasyVision: A turnkey vision solution with AI built-in
by Don Dingee on 07-21-2022 at 6:00 am

People counting with EasyVision, a turnkey vision solution from Flex Logix

Artificial intelligence (AI) is reserved for companies with hordes of data scientists, right? There’s plenty of big problems where heavy-duty AI fits. There’s also a space of smaller, well-explored problems where lighter AI can deliver rapid results. Flex Logix is taking that idea a step further, packaging their InferX X1 edge inference accelerator chip in a turnkey vision solution. The best part: it’s pre-trained for specific use cases, so users don’t need any AI expertise to get running.

Lined up for common object detection use cases

We’re not talking about self-driving rocket science. Vision technology is now robust enough to detect sizable objects, like cars through a checkpoint, or people in a room or walkway. Detection accuracy for low-velocity targets in controlled lighting conditions is very high. Scalability is also easy; one or several cameras can interface over Ethernet, USB, or fast Wi-Fi and be brought to one system for processing.

Still, teams who don’t work with AI everyday struggle with implementation. They must find hardware and software, figure out the right AI model for detecting objects, and find or create an AI training data set. Then, they need to put all that together and verify their application works. It can be a very long path to successfully train an application, even for those with AI experience.

What if the training part were already done in a turnkey vision solution? By hand-picking use cases and creating inference software, the EasyVision solution comes ready for a live image feed. Some applications Flex Logix is working on, with a goal of adding two new ones per month:

  • Workplace safety – checking people entering a facility for visible gear such as hardhats can be automated.
  • People counting – retailers, schools, and event centers can count how many people enter a building, occupy a specific room, or pass through an area.
  • Health monitoring – face mask compliance checks are easy with vision detection.
  • Vehicle access – how many cars, how many open spaces, and how long each car has been inside a parking facility are also easy detection tasks.

YOLO-based recognition at up to 60fps in less than 10W

Running AI inference efficiently is also a big piece of the equation. Quite a few convolutional neural network (CNN) algorithms can do object detection. YOLO (in this case, You Only Look Once) is a one-stage detector algorithm which finds regions and classifies objects in one pass. The result is excellent real-time object detection performance. YOLO continues evolving, with recent versions improving frame rate without compromising accuracy.

YOLO also maps cleanly to the InferX X1 chip, designed for efficient low-power AI inference – not video gaming. Its tensor processor units, or TPUs, are tiled and reconfigurable dynamically for many CNN models. In an AI development workflow, a customer would use the InferX DK tool chain to compile their preferred trained model into the InferX X1. In the EasyVision solution, Flex Logix has already done that work for the YOLO algorithm and object training data sets.

The EasyVision solution runs object detection at up to 60fps HD images from multiple cameras in real-time, using less than 10W of power. The InferX X1 chip is comes on either a PCIe or M.2 card, allowing installation in many hosts – including Dell and HPE platforms. Users get software to install pre-trained object detection models of choice. There’s also a software API for integrating detection results into a high-level application.

As the portfolio of EasyVision-trained applications expands, more users will see the power of a turnkey vision solution. EasyVision gets a vision-enabled object detection application off the ground with no AI learning curve. Teams looking to launch a broader AI initiative may want to start with an EasyVision package to pilot a concept. Then, they can step up to creating models and configuring the InferX X1 chip, leveraging its low-cost, efficient AI inference.

For more info, please visit the Flex Logix EasyVision webpage.


DSPs in Radar Imaging. The Other Compute Platform

DSPs in Radar Imaging. The Other Compute Platform
by Bernard Murphy on 07-20-2022 at 6:00 am

Radar Trends

In the flood of CPU and GPU announcements in pursuit of new technology advances, it is easy to lose track of another kind of platform – DSPs. Digital signal processors, once a niche platform for specialized applications, are now front and center in some of the hottest technologies. Because their strength in signal processing has become key to making those technologies work. Radar imaging is one good example.

4D imaging

In automotive applications we all know about visual imaging and object detection. Cool stuff but it suffers from a couple of important drawbacks. First, it only works well in good seeing conditions, not so well at night or in bad weather. Second, it is primarily 2-dimensional and has no sense of relative velocity or even of distance. It detects an object but is that object near or far away? Is it stationary or moving towards you rapidly?

LIDAR gets a lot of press as a complementary 4D detection method (3 spatial dimensions plus velocity). This can work in bad weather and does provide relative velocity. Radar, also able to sense velocity, was still seen as a useful but coarse technique. Good enough for “something is approaching rapidly from the front or the back of the car, but that was about it.

Radar steps up to imaging

But then radar designers got ambitious with their own 4D option, now able to sense distance and direction in a 2D plane, relative velocity and also vertical information (will I fit under that overpass?) The design starts with an array of up to 200 antennae which can transmit and receive radar signals.  These are still wide beams, now combined through a technique known as beamforming to separate distinct reflections with high accuracy (<1o). This is the same MIMO technique used in 5G.

After noise filtering and corrections, this data is aggregated into a 4D point cloud, similar to the LIDAR approach and object detection, sensor fusion and other operations can run on that data. Following the trend to smart sensing, radar imaging now does most of this analysis at the sensor to avoid latencies and communication overhead in the car network. This sensing is central to safety, so the computation must be fast yet it also must be economical on power.

DSPs – the right solution to radar imaging

Start with beamforming. This is an ultimate signal processing application – teasing a fine resolution signal out of multiple broad resolution reflections. It requires floating or fixed-point analysis because you’re dealing with analog signals after all. Complex signals, if the radar uses complex modulation. And massive parallelism, processing input from ~200 antennae. This task is far beyond the capabilities of CPUs and GPUs but plays directly to the strengths of DSPs.

Other platforms can handle building the point cloud and inferencing . But if you’re already in a DSP that can also handle these functions very well, why switch? Adding more components increases the bill of materials and cost, increases latencies and power and challenges reliability. DSPs are already widely used in machine learning applications with well-established interfaces to all the common ML networks.

Which suggests that platforms like the Tensilica ConnX 110 and 120 IP need a closer look. These compact low-energy platforms improve upon the already popular BBE32EP and BBE16EP platforms, adding to a proven product line for radar, lidar and communications. With a track record in radar imaging with companies like NXP and with differentiated strengths in processing complex data, Tensilica looks like a strong contender in this space.

You can learn more about the ConnX product family HERE, HERE and HERE.


OpenFive Joins Universal Chiplet Interconnect Express (UCIe) Consortium

OpenFive Joins Universal Chiplet Interconnect Express (UCIe) Consortium
by Kalar Rajendiran on 07-19-2022 at 10:00 am

Snapshot of Contributing Members of UCIe

Universal Chiplet Interconnect Express (UCIe) is an open specification that defines the interconnect between chiplets within a package. The objective is to enable an open chiplet ecosystem. Although the initial specification for UCIe was developed by Intel, a consortium was announced in March with Intel, AMD, Arm, Google, Meta, Microsoft, ASE Group, Qualcomm, Samsung and TSMC as its promoting members. The promoting members represent a diverse functional cross section of semiconductor ecosystem expertise. Just in the three months since the consortium’s formation, many companies have joined as contributing level members (see Figure below).

That is a lot of committed members keen on progressing this universal interface standard. Each of these members brings its unique expertise to the consortium and of course expect their involvement to further their own business goals as well as the industry’s progress. OpenFive announced their membership recently and this post will look at what that means for them as well as for the consortium and the industry. The post will review OpenFive’s history and track record, its UCIe membership, and its pending acquisition by Alphawave. In essence, its Past, Present and Future.

Past

The OpenFive team has been delivering custom silicon for over 15 years. The key to increased productivity is leveraging pre-verified IP subsystems and OpenFive has built many such IP subsystems to support its customer base. These IP subsystems address connectivity and memory interfaces. You can learn more at their IP portfolio page.

As chiplets-based development started picking momentum a few years ago, OpenFive started playing an instrumental role to support this movement. OpenFive developed a die-to-die (D2D) IP subsystem. The subsystem supports low-power, high-throughput, and low-latency links enabling quicker integration for heterogenous chipset connections in wired communications, AI and HPC applications. It introduced the industry’s first Die-to-Die (D2D) Controllers which are agnostic to physical link interfaces, thereby supporting OHBI and BoW interfaces for chiplets. You can learn more from a SemiWiki post published last year.

Present

The current industry trend for scalable silicon architectures makes efficient and standardized Die-to-Die and Chip-to-Chip interconnects critical for SoC solutions. This has created a need for strong experience in advanced packaging, test, and production in leading-edge process nodes such as 5nm as well as older nodes. OpenFive is staying ahead by investing in die-to-die (D2D) interfaces, chiplet technology and 2.5D packaging. They can support chiplets that enable partitioning of the design into different functions, and the option to choose a process optimized for that particular function.

With their capabilities to engage in a spec-handoff, netlist handoff or production handoff, OpenFive can service their customers, whether a chiplet interface standard exists or not. But a standard such as the UCIe interface certainly makes it easier, faster and consistent and is expected to accelerate the growth of chiplet based products market.

The addition of support for UCIe support is a natural progression to their existing support for OHBI and BoW interfaces. As a contributing level member of the UCIe consortium, OpenFive will actively participate in the Electrical and Protocol subgroups. They get to drive the specification and influence the direction of the technology. And, of course access the intermediate (dot level) specifications. OpenFive will leverage its depth of experience from multiple customer engagements and its silicon platforms.

Future

In March of 2022, Alphawave IP Group announced a definitive agreement to acquire OpenFive. The transaction is expected to close in the second half of 2022. As per that press announcement, the acquisition will enhance Alphawave’s chiplet design capabilities. The combined company will offer an expanded die-to-die connectivity portfolio that will accelerate chiplet delivery capabilities to customers. The acquisition will nearly double the number of connectivity-focused IPs available to customers. Post-acquisition, the company will become a one-stop-shop for customers bundled connectivity needs in the most advanced technologies at 5nm, 4nm, 3nm and beyond.

Customers looking to implement their chiplet-based SoCs for Cloud/Datacenter, AI/HPC, and Networking applications can expect to benefit by leveraging OpenFive’s leading-edge custom silicon implementation and advanced 2.5D packaging capabilities together with their highly optimized memory and connectivity IP subsystems.

Also read:

IP Subsystems and Chiplets for Edge and AI Accelerators

A 2021 Summary of OpenFive

Enhancing RISC-V Vector Extensions to Accelerate Performance on ML Workloads