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Cadence Execs Look to the Future

Cadence Execs Look to the Future
by Dave Bursky on 07-01-2022 at 6:00 am
Categories: Cadence, EDA, Events

CDNLive 2020

Everything is becoming digital, and everything digital requires semiconductors. Cadence’s President and CEO, Dr. Anirudh Devgan, highlighted this at the recent CadenceLIVE user conference and discussed many of the company’s accomplishments and future directions. Dr. Devgan also sees the emergence of data—especially unstructured data as another major trend. Such data also affects compute, the cloud, and the edge and is transformational in many ways.

About 45% of Cadence’s customers are system companies that possess both hardware and software and are developing their custom semiconductor solutions. Even traditional semiconductor companies are turning into system companies, as the complexity of their design requires software and system-level hardware to deliver a solution. Mechanical and electrical systems are also converging—mechatronics—and Cadence must ensure it has solutions that cater to the emerging trend. Cadence is partnering with well-established leaders such as Dassault on the mechanical front to link the spheres of mechanical and electronics. As this trend continues, Cadence sees advanced packaging and PCB design playing a more critical role.

Cadence is investing about 40% of its revenue in R&D—one of the largest percentages of any large public company. Cadence has more than 9,500 employees, and more than 8,100 are engineers. As Dr. Devgan stated, the challenge has been to improve productivity and make the design easier to implement, from the transistor level to the cell level to design reuse with intellectual property (IP). One of the tools that the company introduced was the Fidelity CFD software, which provides a streamlined CFD workflow for design, multi-disciplinary analysis, and optimization in a single environment.

The next big frontier will be using AI-based EDA tools to aid in productivity and optimization. A lot of EDA is optimization—place-and-route, layout, and other aspects; however, in the systems space, Cadence wants to ensure the simulation is state of the art; there remains much room in optimization to automate design. At this year’s CadenceLIVE event, Cadence introduced the Optimality Intelligent System Explorer, which delivers very impressive results with its AI-driven multidisciplinary analysis and optimization (MDAO) technology for optimal system design and accuracy. The company also has hardware platforms—Palladium Z2 and Protium X2—that provide a hardware acceleration solution from debug to full software evaluation.

The next step—Cadence OnCloud—a cloud-based design solution where all a designer needs is a web browser to launch Cadence software. It is a flexible consumption-based model with a monthly subscription license and a set number of CPU hours. Designers can purchase more hours as their compute needs increase.

Following Dr. Devgan’s keynote, Tom Beckley, Senior Vice President and General Manager of the Custom IC & PCB Group at Cadence, outlined his group’s tool developments and some future directions. He highlighted the significant increase in the number of mechanical engineers (MEs) that Cadence has hired—about 200 MEs were brought on board to deal with future packaging and thermal design challenges.

Mr. Beckley sees a perfect storm coming in electronics, which is really about the shortage of semiconductors impacting many industries. Additionally, he sees “industry 4.0” unfolding—factories, manufacturing, and delivery are all increasingly electrified, intelligent, and automated. This will result in smart products and an increase in the use of artificial intelligence (AI) and machine learning (ML), which generate large amounts of data.

Over the last few decades, the semiconductor industry has been driven by Moore’s Law, which guided improvements to achieve higher performance, lower power, smaller area, and until recently, lower cost. Additional innovations, roughly grouped as “More-than-Moore,” adds techniques such as new transistor structures, chip stacking, the use of chiplets, and other packaging approaches to improve system integration further. Such packaging approaches also allow the mixing and matching of technologies—optical, RF, high voltage, analog, and digital in a single package.

Cadence is investing heavily in its multiphysics system analysis portfolio. Its solvers are distributed and parallelized, providing higher capacity and performance. The company also enables cross-platform design and analysis for better system optimization. For example, Cadence integrates its Celsius Thermal Solver for package and PCB electrothermal analysis with its Voltus IC Power Integrity Solution, which does IC power integrity signoff so power models can be exchanged in real-time. System heat dissipation always involves both conduction and convection, which is part of the IC package to PCB interface. Finite element analysis can be used to solve the dissipation issues, but then the enclosure and airflow is a fluidics challenge, which is why Cadence is integrating its Fidelity CFD solvers with Voltus and Celsius.

Everything has to be fully modeled and simulated. Cadence has developed several new solutions extending the current Allegro and Virtuoso platforms to support the next generation of wafer-level 3D packaging. The Integrity 3D-IC Platform includes system-level planning, full design, and the company’s analysis, extraction, and verification technologies. Cadence has also partnered with Dassault to connect the Allegro PCB Design software with Dassault’s 3D Experience platform. This transforms the basic electromechanical product development and establishes the first cloud-based end-to-end mechatronic solution. The company has integrated SOLIDWORKS with OrCAD and Allegro to target the mainstream companies.

To handle next-generation RF and millimeter-wave design solutions, tools from Cadence will enable designs in the 30-to-300GHz frequency bands for systems beyond current 5G standards. This will be necessary for the next generation of applications, such as the metaverse, which needs rapid data transmission. Telecom, automotive radar, remote sensing, image security screening, and defense applications will drive the mmWave market with an expected growth of 25% to 30% over the next decade.

Cadence is also partnering with Ericsson on RF and mmWave solutions for complex MIMO antenna arrays and beamforming designs. Such designs demand changes to how RF ICs are designed—the power amplifiers, transceivers, and other circuits. The RF circuits are very sensitive to physical layout, which forces designers to control transmission line widths and lengths during design to achieve the desired impedance values for the circuit. Cadence has integrated Virtuoso for custom ICs with Allegro PCB design to have a single “golden” schematic for RF. The company is also integrating Cadence AWR Microwave Office with Virtuoso Platform, allowing MMIC, TIMIC, and filter designs to move from Microwave Office into Virtuoso for RF SoC design. The SoCs can then move back into Microwave Office for module design or to Allegro for PCB design.

Finally, Mr. Beckley detailed the AI enablement of the Cadence system analysis portfolio. This is expected to deliver a 10X improvement in design productivity plus optimized designs. With the Optimality Explorer, designers can select multiple performance goals to optimize—from the package through to the PCB and back to the package and the chip. With the AI-enabled Optimality Explorer software, designers can allow the software, the cloud, and the processors to do the heavy lifting. All of Cadence’s best-in-class solvers can run on the Optimality engine in parallel. The software can simultaneously address multiple objectives with more than 100 parameters using deep learning technology.

Also read:

Refined Fault Localization through Learning. Innovation in Verification

224G Serial Links are Next

Tensilica Edge Advances at Linley

Podcast EP91: A Tour of Agile Analog’s Ground-Breaking Technology with its New CEO, Barry Paterson

Podcast EP91: A Tour of Agile Analog’s Ground-Breaking Technology with its New CEO, Barry Paterson
by Daniel Nenni on 06-30-2022 at 10:00 am

Dan is joined by Barry Paterson, Agile Analog’s new CEO. Barry has held senior leadership, engineering and product management roles at Wolfson Microelectronics and Dialog Semiconductor. He has been involved in the development of custom mixed-signal silicon solutions for many of the leading mobile and consumer electronics companies across the world and has a technical background in Ethernet, audio, haptics and power management.

Barry discusses Agile Analog’s unique IP portfolio and supporting software that facilities migration and optimization for any process node. Barry also covers the breadth of IP available, typical applications and plans for upcoming shows.

The views, thoughts, and opinions expressed in these podcasts belong solely to the speaker, and not to the speaker’s employer, organization, committee or any other group or individual.

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Using IP-XACT, RTL and UPF for Efficient SoC Design

Using IP-XACT, RTL and UPF for Efficient SoC Design
by Daniel Payne on 06-30-2022 at 6:00 am
Categories: Defacto Technologies, EDA

ESDA Revenue

The ESD Alliance collects and reports every quarter the revenue trends for both EDA and Semiconductor IP (SiP), and the biggest component for the past few years has been the SiP, as IP re-use dominates new designs. For Q4 of 2021 the total SiP revenue was $1,314.3 Million, enjoying a 24.8% growth in just one year. Here’s a chart to better show the IP trend:

How are engineers re-using all of this IP in their designs? EDA, IP and systems companies created the SPIRIT Consortium back in 2003 to address IP reuse, and by 2009 this group merged with Accellera, so there’s a long history to standardize how IP is defined and reused with IP-XACT, an XML format. The first IEEE standard for IP-XACT was named 1685-2009, then in 2014 it was superseded by IEEE 1685-2014. Defacto Technologies has been offering EDA tools to use IP-XACT more efficiently for 10 years now.

SoC Compiler

To integrate all of the IP blocks used in a new SoC design requires a methodology, and Defacto supports a front-end design flow that handles RTL, IP-XACT, UPF, LEF/DEF and SDC formats, getting your design ready for logic synthesis. SoC Compiler is the EDA tool from Defacto used for:

  • Design extraction and reuse for existing projects
  • IP connectivity insertion
  • SoC creation and assembly
  • Packaging at IP, subsystem and SoC levels
  • Generation of RTL, IP-XACT and other design collaterals
SoC Compiler Design Flow

SoC Compiler fully supports both the 2009 and 2014 versions of IP-XACT, so it works with all IP provided by vendors. A new feature in SoC Compiler is the ability to automatically extract the system memory map. Here’s an example of how RTL blocks on the left are turned into a memory map on the right, saving you time by not requiring any manual updates.

Extracting System Memory Map

Connectivity Insertion

During SoC assembly there is connectivity insertion, where all of the IP blocks are connected, then creating connections between different ports.  An input port for source and destination port for recipient need to be connected. This process is now highly complicated because of the number of connections that are expected. Using SoC Compiler manages automatically the interconnect used between AMBA AXI and other standard interfaces, just by reading RTL and IP-XACT.

UPF

The Unified Power Format – UPF,  started in 2006 and has been used to define the power control intent for chip designs. In the SoC Compiler tool flow it will create a UPF file that is correct-by-construction, allowing you to validate power intent consistency.

UPF Flow

The new ability added to SoC Compiler for UPF are:

  • Promotion – merge power-intent into higher scope
  • Demotion – split or propagate power-intent into lower scope

So it’s easy to restructure your IP, then automatically update the UPF files without resorting to manual and tedious editing.

UPF – promotion, demotion

DFT

To reach the highest test coverage goals, and reduce test time, an ATPG tool can propose a list of Test Points, but the problem is that this happens too late in the design flow, after logic synthesis. A new feature in SoC Compiler is for Test Point exploration, where you define the target coverage, type and number of Test Points, and the location of inserted Test Points, then it creates a new design with Test Points added. This allows you to quickly trade-off the number of Test Points to be used vs coverage.

Test Point Exploration

DAC 2022

When visiting San Francisco from July 10-14 at Moscone Center, West Hall, make sure to stop by the Defacto Booth on the first floor, #1543. Ask to see Bastien Gratréaux or Chouki Aktouf.

Innova Advanced Technologies

A new spin-off from Defacto was founded in November 2020, Innova Advanced Technologies, and that company is focused on a design flow, resource and project management portal. This approach replaces in-house tools to manage design flows.

Innova PDM

Summary

SoC design with IP reuse is a big challenge, because of the scale and complexity involved, so using the most efficient EDA tool flow makes economic sense. Defacto Technologies has been addressing this challenge through automation in SoC Compiler using standard formats like IP-XACT, UPF and RTL. The new features with each release are designed to save your precious SoC design time  by eliminating manual tasks.

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Using an IDE to Accelerate Hardware Language Learning

Using an IDE to Accelerate Hardware Language Learning
by Daniel Nenni on 06-29-2022 at 10:00 am
Categories: AMIQ EDA, EDA, RISC-V

Indian Institute of Technology IIT Bhubaneswar

Recently, in one of my regular check-ins with AMIQ EDA, I was pleased that they linked me up with an active customer. The resulting post summarized my discussion with three engineers from Kepler Communications Inc. They talked about using one of the AMIQ EDA products in the design of FPGAs for space-borne Internet connectivity. I told Cristian Amitroaie, CEO and co-founder of AMIQ EDA, that I enjoyed the experience and would be glad to talk to other users any time.

Cristian told me that they work with more than 150 companies in more than 30 countries, and then he mentioned that they also have many users in universities. I really like it when hardware and software vendors provide free or deeply discounted products to educational institutions. It gives students access to advanced technology that their schools cannot afford to buy at commercial prices and provides them with experience highly relevant for employment opportunities when they graduate. This system benefits the vendors as well; if the students like the products they use in college they may wish to buy them and continue using them when they are practicing engineers.

Naturally, I asked Cristian if he could arrange a discussion with one of their educational users. He kindly arranged for me to talk with Dr. Srinivas Boppu, Assistant Professor at Indian Institute of Technology (IIT) Bhubaneswar. The following covers the key points in our conversation.

Thank you for joining me today, Dr. Boppu. Anyone in engineering knows the excellent reputation of IIT. Can you please tell us a bit about the Bhubaneswar campus and your role there?

I’ll be glad to. Bhubaneswar is a city of about a million people and the capitol of the Indian state of Odisha. IIT Bhubaneswar was founded in 2008 during a major expansion of the IIT system, which now has 23 locations. I joined the faculty in 2017 to focus on IC design research and IP development. In addition to teaching classes, I currently have two PhD students, two Master’s students, and seven Bachelor’s students.

How did you get involved with AMIQ EDA?

Starting in 2011, I was a hands-on user while pursuing my PhD at Friedrich-Alexander-University of Erlangen-Nürnberg in Germany. I was writing VHDL while designing processor arrays for accelerating nested loops in computer programs. I had experience with integrated development environments (IDEs) for software and I wondered whether there might be a similar solution for hardware languages such as Verilog and VHDL. I discovered AMIQ EDA and requested an educational license for their Design and Verification Tools (DVT) Eclipse IDE.

How did you like the tool?

I found it really useful. It autocompleted the names of variables and other design elements, generated templates when I was instantiating new constructs in the code, and had great check and debug features. It saved me a lot of time and I remembered that when my students began writing Verilog code for projects at IIT. I started working with AMIQ EDA again, and they provided us all the educational licenses that we requested. I really appreciate that.

What sort of things are your students designing?

Let me start with the undergraduate courses. When we teach our advanced digital system design course, we require our students to complete a non-trivial final project. They write register transfer level (RTL) code for the hardware and develop a simple testbench, all in Verilog. They generally choose to design some sort of processor—Java Virtual Machine, IP block implementing the Google Bfloat16 floating-point spec, MIPS CPU, etc. The students also have to synthesize their design for FPGAs and demonstrate its operation in the lab, so this is indeed a significant project.

How does DVT Eclipse IDE help them?

For most students, this course is their first exposure to Verilog, which is rather different from a programming language such as C/C++ or Java. For example, they often have a hard time understanding blocking versus non-blocking assignments. Because the IDE provides templates and offers menus of options, they don’t have to learn every subtle detail of Verilog syntax and semantics. In a way, the IDE is almost like a coach, guiding them as they write code and nudging them in the correct direction with auto-fix suggestions when they make mistakes. I think that it greatly accelerates learning a new hardware language, and even for us long-time users it continues to have high value.

What about your graduate students? Do they have similar experiences?

Yes, I would say so. They often know Verilog fairly well already, but the designs they create are much larger and more complex. Last year I had a student who designed a vectorized floating-point processor comprising about 10K lines of Verilog code in 90 source files. Another student designed a 10×10 processor array that spanned six FPGA devices. Most of the students in my group use DVT Eclipse IDE for their code development and management. My graduate students typically use the IDE for 9-12 months, whereas students in undergraduate classes use it for only a month or two.

What are the benefits seen by you and your students?

I’ve already mentioned faster learning and faster coding, even for experienced users. We like the way that the IDE manages a whole project, which is especially important for the larger designs. Its incremental compilation and instant checking capabilities improve code quality and correctness, and they help my teaching assistants and me review the student designs. We are able to open the documents and reports at any time.

DVT Eclipse IDE helps users understand code that they didn’t write themselves, and it supports mixed languages. Both of these features are proving vital in a mixed-precision floating-point design, where the graduate student inherited some VHDL IP but is writing new code in Verilog.

How has your experience been working with AMIQ EDA?

They have been tremendously supportive. They’re great to work with and are responsive to suggestions for new features.

Could you give an example of something you wish DVT Eclipse IDE did?

We have some interest in using the Bluespec language because it is higher level than Verilog and is used for some RISC-V projects. We have asked AMIQ EDA to consider adding support and they are looking into it.

What’s next for you and your students?

I don’t expect our hardware design courses to change a lot, but the graduate projects are constantly evolving and growing. We have one design underway that will likely have a million gates. We also have some new PhD work in collaboration with other universities, and a common IDE will help keep the teams in sync.

We plan to try DVT IDE for Visual Studio (VS) Code, which AMIQ announced recently. Many of our students have experience with VS Code for software languages so we expect them to have interest in Verilog support as well. Finally, AMIQ EDA has directed my attention to some diagram generation features that we have not used much, so I plan to check those out soon.

Thank you very much for your time. It is good to know that AMIQ EDA is able to help educate the next generation of hardware engineers.

Thank you as well.

Also read:

AMIQ EDA Adds Support for Visual Studio Code to DVT IDE Family

Automated Documentation of Space-Borne FPGA Designs

Continuous Integration of RISC-V Testbenches

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Stalling to Uncover Timing Bugs. Innovation in Verification

Stalling to Uncover Timing Bugs. Innovation in Verification
by Bernard Murphy on 06-29-2022 at 6:00 am
Categories: AI, Cadence, EDA

Innovation New

Artificially stalling datapaths and virtual channels is a creative method to uncover corner case timing bugs. A paper from Nvidia describes a refinement to this technique. Paul Cunningham (GM, Verification at Cadence), Raúl Camposano (Silicon Catalyst, entrepreneur, former Synopsys CTO and now Silvaco CTO) and I continue our series on research ideas. As always, feedback welcome.

The Innovation

This month’s pick is Deep Stalling using a Coverage Driven Genetic Algorithm Framework. The paper published in the 2021 IEEE VLSI Test Symposium. The authors are from Nvidia.

Congestion is most likely to expose problems which can lead to deadlocks, ordering rule violations and credit underflow/overflow problems. Finding such problems requires creating a method to randomly stall FIFOs and pipelines to tease out those timing corner cases. Stalls create backpressure which is most likely to trigger such problems.

Verifiers can select which FIFOs to stall, and when. Given many FIFOs in a design, randomization is the default method to (weakly) optimize coverage in analysis. On the other hand, it creates concerns that it may miss many potential problems. The authors show how they apply genetic algorithms to learn how to improve coverage, using FIFO fill and RAM occupancy statistics as coverage metrics.

Paul’s view

This is a tight paper, easy to read, and provides a clear contribution. It tackles a very specific but important problem: how to most efficiently cover FIFO stalls in functional verification. The authors share that their GPU testbenches have special code to artificially force a FIFO to report full. This code is controlled by some randomized parameters: the probability of triggering the force, and the time window over which the force is held. There is a set of such parameters for each FIFOs in the design.

They use a genetic algorithm to select the best values of these parameters to maximize coverage. Each iteration of the genetic algorithm requires re-running all tests, which limits both initial population size and evolution cycles for the algorithm. To get around this limit, they train a neural network to predict functional coverage based on parameter settings and use this neural network for natural selection in their genetic algorithm rather than actually re-running tests. Using this neural network they are able to achieve a 60x increase in genetic algorithm capacity.

Results are solid – on a key system level coverage metric for the number of stalled GPU shader threads, the authors method can push up to 126 out of a theoretical maximum of 128 versus a baseline of only 90 without using the genetic algorithm and neural network. Using only the genetic algorithm but no neural network achieves 113.

In their introduction the authors note that there is no parameter in their testbench to directly control simultaneous stalling of multiple FIFOs. I can’t help but feel that such a parameter could be very effective to build up “backpressure” from multiple FIFOs being stalled and drive up corner case coverage. Identifying the appropriate groups of FIFOs to stall simultaneously to achieve the necessary backpressure could be well suited to the genetic algorithm proposed by the authors.

Raúl’s view

When a FIFO is full it stalls; it backpressures the transmitter trying to send a value to it. In well-designed systems this rarely occurs. To be able to simulate what happens if FIFOs fill, Nvidia inserts artificial stalls to generate backpressure. They generate stall lengths in Monte Carlo simulation to meet a given coverage goal.

The authors accelerate this process in two ways:

  • Using a Genetic Algorithm framework that evolves stall parameters using elitism, Roulette Wheel Selection and Standard Crossover. This boosts coverage, normalized by simulation time, by 163% for a design called UnitA and by 88% for UnitB. Looking at individual coverage objectives, most of them get a boost. One example showed 472%, although 4 out 11 don’t get any boost. In one case there was slight drop because the multi-objective evolutionary algorithm was trading this objective to maximize others.
  • A Deep Learning model learns the relationship function between the stalling parameters and the coverage metric. The DL model used is a “5-layered MultiLayer Perceptron (MLP) with batch normalization, dropout and RELU applied to all hidden layers. It uses a sigmoid activation function for the final layer.” It ran on 30,000 tests to generate data to train and validate the model. The model predicts the values for both the test data with an accuracy of 85% for the top 1,000 sorted tests and 57% for all 10,000 tests.

The authors conclude that they could intelligently tune stall parameters to significantly boost coverage metric over purely random stalling. This seems reasonable for the GA part. Although it may miss cases covered by a purely random approach as it favors certain parameter values. The DL model is an intriguing addition which presumably needs further development to rise above 57% accuracy.

It is a well written paper and easy to follow,. It focuses totally on the application and just states which genetic algorithm and deep learning model are used. I think this will appeal to designers and EDA tool builders who have added deep learning and genetic algorithms to their portfolio.

My view

In reading around this topic, I noticed multiple articles on backpressure routing in NoCs. This method may possibly have value there also.

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Intel Foundry Services Puts PDKs in the Cloud

Intel Foundry Services Puts PDKs in the Cloud
by Daniel Nenni on 06-28-2022 at 10:00 am
Categories: Foundries, Intel Foundry
3 Comments

Intel Foundry Services Roadmap

Intel announced today that they are partnering with cloud and EDA companies to better enable their foundry business. This is a natural extension of the Accelerator ecosystem program announced earlier. More and more chip designs are being done in the cloud and from my experience cloud based designs are better. Some companies use the cloud for reduced time-to-market, some for lower cost, and other companies rely on the seemingly unlimited compute resources for optimum PPA and to ensure first time silicon for complex designs.

While I have not had a personal experience with IFS I have heard some very good things by others who are engaged. I’m also very appreciative that IFS is participating in conferences including DAC and SEMICON WEST. In fact, IFS is the ONLY foundry at DAC this year so I expect their booth will be busy.

At the Intel 4 briefing I was amazed at the transparency which Scott Jones noted in his write up: Intel 4 Deep Dive. The dozen or so comments are worth reading, absolutely. Let’s hope this leads to a whole new level of technology transparency for foundries.

IFS will be using the Intel 16 (an optimized version of Intel 22nm, which was the first FinFET process to hit production), Intel 3, and 18A. You can see the latest IFS slide deck from the 2022 Investor Meeting HERE.

Here are the quotes associated with the press release. I know most of these people and have high regards for what they say so this is worth reading:

“By leveraging the scalability of cloud-based design environments, the IFS Cloud Alliance will enable broader access to Intel’s advanced process and packaging technologies. Our partnerships with leading cloud providers and EDA tool suppliers will provide a flexible and secure platform where customers can scale compute requirements instantly on production- proven design environments in the cloud.” Randhir Thakur, president of Intel Foundry Services

“We are excited to be collaborating with Intel in the launch of the IFS Cloud Alliance. We share a common goal to make semiconductor design and verification more scalable, and more accessible to a wide range of design teams, with the security and performance needed for reduced IC time-to-market and increased quality.” David Pellerin, director of Semiconductor Industry Solutions, Amazon Web Services

“Our close collaboration with Intel Foundry Services has brought together advanced node manufacturing with cloud computing and collaboration technologies, to establish a foundation for the next round of growth in the semiconductor industry. By joining Intel Foundry Services’ Cloud Alliance, Microsoft is proud to expand on that collaboration to provide a secure and scalable path to advanced silicon manufacturing. This is the latest chapter in the partnership between Intel and Microsoft that stretches back more than 40 years.” William Chappell, CTO, Mission Engineering, and vice president, Mission Systems, Microsoft Corp.

“Ansys’ comprehensive suite of interoperable, scalable multiphysics solutions plays a key role in IFS’ first design flow supported in the cloud. We look forward to continuing our long-standing collaboration with Intel to advance semiconductor design by ensuring that chip designers can access Ansys’ gold standard multiphysics solution via the cloud regardless of their chosen EDA workflow.” John Lee, vice president and general manager of the Semiconductor, Electronics, and Optics Business Unit, Ansys

“Cadence has longstanding leadership providing EDA solutions in the cloud and has successfully enabled thousands of customers to accelerate their innovation with our proven cloud solutions. Using the industry-leading, production-proven Cadence Cloud portfolio, which features highly flexible business models, customers have increased engineering productivity, significantly decreased turnaround times and improved overall cost efficiency. By joining the Intel Foundry Services Cloud Alliance, we’re enabling our mutual customers to leverage the scalable compute power of the cloud with our production-proven portfolio along with Intel’s advanced process and packaging technologies in a secure design environment.” Mahesh Turaga, vice president, Cloud Business Development, Cadence

“Siemens EDA has been optimizing tools for large-scale compute environments for more than 15 years. As part of the IFS Cloud Alliance ecosystem, Siemens EDA will work closely with cloud vendors, customers and Intel Foundry Services to leverage that experience to simplify the path to higher quality of results in less time. Siemens EDA is pleased to join the IFS Cloud Alliance ecosystem, and we look forward to extending the benefits of our industry-leading products and services to companies of all sizes who use Intel’s manufacturing services.” Craig Johnson, vice president, EDA Cloud Solutions, Siemens EDA

“Chip design is moving to the cloud at lightning speed. The Intel Foundry Services Cloud Alliance program will further accelerate the semiconductor industry’s adoption of cloud-based design, ensuring that engineers can continue to use the best technology, tools and flows as they move design to the cloud. We are collaborating with IFS as part of the Cloud Alliance, to enable our mutual customers to deploy our tools quickly and efficiently on the public cloud and help them deliver better products faster while meeting increasingly complex design and verification challenges.” Sandeep Mehndiratta, vice president, Enterprise Go-To-Market & Cloud, Synopsys.

Also read:

Intel 4 Deep Dive

An Update on In-Line Wafer Inspection Technology

0.55 High-NA Lithography Update

 

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Imec Buried Power Rail and Backside Power Delivery at VLSI

Imec Buried Power Rail and Backside Power Delivery at VLSI
by Scotten Jones on 06-28-2022 at 6:00 am
Categories: Events, Semiconductor Services, TechInsights
2 Comments

Imec BPR Page 06

At the VLSI Technology Symposium Imec presented on Buried Power Rails (BPR) and Backside Power Delivery (BSPD) in a paper entitled: “Scaled FinFETs Connected by Using Both Wafer Sides for Routing via Buried Power Rails”. I recently had a chance to interview one of the authors, Naoto Horiguchi about the work. I have interviewed Naoto several times in the past and presented alongside him at conferences and I always enjoy our conversations, he is very knowledgeable and easy to talk to.

Power Delivery is a growing problem at the leading edge. Two key issues addressed in this work are:

  1. On the metal 2 level there are power and ground rails at the top and bottom of standard logic cells. These rails are wider than routing lines to minimize the IR drop. Because half of each line is in the standard cell the wide lines limit cell scaling. As we transition to nanosheets this issue must be addressed to get to cells with less than 6-tracks.
  2. The upper metal layers of a process are very wide and provide global routing of power, but with 16 or more metal layers becoming common, there is a big IR drop bringing the power down through the chain of vias between each metal layer.

In this work the first problem is addressed with BPR, BPR replaces wide-thin power rails in metal 2, with tall-narrow power rails buried in the substrate. This technique reduces the area lost at the cell boundaries and for nanosheets can enable a 5-track or smaller cell.

The second piece is BSPD where the global power routing is done on the back of the wafer and then routed through the wafer with nano-Through Silicon Vias (nTSV). In order to minimize the IR drop the wafer must be very thin and the impact of extreme wafer thinning on the devices is explored in this work.

Figure 1 summarizes the scenarios:

Figure 1. Power Delivery Scenarios.

The addition of BPR reduces the dynamic IR drop by 26% and the addition of BSPD improves the IR drop by an additional 75%, see figure 2.

Figure 2. Dynamic Power Drop.

 Static IR drop is reduced by 23% by BPR and an additional 95% by adding BSPD, see figure 3.

Figure 3. Static Power Drop.

In previous BPR work Imec has used Ruthenium (Ru) for the BPR metal but in this work, they used Tungsten (W). Naoto said that Ru will be necessary at some point to support further scaling but at the scale of this work W was fine and is a well known metal in fabrication with well-defined cleans.

In figure 4, cross sections of the resulting structure and connections are shown. What I find amazing in this work is how incredibly thin the wafer is at less than one-micron. This enables low resistance for the nTSV.

Figure 4. Cross Section and Device Connections.

In figure 5 the process is illustrated for BPR and BSPD.

Figure 5. BPR and BSPD Process.

Some comments about the process flow:

  • An epitaxial process is used to deposit a silicon-germanium (SiGe) layer used as an etch-stop layer and then on top of that the silicon device layer is formed.
  • The W BPR is formed in the wafer.
  • The devices are fabricated.
  • The wafer is bonded to a carrier wafer.
  • Backgrind followed by a wet etch stopping on the SiGe layers is used to thin the wafer.
  • nTSVs are formed.
  • The BSPD is formed.
  • The wafer is annealed to recover performance.

I asked Naoto about the material used to bond the wafers together because the BSPD temperatures are likely too high for most temporary bonding materials. He said a Chemical Vapor Deposited (CVD) dielectric is used. This is based on the wafers not being separated after the process, this means signal lines would have to be routed in from the backside along with power.

Authors note: another question I recently looked into is how you precisely align the nTSV to the front side so they land on the BPR. I had a conversation with a contact at ASML and they said with the wafer this thin the aligners can “see” the front side alignment marks through the wafer. There are some distortion issues, but they are manageable. Long term there is interest in landing nTSV right on source/drains and that will require more work on alignment accuracy.

The bulk of this work was to evaluate device performance and the impact of extreme wafer thinning on the devices. Naoto said in some tests they thinned wafers until they hit the shallow trench isolation and they still got good device performance after annealing the wafer.

Authors note, both Intel and TSMC have announced BSPD for 2nm generation processes, clearly that is an emerging technology.

I told Naoto my sense is companies are hesitant to implement BPR because they must embed metals in the wafer prior to device formation. Intel has announced their BSPD with TSV’s they call PowerVia, they do not use BPR at least for their 20A and 18A process. TSMC is less clear to me, but I think they are avoiding BPR also. Naoto said he thought it wouldn’t be used in first generation BSPD but should be considered for further scaling.

This paper didn’t cover this, but BSPD also offers the possibility to add more functionality to the back of the wafer such as ESD devices, MIM capacitors, etc.

In conclusion, Imec has shown that BPR and BSPD can address the power delivery IR drop problem without degrading devices. This is important work for continued logic scaling.

Also read:

ASML EUV Update at SPIE

The Lost Opportunity for 450mm

Intel and the EUV Shortage

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Time is of the Essence for High-Frequency Traders

Time is of the Essence for High-Frequency Traders
by Dave Bursky on 06-27-2022 at 10:00 am
Categories: Achronix, eFPGA, IP, Silicon Creations
2 Comments

Figure Simplified block diagram of Multiprotocol PMA from Silicon Creations

In the world of financial trading, nanoseconds count. The faster a trade can be accomplished, the more money a trader can make. Getting a trade in before a competitor also results in improved profits. What does this have to do with the partnership deal recently inked between Silicon Creations and Achronix? Plenty. The two companies are parleying their expertise in analog and mixed-signal technology (Silicon Creations) and high-speed programmable logic (Achronix Semiconductor) to deliver Silicon IP supporting higher performance ASIC solutions with more design flexibility by creating interfaces with lower delays. The joint efforts focus on optimizing the data path from the Silicon Creations SerDes interface to and from the Achronix embedded field-programmable gate arrays (eFPGAs), which are both part of a larger system-on-chip (SoC) solution.

The combined efforts by the two companies are filling a need by suppliers of high-frequency trading systems (HFTS). Such HFTS are typically proprietary designs that demand the highest-performance, lowest-latency ASIC solutions. To push more performance and design flexibility into the HFTS, Silicon Creations and Achronix provide silicon IPs that enable their customers to optimize the data path from the SerDes interface to and from the eFPGA IP. That will allow trading system designers to add flexibility and achieve topnotch performance in algorithmic trading applications.

 

HFTS are typically proprietary designs that demand the highest-performing, lowest-latency silicon available. While ASICs are often a key component of such designs, eFPGA IP weaved into ASICs can deliver the performance and programmability that leading-edge systems require. Silicon Creations, a leading supplier of high-performance analog and mixed-signal intellectual property (IP), saw the synergy with programmable silicon, and that led to the partnership with Achronix Semiconductor Corporation, a leader in high-performance FPGAs and embedded FPGA (eFPGA) IP.

SerDes PMAs from Silicon Creations are optimized for ultra-low-latency optical connections, which are ideal for HFT Ethernet interfaces with in-PMA latency below 1.3 ns for 10G Ethernet. The SerDes PMAs also fit well in multiprotocol applications that support Ethernet 10G-KR, PCIe4, and many other protocols (see the figure). Multiprotocol SerDes PMA designs from Silicon Creations support over 30 protocols including CEI 6G & 11G SR, MR, LR, DisplayPort, Ethernet 10GBASE-X/S/K/R, PCIe Gen1/2/3/4, V-by-One HS/US, CPRI, PON, OTN/OTU, 3GSDI, JESD204A/B/C, SATA1-3, XAUI, SGMII. They have programmable (de)serialization widths of 8, 10, 16, 20, 32, or 40 bits. The transmit ring PLL includes fractional multiplication, spread spectrum and jitter cleaner function for Sync-E and OTU. Additionally, the PMAs offer out-of-band, electrical-idle signaling capability for SAS, SATA, and PCIe.

“We’re ready to provide tailored IP for HFT ASICs fabricated using 12/16 nm FinFET technology,” said Randy Caplan, co-founder and executive VP at Silicon Creations. “Engineers who need to stay at the front of today’s latency race must make a critical architectural decision: FPGA or ASIC? We think our partnership with Achronix to embed programmable logic in an ASIC offers the perfect blend of both technologies to drive improvements in programmable algorithmic trading.

Echoing a similar opinion, Steve Mensor, VP of Marketing and Strategic Planning at Achronix sees the partnership with Silicon Creations able to deliver a UDP-to-TCP loopback latency of under 10 ns, which is not possible with standalone FPGAs. “Together, we enable customers to create significant differentiation in their HFT systems by leveraging Achronix Speedcore eFPGA IP and Silicon Creations SerDes IP integrated into a customer’s ASIC.”

Read the full press release here: https://www.achronix.com/company/newsroom/news

For more information, visit www.siliconcr.com, and www.achronix.com

Also Read:

Creating Analog PLL IP for TSMC 5nm and 3nm

Essential Analog IP for 7nm and 5nm at TSMC OIP

Keeping Pace With 5nm Heartbeat

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TSMC 2022 Technology Symposium Review – Advanced Packaging Development

TSMC 2022 Technology Symposium Review – Advanced Packaging Development
by Tom Dillinger on 06-27-2022 at 6:00 am
Categories: Events, Foundries, TSMC
2 Comments

3D blox

TSMC recently held their annual Technology Symposium in Santa Clara, CA.  The presentations provide a comprehensive overview of their technology status and upcoming roadmap, covering all facets of the process technology and advanced packaging development.  This article will summarize the highlights of the advanced packaging technology presentations – a previous article covered the process technology area.

General

TSMC has merged their 2.5D and 3D packaging offerings into a single brand – “3D Fabric”.  The expectations are that there will be future customers that pursue both options to provide dense, heterogeneous integration of system-level functionality – e.g., both “front-end” 3D vertical assembly, combined with “back-end” 2.5D integration.

Technically, the 2.5D integration of SoCs with “3D” high-bandwidth memory HBM stacks is already a combined offering.  As illustrated above, TSMC is envisioning a much richer mix of topologies in the future, combining 3D SoIC with 2.5D CoWoS/InFO as part of very complex heterogeneous system designs.

As with the process technology presentations at the Symposium, the packaging technology updates were pretty straightforward – an indication of successful, ongoing roadmap execution.  There were a couple of specific areas representing new directions that will be highlighted below.

Of particular note is the TSMC investment in an Advanced System Integration fab, which will support the 3D Fabric offerings, providing full assembly and test manufacturing capabilities.

2.5D packaging

There are two classes of 2.5D packaging technologies – “chip-on-wafer-on-substrate” (CoWoS) and “integrated fanout” (InFO).

(Note that in the figure above, some of the InFO offerings are denoted by TSMC as “2D”.)

The key initiative for both these technologies is to continue to expand the maximum package size, to enable a larger number of die (and HBM stacks) to be integrated.  As an example, the fabrication of the interconnect layers on a silicon interposer (CoWoS-S) requires “stitching” multiple lithographic exposures – the goal is to increase the interposer size in term of multiples of the maximum reticle dimensions.

  • CoWoS

CoWoS has expanded to offer three different interposer technologies (the “wafer” in CoWoS):

  • CoWoS-S
    • uses a silicon interposer, based on existing silicon wafer lithographic and redistribution layer processing
    • in volume production since 2012, >100 products for 20+ customers to date
    • the interposer integrates embedded “trench” capacitors
    • 3X max reticle size in development – to support a design configuration with 2 large SoC’s and 8 HBM3 memory stacks, with eDTC1100 (1100nF/mm**2)
  • CoWoS-R
    • uses an organic interposer for reduced cost
    • up to 6 redistribution layers of interconnect, 2um/2um L/S
    • 2.1X reticle size supporting one SoC with 2 HBM2 stacks in a 55mmX55mm package; 4X reticle size in development, with 2 SoCs and 2HBM2 in an 85mmX85mm package
  • CoWoS-L
    • uses a small silicon “bridge” inserted into an organic interposer, for high density interconnects between adjacent die edges (0.4um/0.4um L/S pitch)
    • 2X reticle size supports 2 SoCs with 6 HBM2 stacks 2023); 4X reticle size in development to support 12 HBM3 stacks (2024)

TSMC highlighted that they are working with the HBM standards group on the physical configuration of HBM3 interconnect requirements for CoWoS implementations.  (The HBM3 standard appears to have settled on the following for the stack definition:  capacity of 4GB w/four 8Gb die to 64GB w/sixteen 32Gb die; 1024-bit signal interface; up to 819GBps bandwidth.) These upcoming CoWoS configurations with multiple HBM3 stacks would provide tremendous memory capacity and bandwidth.

Also, in anticipation of much greater power dissipation in upcoming CoWoS designs, TSMC is working on appropriate cooling solutions, both improved thermal-interface-materials (TIM) between die and package, as well as transitioning from air to immersion cooling.

  • InFO

After accurate (face-down) placement orientation on a temporary carrier, die are encapsulated in a epoxy “wafer”.  Redistribution interconnect layers are added to the reconstituted wafer surface.  The package bumps are then connected directly to the redistribution layers.

There are InFO_PoP, InFO_oS, and InFO_B topologies.

As shown below, InFO_PoP denotes a package-on-package configuration, and is focused on integration of a DRAM package with a base logic die.  The bumps on the DRAM top die utilize through-InFO vias (TIV) to reach the redistribution layers.

  • InFO_PoP primarily for the mobile platform
  • over 1.2B units shipped since 2016

An issue with the InFO_PoP implementation is that currently the DRAM package is a custom design, and only able to be fabricated at TSMC.  There is an alternative InFO_B topology in development, where an existing (LPDDR) DRAM package is added on top, with assembly to be provided by an external contract manufacturer.

InFO_oS (on-substrate) enables multiple die to be encapsulated, with the redistribution layers and their microbumps connected to a substrate with TSVs.

  • in production for over 5 years, focus is on HPC customers
  • 5 RDL layers on the substrate, with 2um/2um L/S
  • the substrate enables a large package footprint, currently at 110mm X 110mm with plans for greater sizes
  • 130um C4 bump pitch

As depicted above, InFO_M is an alternative to InFO_oS, with multiple encapsulated die and redistribution layers, without the additional substrate + TSVs (< 500mm**2 package, production in 2H2022).

3D packaging

InFO-3D

There is a 3D stacked package technology that utilizes micro-bumped die integrated vertically with redistribution layers and TIVs, focused on the mobile platform.

3D SoIC

The more advanced vertical-die stacked 3D topology packaging family is denoted as “system-on-integrated chips” (SoIC).  It utilizes direct Cu bonding between the die, at an aggressive pitch.

There are two SoIC offerings – “wafer-on-wafer” (WOW) and “chip-on-wafer” (COW).  The WOW topology integrates a complex SoC die on a wafer providing deep trench capacitor (DTC) structures for optimal decoupling.  The more general COW topology stacks multiple SoC die.

The process technologies qualified for SoIC assembly are shown in the table below.

Design Enablement for 3DFabric, including 3Dblox

As illustrated in the upper right corner of the 3D Fabric image above, TSMC is envisioning complex system design-in-package implementations, combining both 3D SoIC and 2.5D technologies.

The resulting complexity in the design flow is great, as highlighted above, with advanced thermal, timing, and SI/PI analysis flows required (which can also deal with the model data volume).

To enable the development of these system-level designs, TSMC has collaborated with EDA vendors on three major design flow initiatives:

  • improved thermal analysis, using a coarse-grained plus fine-grained approach)
  • hierarchical static timing analysis
    • individual die are represented by an abstracted model, to reduce the total (multi-corner) data analysis complexity 
  • front-end design partitioning

To help accelerate the front-end design partitioning of a complex system, TSMC has pursued an initiative denoted as “3Dblox”.

The goal is to break down the overall physical package system into modular components, which are then integrated.  The module categories are:

  • bumps/bonds
  • vias
  • caps
  • interposers
  • die

These modules would be incorporated into any of the SoIC, CoWoS, or InFO package technologies.

Of specific note is that TSMC is driving an effort to enable 3D Fabric designs to use various EDA tools – that is, to complete physical design with one EDA vendor tool, and (potentially) use different EDA vendor products for support for timing analysis, signal integrity/power integrity analysis, thermal analysis.

3Dblox appears to take the concept of “reference flows” for SoCs to a new level, with TSMC driving interoperability between EDA vendor data models and formats.  The overall 3Dblox flow capability will be available in 3Q2022.  (A preliminary step – i.e., automated routing of redistribution signals on InFO – will be the first feature released.)

Clearly, TSMC is investing extensively in advanced packaging technology development and (especially) new fabrication facilities, due to the anticipated growth in both 2.5D and 3D configurations.  The transition from HBM2/2e to HBM3 memory stacks will result in considerable performance benefits to system designs utilizing CoWoS 2.5 technology.  Mobile platform customers will expand the diversity of InFO multi-die designs.  The adoption of complex 3DFabric designs combining both 3D and 2.5D technologies will no doubt increase, as well, leveraging TSMC’s efforts to “modularize” the design elements to accelerate system partitioning, as well as their efforts to enable a broad set of EDA tools/flows to be applied.

-chipguy

Also Read:

TSMC 2022 Technology Symposium Review – Process Technology Development

Three Key Takeaways from the 2022 TSMC Technical Symposium!

Inverse Lithography Technology – A Status Update from TSMC

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Multiphysics, Multivariate Analysis: An Imperative for Today’s 3D-IC Designs

Multiphysics, Multivariate Analysis: An Imperative for Today’s 3D-IC Designs
by Daniel Nenni on 06-26-2022 at 6:00 am
Categories: Ansys, Inc., EDA, Events

Ansys Heat Map

Semiconductor manufacturers are under constantly increasing and intense pressure to accelerate innovative new chip designs to market faster than ever in smaller package sizes while assuring signal integrity and reducing power consumption. Three-dimensional integrated circuits (3D-ICs) promise to answer all these demands but, at the same time, they introduce a new level of design complexity that is challenging traditional tools and processes.

Manufactured by stacking dies and interconnecting them so they perform as a single device, 3D- ICs create new risks, including thermal build-up caused by greater density. Because they’re significantly larger than a typical system-on-a-chip (SoC), with longer interconnects, they need to be rigorously tested for faulty integration points as well as system-level failures.

However, most semiconductor development teams simply aren’t equipped to manage the difficult job of 3D-IC analysis and design validation. They’re burdened by a historical approach to SoC simulation that relies on a serial, step-by-step process, in which single-physics simulation tools are applied one by one. When engineers apply these disparate tools, and this serial process, to complex 3D-IC designs, they’re missing system-level interactions, connection points, consolidated thermal effects and other considerations for something to go seriously wrong.

As 3D-ICs become more common for advanced semiconductor applications, engineering teams need a new analytic approach that’s equally innovative. They need a single, open and proven platform to conduct concurrent, multivariate simulation and analysis across the entire product design. They need to consider multiple physics, quickly and simultaneously, at both the component and system levels.

An Open Platform for Optimizing Every Performance Aspect

Ansys’ industry-leading solutions for 3D-IC simulation and analysis provide engineering teams with best-in-class capabilities for optimizing every aspect of performance, including power integrity, reliability, electromagnetics (EM), thermal, computational fluid dynamics (CFD) and mechanical stress.

This is a resistance heatmap of a chip-package system with pin resolution The IR drop map and electromigration map can also be generated for power integrity and reliability sign-off of 3DIC system.

The comprehensive Ansys toolkit positions semiconductor engineering teams to assess stand-alone performance aspects like thermal conductivity, while simultaneously looking at every other critical metric. The entire 3D-IC design can be subjected to realistic operating conditions as an integrated system, beginning at the earliest design stage.

This is a temperature contour map of a chip-package system with die, interposer and package modeled by RHSC ET. The nodal temperature at each layer of the system can be displayed to identify the hotspot location for applying thermal integrity solutions.

Ansys provides a unified 3D-IC simulation platform incorporating our best-in-class solutions. For example, Ansys RedHawk-SC Electrothermal can be leveraged to verify the thermal hotspots, melting risk, local failure modes of each welding site, based on the electrical current load at that specific point. Ansys CFD capabilities can optimize the performance of fans and heat sinks as they generate airflows to cool the assembly. Ansys solutions can also analyze advanced performance aspects, such as low-frequency power oscillations, and predict their impact on the larger design.

Shown here is an analysis of mechanical stress/warpage, as well as thermal gradients, in a 3D-IC multi-die package. This is an example of a complex real-world problem that can only be solved quickly via a multiphysics, multivariate approach.

Not only does Ansys address all of these individual engineering challenges through best-in-class solvers, but it equips semiconductor development teams to conduct these studies simultaneously. Only Ansys supports this type of multiphysics, multivariate, concurrent approach that reveals critical design trade-offs at the system level, rapidly and at an early stage.

In Your Rush to Market, Don’t Shortchange Your Analysis

Faced with worldwide chip shortages, increasing performance demands, a lack of engineering talent, and an urgent need for low-cost innovation, semiconductor manufacturers may be tempted to focus on their existing set of serial processes and isolated, single-physics simulation tools. But these outdated methods are insufficient to capture the complexity of 3D-IC designs and their equally complex failure risks.

Different engineers, using different simulation and analysis tools, may actually work at cross-purposes. For instance, one team’s efforts to resolve a signal-integrity issue might inadvertently create a timing failure or thermal risk that needs to be resolved by another team — which then hands it back to the signal-integrity team. The result? The dreaded ping pong effect with costly delays, resource-intensive handoffs, and significant rework.

In contrast, the robust and comprehensive Ansys simulation platform supports synergistic, collaborative, and cross functional analysis. It’s fast and intuitive for the multidisciplinary design team to look at the holistic 3D-IC design and concurrently analyze novel physics, to optimize performance aspects from electrical reliability to mechanical and thermal stability.

Collaboration-Driven Innovation: The Wave of the Future

The world’s semiconductor leaders are realizing that true 3D-IC innovation requires a new level of collaboration and vertical integration. Only by removing traditional functional boundaries — and eliminating a single-physics, serial approach — can development teams accelerate the design cycle, drive down costs, and produce game-changing new performance innovations.

Ansys’ open, extensible, and powerful simulation platform for multiphysics 3D-IC simulation is purpose-built to realize this vision. By leveraging a unified platform with proven, best-in-class solutions for multiphysics and multiscale analysis, semi development teams can launch new designs quickly and collaboratively, without sacrificing analytic rigor or product confidence. Costly handoffs and rework are reduced as the cross functional team shares the same understanding of performance trade-offs and ultimate goals.

While it can be difficult to break down cultural and organizational barriers to collaboration and vertical integration, the rewards are well worth it, including faster time-to-market and higher levels of innovation. Replacing sequential analysis and a disparate toolkit with the Ansys platform to support concurrent, multiphysics, system-level design simulations is a critical first step.

Visit Ansys at DAC 2022

If you’re hoping to fully capitalize on the incredible promise of 3D-IC designs, you owe it to yourself to learn more about the Ansys platform for multivariate, multiphysics simulation. Visit Ansys at Booth #1539 at the Design Automation Conference (DAC), in San Francisco July 11-14. Request a meeting or product demo now to start supporting a new level of 3D-IC design optimization.

Also read:

A Different Perspective: Ansys’ View on the Central Issues Driving EDA Today

Unlock first-time-right complex photonic integrated circuits

Take a Leap of Certainty at DAC 2022