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NILS Enhancement with Higher Transmission Phase-Shift Masks

NILS Enhancement with Higher Transmission Phase-Shift Masks
by Fred Chen on 07-24-2023 at 8:00 am
Categories: Lithography
2 Comments

Figure 1. NILS is improved

In the assessment of wafer lithography processes, normalized image log-slope (NILS) gives the % change in width for a given % change in dose [1,2]. A nominal NILS value of 2 indicates 10% change in linewidth for 10% change in dose; the % change in linewidth is inversely proportional to the NILS. In a previous article [2], it was shown that NILS is better for a dark feature against a bright background than the other way around. Attenuated phase shift masks (attPSMs) help to improve the NILS to reach values of 2 or more, in cases where conventional binary masks can’t without an exorbitantly high dose.

Increasing the transmission of the attenuated phase shift mask [3] takes the improvement further. A higher transmission effectively makes the dark areas darker, which increases the image log-slope.

Figure 1. NILS is improved for higher transmission of the attenuated phase-shift mask. The images are taken along the long axis of a dense oblong (1.3:1) pattern with cross-dipole illumination. The graph on the right uses the log scale instead of linear scale for the y-axis, representing intensity. The more obvious dip indicates better NILS for the higher transmission (16% vs 6%).

Besides improving NILS, the mask error sensitivity and depth of focus are also improved [3]. Improving the NILS is particularly important for improving the resolution of 2D shapes such as in Figure 1 or in the header above this article. For the 12% attPSM of Ref. 3, a square feature width of 65% of pitch with cross-dipole illumination (for tightest 2D resolution: dipole illumination in X + dipole illumination in Y) just manages to hit a NILS of 2.0 in both x and y. This is another opportunity to improve 2D resolution for DUV, especially for core patterning for self-aligned double patterning (SADP) [4].

References

[1] C. A. Mack, “Using the Normalized Image Log-Slope,” The Lithography Expert, Microlithography World, Winter 2001: http://lithoguru.com/scientist/litho_tutor/TUTOR32%20(Winter%2002).pdf

[2] F. Chen, “Phase-Shifting Masks for NILS Improvement – A Handicap for EUV?”, https://www.linkedin.com/pulse/phase-shifting-masks-nils-improvement-handicap-euv-frederick-chen

[3] T. Faure et al., “Development of a new high transmission phase shift mask technology for 10 nm logic node,” Proc. SPIE 9984, 998402 (2016).

[4] H. Yaegashi et al., “Overview: continuous evolution on double-patterning process,” Proc. SPIE 8325, 83250B (2012).

This article first appeared in LinkedIn Pulse: NILS Enhancement with Higher Transmission Phase-Shift Masks

Also Read:

Assessing EUV Wafer Output: 2019-2022

Application-Specific Lithography: 28 nm Pitch Two-Dimensional Routing

A Primer on EUV Lithography

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Intel Enables the Multi-Die Revolution with Packaging Innovation

Intel Enables the Multi-Die Revolution with Packaging Innovation
by Mike Gianfagna on 07-24-2023 at 6:00 am
Categories: Foundries, Intel Foundry
2 Comments

Intel Enables the Multi Die Revolution with Packaging Innovation

The trend is undeniable. Highly integrated monolithic chips can no longer handle the demands of next-generation systems. The reasons for this significant shift in design are many. Much has been written on the topic; you can get a good overview of the forces at play in multi-die design here. These changes represent the next chapter in the pursuit of exponential scaling originally defined by Moore’s Law. So, it is quite natural to look to Intel, the birthplace of Moore’s Law, for a peek at what lies ahead. Read on to see how Intel enables the multi-die revolution with packaging innovation.

The Packaging Challenge

The move to multi-die systems creates substantial design and manufacturing challenges. Billions of transistors are now spread across multiple dies integrated with complex package form factors containing millions of bump connections. The resultant heterogeneous integration demands a silicon, package and board co-design approach. 

Conventional approaches to these challenges often involve a silicon interposer to implement a “2.5D” integration. Drawbacks of this approach include the cost of the extra silicon and increased design complexity and reduced yield. The number and type of dies that can be integrated is also limited with this approach.

Finding a Better Way – EMIB

Intel has found a way around many of the current limitations of 2.5D packaging. Embedding a small silicon bridge chip into the package is the answer. EMIB, or embedded multi-die interconnect bridge, delivers a cost-effective way to connect multiple dies within a package. An overview of the approach is provided in the figure below.

EMIB Overview

A highly scalable capability is delivered with EMIB. There is now flexibility in total design size, number of chiplets bridge dimensions, and localized optimizations to support a wide variety of heterogeneous configurations. EMIB has been proven on several designs, as shown in the figure below.

Real Product Examples

Implementing EMIB – The Power of the Ecosystem

EMIB-based package design has its own set of challenges. The approach presents high pin count, net count and design density. An example design could contain 24 layers, 52,000 nets and 240,000 pins. All this must be managed across a heterogeneous design flow to achieve low latency and optimal energy efficiency.

Intel Foundry Services (IFS) have repeatedly stated their commitment to bring Intel technology to customers via the industry standard and powerful avenue of a foundry ecosystem. Staying true to that commitment, Intel approached this problem with standards and ecosystem collaboration. Data management, silicon/package/board co-design, consistent modeling/analysis and optimized cost and performance via design reuse are all supported with a comprehensive package assembly design kit (PADK). The PADK contains:

  • EMIB Design Guide
    • SI/PI Collateral
    • Thermal Tolerance
    • Mechanical Parameters
  • Package Library
    • Layout Template
    • Padstacks/Pins/Vias
    • Parts and Fiducials
  • Stack Up
    • Thickness
    • Tolerance
  • Design Rule Specs
    • Manufacturing Checks
    • Assembly Checks
    • Design Rule Checks
  • Performance
    • Electrical Rules
    • Constraints

Using this information, Intel built an EMIB-based reference flow with its key EDA partners. There is a design and an analysis reference flow in development. The figure below summarizes the status of each flow across the ecosystem.

Design Flow Status

What’s Next

There is much more to come from Intel in this area. Additional work includes:

  • Die-to-Die IP with UCIe
    • Reusability, compatibility, standardization
  • EDA-CAD agnostic standards
    • Chiplets, tech files, collateral, kits with end-to-end focus for ecosystem development
  • EDA framework
    • Silicon/package/system co-design
    • Interoperable EDA tools, flows and methods
    • Data exchange and workflows

The Intel view is that advanced packaging technology, content density, and package complexity requires new methods to drive design efficiency. The focus is to collaborate for ecosystem development using design standards and vendor agnostic tools, flows and methods.  And that’s how Intel enables the multi-die revolution with packaging innovation, and IFS delivers it to the external customers.

Also Read:

Intel Internal Foundry Model Webinar

VLSI Symposium – Intel PowerVia Technology

IEDM 2022 – Ann Kelleher of Intel – Plenary Talk

Podcast EP173: The Impact of Celestial AI’s Photonic Fabric on the Future of High-Performance Architectures

Podcast EP173: The Impact of Celestial AI’s Photonic Fabric on the Future of High-Performance Architectures
by Daniel Nenni on 07-21-2023 at 10:00 am

Dan is joined by Dave Lazovsky, CEO of Celestial AI. Dave has an in-depth knowledge of semiconductor, data/telecommunications, photonics and clean energy industries, as well as extensive international business experience. He currently has over 50 issued and 5 pending U.S. patents.

In this broad and forward-looking discussion, Dave explains the incredible demands being placed on next-generation compute architectures. He explores the capabilities of Celestial AI’s optical interconnect technology platform for memory and computation. He describes the game-changing impact the company’s Photonic Fabric can have on performance, energy efficiency and flexibility.

The views, thoughts, and opinions expressed in these podcasts belong solely to the speaker, and not to the speaker’s employer, organization, committee or any other group or individual.

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ASML-Strong Results & Guide Prove China Concerns Overblown-Chips Slow to Recover

ASML-Strong Results & Guide Prove China Concerns Overblown-Chips Slow to Recover
by Robert Maire on 07-21-2023 at 8:00 am
Categories: Semiconductor Advisors, Semiconductor Services
2 Comments

ASML 2023 Results

-ASML reports better results & guide despite China restrictions
-Supports our view of China issues not that impactful longer term
-Industry recovery seems very far off with more delays
-ASML remains the best, most robust story in a weak industry

ASML reports nice beat despite China concerns

ASML reported revenues of Euro6.9B of which Euro5.6B was for systems with EPS of Euro4.93 . This is roughly $7.52B in revenues and $5.37 in EPS versus street estimates of $7.48B and $5.10…so a nice beat.

Guidance is for between Euro6.5B and 7.0B in revenues. At the midpoint this is roughly $7.57B versus expectations of $7.14B.

Margins remained above 50%.

Perhaps most importantly, ASML expects that growth in 2023 will be roughly 30% above that of 2022 which is up from prior expectations of 25-27%.

All in all a very good quarter despite industry weak conditions and macroeconomic uncertainty.

Confirms our view that China impact is minimal and not significant

We have suggested since the start of sanctions on the sale of litho tools to China that the overwhelming demand for ASML’s tools would more than offset tools impacted by sanctions. This appears to be the case as demand from China for older technology tools is stronger than ever.

We think investor concerns continue to be overblown as overall demand remains quite strong despite the prolonged industry downturn.

Semiconductors remains a zero sum game

In the long term, semiconductor production will remain a zero sum game. By that we mean that chips not produced in China will have to be produced elsewhere by some other country perhaps at a slightly higher cost but using the same ASML tools that China would have otherwise bought.

In a way, the restrictions on sales to China may help to diversify demand and chip production across the globe so that China does not dominate both the purchase of tools as well as production.

While this may cause disruption in the near term it likely is better for all in the long term as it prevents the total domination we have seen from China in both the solar and LED markets. We wouldn’t want what happened in those markets to happen in the much more critical chip market.

We strongly maintain our belief in the control of exports of chip equipment to China to prevent that from happening for both defense and economic concerns.

China is buying plenty of DUV tools anyway

Its certainly not like China isn’t buying a lot of tools from ASML as they can still buy DUV tools and continue to do so in large quantity. The DUV business for ASML remains quite robust at almost 50% of overall business. Up from prior quarters.

Memory even worse than before, almost down by 50% Q/Q

While logic and foundry, especially in trailing edge remains strong, memory continues its nosedive with memory related sales dropping by almost half quarter over quarter from 30% of sales in Q1 to just 16% of sales in the just reported quarter.

As we have continued to repeat…memory is very, very ugly. There is no recovery in sight and capex continues to trend down in memory to just sustenance levels and no more

Fab delays are impactful

We had mentioned in our note from SEMICON West last week that we were growing concerned about delays in planned fab construction and likely further delays and cancelations as capacity is clearly not needed in foundry/logic and especially not in memory which is swimming in capacity.

ASML pointed out that fab utilization remains low which means tool utilization is low. ASML said that fab delays are delaying and pushing out deliveries of equipment.

We clearly haven’t seen the end of this and fab delays will likely worsen as the downturn extends into next year.

Right now we are just seeing delays but some of that could turn to cancelations if the fabs they were intended for get canceled.

Fantastic job on DUV offsets weakness to some extent

ASML is now talking about shipping a staggering 375 DUV tools of which 25% would be immersion. Rather than Euro3B of revenue that was expected to be delayed from 2023 to 2024, ASML has instituted some fast ship protocols and will see an additional Euro700M in 2023.

This helps offset other weakness and contributed to increasing the overall 2023 growth rate.

This obviously helps make up for slowing EUV sales which were expected to grow 40% Y/Y but now expected to grow only 25% Y/Y.

The book to bill wasn’t great with Euro4.5B in orders but the backlog remains strong and long at Euro38B, a huge number that will continue to keep ASML warm through the now lengthened chip winter.

Somewhat worse news on industry downturn confirms our pessimistic view

We have been suggesting since the beginning of this downcycle almost a year ago that this down cycle would be worse than most due to a variety of circumstances. This appears to be the case and the prolonged downturn seems to have been communicated in ASMLs report as they had essentially no hint of a recovery and a number of factors worsened.

We have also clearly communicated that we can’t have a significant recovery of the overall industry without memory recovering as well….it just doesn’t happen that way.

Right now memory is as bad as ever. Pricing remains low, bloated inventories, lowered production, cut capex…..all bad signs on top of macro economic issues.

AI is not the savior of AI and we think investors may be figuring that out

The stock- A beautiful mansion with a moat in an ugly neighborhood

If we had to buy one semiconductor equipment stock ASML would be it. Growing 30% Y/Y during a downturn is just amazing. They are a true monopoly with dominant market share and technology with zero competition.

China issues are not impactful in our view and could offer long term benefit.

The long term semiconductor view remains very positive.

The obvious problem is that in the near term the industry remains ugly. ASML will outperform the group by far during the downturn as they are already proving. They will also be the first out of the downturn as litho tools are the first thing you buy for your new fab.

We would equate ASML to being a beautiful, well built mansion with a deep moat around it in a neighborhood that is going through a difficult period of transition.

It may be the best home in town but investors may be concerned about buying in at this particular point in time given the overall neighborhood condition, thus we will see a weak stock despite financial & technical out performance.

We view this report more negatively for others in the semiconductor equipment space as it suggests a longer downturn that we have predicted and as we mentioned last week, investors may start to get impatient as the recovery seems further away tahn hoped.

Also Read:

SEMICON West 2023 Summary – No recovery in sight – Next Year?

Micron Mandarin Memory Machinations- CHIPS Act semiconductor equipment hypocrisy

AMAT- Trailing Edge & China Almost Offset Floundering Foundry & Missing Memory

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Upskill Your Smart Soldiers and Conquer the Chip War in Style!

Upskill Your Smart Soldiers and Conquer the Chip War in Style!
by Sivakumar PR on 07-21-2023 at 6:00 am
Categories: Maven Silicon, RISC-V, Semiconductor Services

Maven Silicon Article Figure 1

My recent article, ‘Chip War without Soldiers’ explained the importance of upskilling and preparing the chip design workforce in this current scenario, and it also explained how it will lead to ‘Fabs without Chips’ if we don’t prioritize it. VLSI Engineers are the pillars of the semiconductor industry, and they can only transform our industry into a trillion-dollar industry with their inventions and innovations. So, in this article, I want to explain how Maven Silicon can collaborate with your organization as the VLSI Centre Of Excellence for upskilling your chip design workforce and why you should choose Maven Silicon as your preferred VLSI training partner.

To understand ‘Why Maven Silicon for upskilling your workforce?’ – Let me convince you with our USPs.

Maven Silicon USPs:
  1. Scalable Training Services: Maven Silicon is the only VLSI training company that can train engineers in bulk worldwide using our cloud-based online training solutions. We are the one who introduced this kind of innovative learning subscription model to tier-1 global product and services semiconductor MNCs. Today we train thousands of VLSI engineers every year for our enterprise customers. At Maven Silicon, we also provide ILT-Offline and VILT-Blended-online courses for project-specific specialized training courses. So, we can support your workforce L&D initiatives at any scale as per your business requirements.
  2. Flexible Business Models: We offer inexpensive multi-year learning subscription business models to upskill an army of engineers globally, along with our standard corporate training business models, which involve training a batch of engineers [Instructor-Led Offline Project/Domain specific Specialized Training] periodically for various projects.
  3. Domain Expertise: Maven Silicon has been designated as ARM Approved Training Partner by ARM and Global RISC-V Training Partner by RISC-V International to train the VLSI engineers on their processor architectures. Synopsys and Siemens EDA are our EDA partners. All our lead trainers have been trained formally by our industry partners ARM, RISC-V, Synopsys, and Siemens EDA. Our trainers are specialized in various VLSI domains like RTL Design and Verification, DFT, Physical Design, SoC Design, ASIC & FPGA, ARM and RISC-V. The image below explains how we offer various VLSI courses and support our enterprise customers with our domain expertise and flexible business models.

Click here to view the full image

I also want to share some of the myths and fallacies about upskilling the VLSI engineers we observed while interacting with the project managers and business heads in India and explain how we can collaborate with your L&D team to address their challenges or concerns.

Myths & Fallacies:

1) Internal Training is very effective and inexpensive: Internal training might be effective, but it’s not a scalable model. Refer to our USPs 1&2. Involving your experienced and expensive project managers as trainers in the internal training programs will be more expensive than involving external vendors. Training services are our core business, so we deliver our courses efficiently with our unique pedagogy and curricula. We regularly learn new technologies and update our curricula.

A traditional, highly experienced project manager may not be competent to train the next generation of engineers on the latest technologies and design methodologies. For example, V-Plan based CRCDV using UVM is different from Test plan-based HDL verification. Some experienced traditional DV project managers refer to the Test plan [Directed testcases] while using UVM/SystemVerilog, like how we casually use the term ‘DUT’ for DUV. Can they quickly unlearn traditional and outdated techniques/methodologies? What if they leave your company because of this additional training responsibility – teaching, developing, and maintaining course content? What about the additional efforts and expenses incurred by your LMS software and EDA licenses? What is your core business – EDA or Product or Design Services, and why don’t you dedicate your expensive, experienced resources to grow your core business?

2) External Training is expensive: Why should a billion-dollar VLSI company be conservative as miserliness for upskilling its workforce? It’s time for us to think beyond free learning subscriptions and internal training programs and invest more in new L&D initiatives to support our VLSI engineers for their long-term career development. Refer to our USPs 1&2. We offer various online and offline VLSI training programs with flexible business models to upskill your engineers efficiently within your L&D budget. Companies that support engineers generously for their long-term career growth can retain them for long and grow them as next-generation leaders. Hiring culturally fit experienced engineers, project leads, managers, architects, and engineering directors from competitors is very expensive than investing in L&D upskilling initiatives. Isn’t it?

3) Internship is more effective than direct hiring: Whether direct hiring or internship, it can be more effective only with proper training and coaching/mentorship. In the case of hiring New College Graduates, we partner with our customers to upskill them using our pre-onboarding NCG training courses. It is unique as this pre-onboarding training begins during their engineering course during the pre-final/final year. It works beautifully for the companies to onboard them efficiently without much attrition. Most electronics/electrical engineers are still attracted to the software giants because of the lucrative career and complexity of the VLSI technology. Formally upskilling passionate engineers can help them to deal with VLSI comfortably. So, they will choose our industry and pursue their long-term VLSI career. The internship is more effective with our pre-onboarding training, and it reduces the duration and cost of the internship minimum of 50% for the company. Why do you still want to follow the same informal/traditional on-the-project internship/training? Is it effective?

We can dream about transforming our semiconductor industry into a trillion-dollar industry only with creative and skilled chip design engineers. We need next-gen advanced node chips to implement and support new technologies like AI, 5G, Cloud, etc., and grow our business. We need more creative and skilled engineers for the same. Are we gearing up with the next generation of skilled chip designers to design more new chips, especially working chips, and make the fabs busy?

Also Read:

Chip War without Soldiers

Maven Silicon’s RISC-V Processor IP Verification Flow

Is your career at RISK without RISC-V?

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The Efabless Generative AI Challenges and Why They Matter

The Efabless Generative AI Challenges and Why They Matter
by Daniel Nenni on 07-20-2023 at 10:00 am
Categories: Efabless, Semiconductor Services

Efabless Banner for SemiWiki

Last week, Efabless announced the second edition of its AI Generated Open-Source Silicon Design Challenge series.  As we discussed in earlier blogs, the first challenge was a great success with twelve submissions and six successful designs created in just three weeks. The contestants used natural language prompts to create Verilog and implemented their designs using the Efabless chipIgnite platform and its OpenLane open-source design flow. The first-place winner was a co-processor by Hammond Pearce at New York University; you can read the story here.  Silicon for the winners will be fabricated by Efabless and the devices are expected back at the end of October.  The second challenge has the same guidelines but the time to design is extended from three weeks to two months.

There is obviously lots of interest in Generative AI in chip design.  It promises to speed and simplify the design of chips, making custom silicon economically feasible across a previously unimaginable diversity of designs to meet the breadth of requirements for IoT and Machine Learning.  That being said, there are still lots of questions.  Are the data sets large enough to enable the LLM models required?  How will verification be done to the appropriate levels of completeness?  How will people learn and adapt to this new approach?  Will the chips work?  Will people actually trust that they do work?

Efabless plans to address these concerns and accelerate the emergence of the new world.  They      believe that the key is to engage the maximum number of potential users to drive the maximum number of designs, enable collaboration and sharing of experiences and designs and, last but far from least, to provide a full path to manufacturing because “the proof is always in the pudding.”  The answer lies in open source and community models, an approach that Efabless has proven over the past several years.

Here is how:

Open Source is fundamental.  By putting prompts and designs in the public domain they can be studied by others and used as starting points for future designs.  In short order a vast array of examples will be created to expand the potential data sets.  The use of the open source design flows and the automation offered by Efabless expands the number of potential designers (and therefore the number of designs) by lowering barriers to entry.

Community engagement adds to the success.  It was remarkable how contestants openly collaborated in the first challenge, sharing their learnings in both design and verification.  As the number of contestants grows it stands to reason that the collective insights will grow exponentially with it.

Prototyping is key. Last but not least, Efabless has addressed the last mile to manufacturing, making it both fast and affordable at scale.  This enables attractive incentives for people to participate in the journey and very importantly it rapidly closes the loop to show which prompts, methods and, ultimately, AI generated designs are most effective.

Mike Wishart, CEO, has described the very logical fit of generative AI with Efabless and its mission to simplify design and open it to everyone.  It now seems that Efabless will be a key enabler in accelerating its adoption.

Also Read:

Efabless Celebrates AI Design Challenge Winners!

Why Generative AI for Chip Design is a Game Changer

A User View of Efabless Platform: Interview with Matt Venn

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Reducing Electronic Systems Design Complexity with AI

Reducing Electronic Systems Design Complexity with AI
by Kalar Rajendiran on 07-20-2023 at 6:00 am
Categories: AI, EDA, Siemens EDA

Siemens Reducing Complexity with AI Whitepaper Graphics

 

In the world of electronic systems design, complexity has always been a major challenge. As technology advances and demands for more efficient and powerful electronic devices grow, engineers face increasingly intricate design requirements. These complexities often lead to longer design cycles, increased costs, and potential design flaws. Siemens EDA recognizes the urgent need for innovative solutions to overcome these obstacles. The company has identified artificial intelligence (AI) as a technology that could offer tremendous leverage for innovation. AI encompasses computational technologies that enable machines to reason and infer without human intervention. AI solutions can analyze large volumes of data to identify patterns and trends, improving processes and providing recommendations for better decision-making.

Siemens EDA has been making significant investments in AI technologies and applying them to various product areas, including PCB design, autonomous driving systems, smart factory floor management and smart city management. The company recently published a whitepaper that delves into how the application of AI technology can address the challenges in printed circuit board (PCB) design.

Challenges in PCB Design

PCB electronic systems engineers face challenges in designing complex, fast ICs that require adequate power, cooling, signal integrity, and thermal integrity. They must deliver high-performance PCBs and interconnected electronic systems within shrinking time-to-market windows while minimizing power consumption. Understanding PCB design and EDA tools involves a steep learning curve and engineers often learn on the job. Component selection is another challenge that requires extensive research and analysis of datasheets.

Leveraging AI

AI can mine completed designs to identify patterns and guide designers to the next logical step, improving design quality and efficiency. AI can develop models based on historical information to recommend viable component options, speeding up the selection process. Integrate this with real-time visibility into component supply chain and it turns into a powerful capability.

The ultimate goal of AI-driven electronic design is for AI algorithms to generate PCB designs and manufacturing outputs, reducing design time and eliminating costly mistakes.

Generative Design

Generative design is an innovative approach that uses algorithms and computational methods to automatically generate and optimize design solutions based on specified parameters and constraints. It combines the power of artificial intelligence, machine learning (ML), deep learning (DL) and advanced simulation techniques to explore a vast design space and produce optimized and efficient designs.

Benefits of Leveraging AI in Electronic Systems Design

Generating component models, such as symbols, physical geometries, and simulation models, is time-consuming. AI technologies like natural language processing and image recognition can automatically process datasheets and generate the required models, reducing manual effort and leveraging domain knowledge.

Schematic connectivity, establishing connections between components, is another manual task. ML models trained on completed designs can recommend components and suggest pin-to-pin connections, accelerating the design process.

Dynamic reuse of functional blocks and intelligent database management can be achieved by training DL models, enabling design tools to predict potential functions of blocks and suggest reusable placement and routing options.

Constraints, such as layout, high-speed design, manufacturing, and test rules, are usually entered manually, posing a risk of errors. AI can recommend constraint sets and values based on the current design and knowledge from released designs, streamlining the process.

Layout tasks like component placement and routing are time-consuming. AI systems can recommend placement and routing strategies based on completed designs, and advanced routing methodologies like sketch routing can be applied. Auto routing and analysis tools can also benefit from AI/ML algorithms to generate optimal routes and perform accurate simulations.

Summary

AI is increasingly important in enhancing operational productivity and user expertise. In PCB design, AI is particularly valuable in automating manual processes and enabling entry-level users to perform tasks that previously required expert knowledge. By leveraging AI technologies, decision-making can be accelerated, mundane processes can be automated, new users can work more efficiently, and the performance and manufacturability of multi-domain systems can be optimized.

As part of the Siemens Xcelerator portfolio, AI-driven tools enable electronic systems design companies to leverage AI technologies and bring futuristic products to market. Siemens continually identifies new use cases where AI can be applied to improve design tools and invests time and resources in enhancing existing algorithms or developing innovative methodologies to address challenges.

This whitepaper is a valuable read for everyone involved in the electronic systems design process.

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Has Electronics Bottomed?

Has Electronics Bottomed?
by Bill Jewell on 07-19-2023 at 6:00 pm
Categories: Semiconductor Intelligence, Semiconductor Services
3 Comments

Electronics Bottomed 2023 1

The current slump in the electronics market began in 2021. Smartphone shipments versus a year earlier turned negative in 3Q 2021. The smartphone market declines in 2020 were primarily due to COVID-19 related production cutbacks. The current smartphone decline is due to weak demand. According to IDC, smartphone shipments were 269 million units in 1Q 2023, the lowest level in almost ten years since 262 million units were shipped in 3Q 2013. In its June forecast, IDC projected smartphone unit shipments will drop 3% in 2023. However, we could have reached the bottom of the decline. IDC estimated 1Q 2023 smartphones were down 14.5% from a year earlier, following an 18.3% year-on-year decline in 4Q 2022. IDC 2Q 2023 estimates are not yet available, but Canalys puts 2Q 2023 smartphones down 11% from a year ago. This could signify the bottoming of the downturn and the beginning of a recovery. Smartphones could show positive year-to-year growth by 4Q 2023.

PCs experienced a COVID-19 related boom in 2020 after years of flat to declining shipments. After peaking at 57% in 1Q 2021, PC shipment year-to-year change has steadily declined, hitting a low of minus 29% in 1Q 2023. IDC’s estimate of 56.9 million PCs shipped in 1Q 2023 is the lowest since 54.1 million PCs were shipped in 1Q 2020. IDC’s 2Q 2023 estimates indicate the beginning of a recovery, with PCs down 13% from a year ago versus down 29% in 1Q 2023. 2Q 2023 PC shipments were up 8.3% from 1Q 2023, the strongest quarter-to-quarter growth since 10% in 4Q 2020. IDC’s June PC forecast was a 14% decline in 2023. The second half of 2023 would need to grow 12% from the first half to meet the 14% decline for the year. This scenario seems reasonable since it would only require about 5% to 6% quarter-to-quarter growth. PCs could return to positive year-to-year change by 4Q 2023 or 1Q 2024.

China is the world’s largest producer of electronics – including TVs, mobile phones and PCs. China production data shows a turn towards improvement. Three-month-average unit production versus a year ago for May 2023 shows color TVs up 8% after negative change in the first quarter of 2023. Mobile phones were down 3.3%, an improvement from double-digit declines in January and February 2023. PCs were still weak with a 17% decline but improved from 20% plus declines earlier in 2023. Total China electronics production in local currency (yuan) was positive in May with a 1.0% three-month-average change versus a year ago. Electronics change had been negative in the first three months of 2023.

Electronics production data for other significant countries in Asia show differing trends. Japan bounced back from a weak 2022 to show three-month-average change versus a year ago of 8.4% in April 2023. In contrast, Taiwan experienced strong growth in 2022, but slowed to 5.1% in April 2023. Vietnam also showed strong growth in 2022 but turned negative in February 2023. Vietnam was down 10.8% in May 2023, but improved slightly to a 7.8% decline in June. South Korea electronics production has been volatile, experiencing double-digit growth in late 2022, but falling to a 12.4% decline in May.

Electronics production for the 27 nations of the European Union (EU) and for the United States has been on a deceleration trend in the last several months. U.S. three-month-average change versus a year ago peaked at 8.1% in November 2022 and has decelerated each month since, reaching 2.8% in April 2023. EU 27 production growth peaked at 22% in October 2022 and has since slowed to 4.2% in April 2023. UK production growth is down from its peak of 17% in October 2022, but has held in the 8% to 11% range for the first five months of 2023.

A near-term turnaround in the electronics markets is far from certain. Global economies are expected to be generally weak in the second half of 2023. Trading Economics projects U.S. GDP growth will slow from 2.0% in 1Q 2023 and 1.9% in 2Q to a 0.1% decline in 3Q before bouncing back to a modest 0.6% growth in 4Q. The Euro area and the UK are expected to have relatively low GDP growth in the last half of 2023 ranging from 0.1% to 0.4%. China is forecast to have lower GDP growth in the second half of 2023 compared to the first half. Japan’s second half 2023 should be slightly lower than in the first half.

The good news is we have probably reached the low point in the electronics downturn. However, the recovery could be slow. A significant return to growth may not happen before 2024.

Semiconductor Intelligence is a consulting firm providing market analysis, market insights and company analysis for anyone involved in the semiconductor industry – manufacturers, designers, foundries, suppliers, users or investors. Please contact me if you would like further information.

Bill Jewell
Semiconductor Intelligence, LLC
billjewell@sc-iq.com

Also Read:

Semiconductor CapEx down in 2023

Steep Decline in 1Q 2023

Electronics Production in Decline

 

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WEBINAR: Driving Golden Specification-Based IP/SoC Development

WEBINAR: Driving Golden Specification-Based IP/SoC Development
by Daniel Nenni on 07-19-2023 at 10:00 am
Categories: Agnisys, EDA, Events

Correct By ConstructionGoldenSpec BasedIP SoCDevelopment

The ever-increasing demands placed on Intellectual Property (IP) and System-on-Chip (SoC) development teams have resulted in an ever-increasing need for automation solutions that can boost productivity without contributing to further risk. Certainly, demands for automation have long been the drivers behind the growth of the EDA industry, and, in turn, the expansion of the many market segments and application spaces that EDA has come to serve. However, mounting chip complexity, in combination with demanding customers and ever-shrinking market windows, poses its own set of roadblocks to those much-needed automation solutions.

REGISTER HERE FOR THE REPLAY

Working closely with so many market makers and leading-edge startups across a wide variety of applications, Agnisys got to see, first-hand, the many challenges being faced by those development teams. This resulted in Agnisys deciding to take aim at specification automation solutions that could address those same challenges. We asked ourselves what could be done to generate the required files for design, software, verification, validation, and documentation for semiconductor development directly from executable specifications.

Due to the ubiquity of registers in chips, and partly to their sheer numbers, Agnisys focused on the automation of register design, verification, programming, validation, and documentation. It was uncommon for a hardware software interface (HSI) to define thousands to millions of registers, with a correspondingly large API to access them. Consequently, the process of manually designing and programming all these registers came to prove daunting.

To eliminate that excessive burden, specification automation just made sense. If you could specify your registers using an unambiguous, executable format, then it would be possible to automatically generate all sorts of files for everyone on your project team. And when the specification changes, as is always the case, the files for each team member can be regenerated to reflect those inevitable changes.

No doubt many of you may have already developed a do-it-yourself (DIY) register automation solution. With standard formats such as SystemRDL, it can certainly seem easy enough to write a script or program to read the specification and generate the register-transfer-level (RTL) design code. But the real-world application of DIY solutions seldom works to plan.

By focusing both certified and standards-compliant specification automation on the problem, much can be done to improve and accelerate productivity. And, with front-end automation advances that encompass an innovative register information management system to capture hardware functionality and an addressable register map in a single “executable” specification, it is now possible for downstream code and documentation for the addressable registers, sequences, and interrupts to be generated from the single specification. Add to this design process the elimination of the inherent specification inefficiencies, and you can not only reduce the high costs of design, but you can also improve quality and time to market.

Taking the wish lists of our customers, we developed specification automation solutions that can quickly and efficiently create correct-by-construction reusable designs. Not only can our user quickly and comprehensively verify registers and memories, but they can also swiftly generate device drivers, as well as automatically generate derived documentation for tech-pubs, lab, internal and external customer.

And in the design process, inefficiencies can be eliminated. Errors can be prevented from entering the system by giving appropriate error messages in the specification itself. Users can carefully manage register information – and any inevitable changes – throughout the design process, thereby increasing productivity for the entire development team with auto generation of register database information delivered in the formats desired by the various teams. Ultimately, design costs are reduced by reducing iterations that are the result of a lack of accurate communication between various teams.

REGISTER HERE FOR THE REPLAY

Also Read:

The Inconvenient Truth of Clock Domain Crossings

Can We Auto-Generate Complete RTL, SVA, UVM Testbench, C/C++ Driver Code, and Documentation for Entire IP Blocks?

ISO 26262: Feeling Safe in Your Self-Driving Car

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Back to Basics – Designing Out PPA Risk

Back to Basics – Designing Out PPA Risk
by Bernard Murphy on 07-19-2023 at 6:00 am
Categories: Arteris, IP

balancing rocks

I wrote earlier about managing service-level risk in SoC design, since the minimum service level a system can guarantee under realistic traffic is critical to OEM guarantees of dependable system performance. An ABS design which might get bogged down in traffic under only 0.1% of scenarios is of no use to anyone. That said, meeting target PPA goals remains a core benchmark for successful designs. PPA is still, presuming an architectural design and IP which should be able to meet those goals, a primary source of risk for high-complexity SoC designs in advanced processes.

The reason is simple to understand. Advanced designs depend on advanced architectures with high levels of parallelism connecting many cores through a very complex web of communication interconnect. That interconnect contributes 12% or more of the area to the design, it contributes important power consumption over and above contributions from the cores and, since it spans across what are typically very large chips, efficient design is critical to performance. PPA goals are dependent on system design, functional design and physical floorplan, and they can’t be guaranteed securely without balancing all three together.

It all hinges on a floorplan

It’s difficult to consider floorplan constraints without a floorplan. Fortunately, some sense of how major functions should layout in the design should be available as early as product planning, even if it is only a hand sketch. Blocks from that sketch can be placed as physical constraints to guide a NoC design planning tool.

This will allow you to evaluate topologies (a tree in the example above), NoC component placement, and resource utilization within the available area. By visualizing the NoC design within the floorplan, you can identify areas of underutilization or excessive resource allocation. This insight helps in optimizing area utilization, reducing unnecessary resource duplication, and improving overall area efficiency.

Planning in this view also allows for approximate delay estimation through routes, in turn enabling you to plan latency minimization along latency critical paths or to add pipelining in paths that can handle increased latency. At the same time, you can weigh tradeoffs between bandwidth and network link widths. A wide link will support higher bandwidth but may increase congestion in that area, which should be readily apparent in an elaborated view of the plan.

Other options you might also consider to minimize area/congestion are compression/decompression (handled at initiators/targets) and traffic multiplexing through long-routes. You still provide mechanisms for these methods; the floorplan view helps highlight the need to make those choices as you are architecting the NoC.

Later in the design schedule, when a more complete floorplan is available, these options can be fine-tuned to optimize to that floorplan. Given the early optimization defined above, this really will be fine-tuning rather than a NoC rip-up and redesign that might be possible if the first design proves insufficiently flexible to adapt to the floorplan.

A very nice advantage of NoC architectures over crossbar structures is that they can be internally controlled for dynamic and static power, just as you can control other logic in the design. Clock gating is an option of course, but in the context of this topic, it is also worth considering power gating and voltage scaling options (commonly late-stage optimizations in this case). Taking advantage of these options depends on access to power/voltage domains, necessarily localized in the floorplan. You should have information about domain support for function blocks (CPUs, GPUs, etc.), suggesting possibilities for domain support in nearby NoC elements.

Design out PPA risk or hope for the best?

Interconnect design in complex SoCs built in advanced processes can be a significant contributor to PPA risk and, therefore, to missing target specs or design schedules. This risk is very much a factor of the close coupling between architecture, microarchitecture and implementation in today’s advanced designs.

That risk is very manageable when considering interconnect design within the context of the SoC floorplan, estimated initially and later refined. Check out Arteris IP’s FlexNoC 5 to get more details on how you can remove risk from your SoC designs.