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Ecomotion: Engendering Change in Transportation

Ecomotion: Engendering Change in Transportation
by Roger C. Lanctot on 06-05-2022 at 6:00 am
Categories: Automotive
1 Comment

Engendering Change in Transportation

Prioritizing gender-related behavior in the analysis of transportation patterns may change planning priorities and accelerate a transition to more sustainable mobility solutions. That is the finding of a report compiled by the Ministry of Environmental Protection in Tel Aviv, Israel and shared at the Women in Mobility summit as part of Ecomotion Week.

Speaking at the Tel Aviv summit, Tamar Keinan, of the Department of Economics of Bar Ilan University, described important differences between male and female transportation behaviors as identified from studies conducted in Israel and globally. Focusing on issues ranging from vehicle ownership, to driving styles, and the use of micromobility and public transit, Keinan shared surprising insights suggesting that women may serve as an important fulcrum for evolving transportation toward a more sustainable future.

Among the findings shared by Keinan were:

  • Men are more dependent on the use of privately owned vehicles and tend to travel continuously for long distances
  • Women tend to make multiple stops when driving a privately owned vehicle and prioritize slower and less expensive means of travel over cars
  • Men are more secure when traveling
  • Men are more likely to ride a bicycle
  • Men have a low awareness of environmental concerns and are less inclined to prioritize sustainability
  • Men are more inclined to work further from home
  • Women report a higher degree of satisfaction with public transportation
  • Private car ownership by men is 1.5x greater than women for most age groups
  • Men account for three quarters of employer-provided vehicles

The findings point to differences in transportation behaviors that are important enough to influence decision making. In fact, the studies suggest that ongoing analysis of this nature ought to be prioritized to foster a deeper understanding of transportation client behaviors in order to create policies intended to influence user decision making to achieve preferred outcomes.

The report concludes:

  • Improving public transportation is a tool for achieving greater gender equality
  • There is a lack of continuous information gathering to allow the measurement of gaps in transportation service delivery
  • Female transportation patterns are not necessarily tied to the upbringing of children
  • There is a need to redefine the peak and low hours of public transportation demand
  • Women may play an essential role as change agents for achieving greater sustainability

The report suggests action items for transportation authorities:

  • An expansion and improvement of public transportation including gender-specific marketing
  • Road signs depicting both male and female figures
  • The encouragement of “collaborative” travel
  • More frequent travel behavior studies

The report also had recommendations for parents of daughters:

  • Do not drive your daughters to school. Help them plan the safe way. Do not get them used to being passengers, next to the driver.
  • Encourage them to ride a bike at a young age.
  • Set a personal example, maintain gender balances in family transportation
  • Experience public transportation, walking, and cycling

And recommendations for statisticians:

  • Recognize the importance of differences in estimating satisfaction with public transportation among frequent users
  • Recognize that sharing information helps reduce gender gaps in transportation
  • Collect and analyze gender data regarding toll roads and vehicles from the workplace

And for municipal authorities:

  • Create short walking distances
  • Foster the use of multiple transportation modes
  • Provide safe and continuous bike paths to help increase the percentage of female riders
  • Strengthen the sense of security in the public space to foster the independent mobility of women

The transportation priorities and concerns of women are better aligned with societal sustainability goals – relative to the behaviors and preferences of men. By better addressing the transportation needs of women, municipalities and public authorities generally can accelerate their simultaneous progress toward transportation equity and ecologic and economic responsibility.

While the individual study findings seem deceptively obvious in some cases, the powerful implications are worthy of note. Women can serve as global change agents for achieving unmet global mobility goals.

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Podcast EP83: The ESD Alliance and SEMI – Mission and Strategy with Bob Smith

Podcast EP83: The ESD Alliance and SEMI – Mission and Strategy with Bob Smith
by Daniel Nenni on 06-03-2022 at 10:00 am

Dan is joined by Bob Smith, executive director of the ESD Alliance, a SEMI technology community. The ESD Alliance represents the electronic system and semiconductor design ecosystems. It is the first design-oriented community in SEMI.

Bob explores the mission of the ESD Alliance and how the organization leverages the worldwide footprint of SEMI. Security, software piracy, encryption and tracking worldwide events impacting the design and manufacturing ecosystems are some of the topics Dan and Bob discuss in this far-reaching and informative podcast.

The views, thoughts, and opinions expressed in these podcasts belong solely to the speaker, and not to the speaker’s employer, organization, committee or any other group or individual.

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Leveraging Simulation to Accelerate the Design of Plasma Reactors for Semiconductor Etching Processes

Leveraging Simulation to Accelerate the Design of Plasma Reactors for Semiconductor Etching Processes
by Kalar Rajendiran on 06-03-2022 at 6:00 am
Categories: Dassault Systemes, EDA, Events

Etching Processes

There is no shortage of reporting on the many technological advances happening within the semiconductor industry. But sometimes it feels like we hear less in the area of semiconductor manufacturing equipment than in the design and product arenas. That doesn’t mean that there is less happening there or what is happening there is of any less value. In fact, the advances or hurdles thereof determine the course of the entire semiconductor industry.

The never ending push for packing more transistors into a sq.mm area of a wafer continues to drive the need for reducing feature sizes. Advanced manufacturing technology is what makes these finer and finer feature sizes possible. Naturally, advanced manufacturing equipment are needed to produce these advanced chips. With many more end-markets creating demands for advanced process-based chips than ever before, wafer fab equipment sales are growing rapidly. According to SEMI, worldwide sales of semiconductor manufacturing equipment in 2021 rose 44% to an all-time record of $102.6 billion.

While fab equipment vendors see huge market opportunities, they also have to address many challenges to deliver cost-effective equipment optimized for mass production use. I recently conversed with Richard Cousin, an Industry Process Expert in Electromagnetics within the SIMULIA Brand line of Dassault Systèmes, headquartered in France. Richard is currently leading the Charged Particle Dynamics driven products and has a strong expertise on vacuum electron devices and plasma physics. The conversation focused on the etching process, which is one of the many steps involved in the manufacture of semiconductor chips. Richard discussed the challenges with the etching process, the designing of advanced plasma reactors and the plasma reactor device workflow. And he closed the conversation with a teaser of how simulation tools at the Fabrication process level can help address the plasma reactor design challenges. This article is a summary of that conversation. For those interested in learning more specifics about the simulation tools, you may want to register for a June 8th Webinar. In that webinar, Richard will dive into the details of simulation and optimization techniques that designers of semiconductor manufacturing equipment will find useful.

Etching Process: Wet vs Dry

The wet etching process is commonly used for isotropic etching whereas the dry etching process allows anisotropic etching as well as isotropic etching. While the wet etching process is still in use, the chemical reactions can cause issues when radicals are expanded over the device.

With the dry etching process using the Argon neutral gas, there are no chemical reactions. The process is controlled by the plasma uniformity and offers a better selectivity of the material to be etched. The resulting anisotropic etching process is well suited for small size features in the nanoscale. Also, more physical parameters can be controlled to characterize the plasma, such as the input power as well as the pressure of the neutral gas which controls the plasma density. Tuning the operating frequency is set by a so-called matching box.

Thus, the dry etching technique offers better flexibility for delivering accurate and uniform profiles well suited and more critical for small size features.

Designing a Plasma Reactor for Dry Etching

The design of a plasma reactor has to balance many different parameters to accommodate various requirements and plasma characteristics. The plasma characteristics include the density profiles, the ionization rate, the effect of the pressure and the type of gas used as well as the influence of the geometry to prevent damages. One key parameter is the matching network connected to the plasma reactors in order to maximize the input power to be transmitted to the device. This is a critical requirement to maintain the discharge and for better control of the plasma formation for the type of etching to be performed.

Referring to the Figure below, there are different types of dry etching processes that broadly fall into the IBE and RIE categories. The IBE process is a deposition process similar to a sputtering approach whereas the RIE process removes some materials from the substrate. Therefore, the pressures involved in RIEs are more important and require higher plasma densities to etch the substrates. Thus, the designing of a plasma reactor is challenging as it needs to support different types of dry etching processes.

3DS SIMULIA Space Charge Dynamics Simulation Tool

SIMULIA possesses an unique capability of calculating the space charge dynamics for predicting experimental results when no diagnostics are available. The SIMULIA approach allows for virtual prototyping which helps with designing real and new plasma reactors from the space charge dynamics computation to the appropriate RF matching network.

When simulating, SIMULIA can do a microscopic approach or a macroscopic approach. Under the microscopic approach, it uses a time-domain kinetic approach with a Poisson based Particle-In-Cell code. Several particle interactions are taken into account in a global Monte-Carlo Collision (MCC) type model. The ionization of the neutral gas, its excitation and the elastic collisions are considered simultaneously to compute the plasma kinetics.  Under its macroscopic approach, SIMULIA treats the plasma as bulk. The plasma parameters are extracted from the MCC models to feed an equivalent dispersion model. This enables it to accurately characterize the matching network (so-called matching box) connected to the plasma reactor.

The SIMULIA space charge dynamics simulation tool simulates all phases of the plasma reactor device workflow except phase 7 (Refer to Figure below).

For those interested in learning more specifics about the simulation tools, you may want to register for a June 8th Webinar.
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Fully Modeling the Semiconductor Manufacturing Process

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Flexible prototyping for validation and firmware workflows

Flexible prototyping for validation and firmware workflows
by Don Dingee on 06-02-2022 at 10:00 am
Categories: Prototyping, S2C EDA

The Prodigy S7-P19 Logic System can help speed up validation and firmware workflows

The quest for bigger FPGA-based prototyping platforms continues, in lockstep with each new generation of faster, higher capacity FPGAs. The arrival of the Xilinx Virtex UltraScale+ VU19P FPGA takes capacity to new levels and adds transceiver and I/O bandwidth. When these slot into S2C’s Prodigy S7-19P Logic System, the result is flexible ASIC and SoC prototyping for validation and firmware workflows. Let’s look at FPGA-based prototyping for these use cases.

Automated partitioning and realistic high-speed I/O for validation

Hardware teams get concerned when designs must be modified to be tested. Modifications take time and introduce the possibility for errors. FPGA-based prototyping is now mature technology. Firms like S2C have put in years of research on accurately partitioning logic into interconnected FPGAs with automated tools. Improvements in FPGA transceiver bandwidth – up to 4.5Tb/s total in the VU19P – streamline SerDes interconnects between parts for minimal latency.

With four VU19Ps, the 7th-generation Prodigy S7-19PQ can take on ASIC and SoC designs of up to 196M gates. Teams can scale down with smaller configurations using one or two VU19P FPGAs or scale up by stacking systems and interconnecting logic modules. All interconnects between FPGAs use the same high-speed transceivers, so stacking is as simple as cabling. On-board DDR4 memory keeps the FPGAs fed at speed. Advanced clock management keeps both standalone and multi-system configurations in sync.

During system validation, realistic high-speed I/O for stimulus and output evaluation is a requirement. Often, the burden on teams to create their own I/O testing hardware, S2C has standardized its I/O and created over 90 daughtercards with pre-tested, proven designs. I/O voltages are adjustable in software with steps from 1.2V to 1.8V. Using the same interface, teams can turn to S2C or design their own if a full-custom I/O card is required.

Instead of leaving validation to the very end of the project, and perhaps getting surprised, teams can move to a more continuous validation workflow using FPGA-based prototyping. This also allows room for expanding validation testing, since it’s not compressed into a small window. System-level faults can be exposed earlier and corrected in the ASIC or SoC design.

More power and control in the hands of firmware developers

One of the more powerful use cases for FPGA-based prototyping technology is firmware development for SoCs. For enhanced productivity, software teams need a dedicated system an individual developer can configure and control.

With daughter cards and cables plugged in, the Prodigy S7-19P auto detects its configuration. Designs load into the FPGAs through Ethernet, USB, JTAG, or a microSD card. Developers can kick the box when they need to remotely, powering it on or off or resetting it over Ethernet. A virtual UART allows a developer into firmware for debugging. Virtual switches and LEDs make it easy to change settings and see status remotely.

This kind of power can put software teams on their own workflow track, out of the way of ASIC or SoC hardware teams. Conflicts early in the design, when hardware is in flux and access is tight, can set software schedules behind. Without the right firmware for initializing registers across the chip, hardware progress may slow as well. Firmware developers can start code on a working configuration, reset the platform when they need to, and even reconfigure the platform from a design file stored on the network without bothering the hardware teams.

Win by speeding up surrounding validation and firmware workflows

Most semiconductor IP is thoroughly rung out before it gets into the hands of ASIC and SoC developers. And the tools for combining IP into a design and debugging it are much better. The remaining long poles in the tent are now validation and firmware workflows – and speeding those up with FPGA-based prototyping technology can be a huge win. Platforms like the S2C Prodigy S7-19 Logic System give validation and firmware teams their own environment working in parallel with hardware development. A short S2C video highlights this new platform.

Also read:

White Paper: Advanced SoC Debug with Multi-FPGA Prototyping

Prototype enables new synergy – how Artosyn helps their customers succeed

S2C’s FPGA Prototyping Solutions

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Inverse Lithography Technology – A Status Update from TSMC

Inverse Lithography Technology – A Status Update from TSMC
by Tom Dillinger on 06-02-2022 at 6:00 am
Categories: Events, Foundries, TSMC
6 Comments

ILT mask rules

“Inverse lithography technology (ILT) represents the most significant EDA advance in the last two decades.”  Danping Peng from TSMC made that assertion at the recent SPIE Advanced Lithography + Patterning Conference, in his talk entitled:  ILT for HVM:  History, Present, and Future.  This article summarizes the highlights of his insightful presentation.  Indeed, ILT has enabled improvements in the ability to print wafer-level features with improved fidelity.

ILT History

First, a brief review of the steps after design tapeout, associated with mask manufacture:

  • The mask shop applies optical proximity correction (OPC) or ILT algorithms to the mask data.
  • Mask data prep (MDP) will compose the OPC/ILT-generated data in a format suitable for the mask writer.
  • Mask writing has evolved from (an optically-based) pattern-generation shot exposure of the photoresist-coated mask blank to an e-beam based exposure. Both variable-shaped beam (VSB) and multiple-beam ask writing systems are available.  (More on this shortly.)
  • Mask inspection steps include:
    • critical dimension (CD) metrology (CD-SEM)
    • mask review using an aerial image measurement system (e.g., Zeiss AIMS)
    • mask defect repair

The mask then proceeds to the fab, where a wafer-level print will be subjected to similar steps:  CD-SEM dimensional evaluation, wafer inspection and defect analysis.

The need for mask correction algorithms is highlighted in the figure below.

As the printed dimensions on the wafer scaled with successive process nodes, the fidelity of the image – i.e., the difference between the target image and the printed wafer contour – became poor.  Corrections to the layout design data were needed.

The original approach to generating mask updates were denoted as optical proximity corrections (OPC).  Individual segments in the (rectilinear) design data were bisected at appropriate intervals, and the sub-segments were moved, typically using a rule-based algorithm.  Rectangular serifs were added at shape corners – both expanded segments at outside corners and reduced at inside corners.  (Colorful names were given to the OPC results – e.g., “hammerheads”, “dogbones”.)

Subsequently, OPC algorithms added sub-resolution assist features (SRAF) to the mask data.  These are distinct shapes from the original design, whose dimension is intentionally chosen so as not to print at the wafer photoresist resolution, but to provide the appropriate (constructive and destructive) interference due to optical diffraction at the edges of the design shapes.

As shown in the figures above and below, ILT algorithms make a fundamentally different assumption, utilizing curvilinear mask data for corrections and SRAFs.  The figure below illustrates the key differences between the edge-based nature of OPC and the pixel-based ILT algorithm.

How ILT Works

Danping used the following two figures to illustrate how ILT works.  The first figure below is a high-level flowchart, providing the comprehensive (ideal) iterative loop between mask data generation and post-etch wafer-level metrology.  (More on this full loop shortly.)

The figure below provides more detail on the ILT flow.  Two adjacent shapes are used for illustration.

A three-dimensional representation of the illumination intensity is computed.  An error function is calculated, with a weighted sum of constituent elements.  Each weight is multiplied by a factor related to the difference between the calculated print image and the wafer target across the pixel field.

The error function could include contributions from a variety of printed image characteristics:

  • nominal dimension (print-to-target difference)
  • modeled three-dimensional resist profile
  • pixel light intensity outside the target area to be suppressed
  • sensitivity to illumination dose and focus variations

Iterative optimizations are pursued to reduce the magnitude of this error function.  Note that the figure above mentions gradient-based optimization to reduce the error function calculated form a difference between a model prediction and a target – the similarities of ILT to machine learning methods are great, as Danping highlighted in the Futures portion of his talk.

Current ILT Adoption and Challenges

There have been hurdles to ILT adoption over the past two decades.  Danping reviewed these challenges, and how they are being addressed.

  • mask write time

The curvilinear (pixel-based) ILT mask data provide improved depth-of-focus over conventional OPC methods.  Yet, the corresponding data complexity results in a major increase in the e-beam shot count to write the mask, using variable size beam (VSB) technology.

Danping explained, “When ILT was first being pursued, there were no multiple beam mask writers.  As a result, it took days to expose an ILT mask with a VSB system.  Now, with multiple-beam systems, the mask write time in essentially constant, around 8 hours.” 

Note that there are “moderate constraints” applied for the ILT data generation to assist with this speed-up – e.g., minimum design rules for SRAF area/space/CD, maximum limits on the curvature of the shapes data.

  • ILT mask data generation time

“The first adoption of ILT was by memory foundries.”, Danping indicated.  “The highly repetitive nature of their layouts, with some careful crafting, results in a reduced number of repeating patterns.” 

ILT adoption for logic designs has been slower.  Danping elaborated on some of the challenges:

    • long computational runtime (“20X slower than OPC”)
    • mask data rules checking technology for curvilinear edges has lagged
    • improvements in exposure systems have improved image resolution (e.g., 193 to 193i) and dose uniformity, reducing the ILT advantages

ILT algorithms for model generation and error function + gradient computation is dominated by matrix operations.  To address the runtime challenge, ILT code has been ported to GPU-based computation resources.  This provides “a 10X speed-up over strictly CPU-based computation”, according to Danping.

To address the mask data validation challenge, the SEMI Curvilinear Task Force is working on a data representation that will serve as a standard format for model interchange.  (This is also driven by the curvilinear design layout data associated with silicon photonics structures.)  The figure below illustrates new “rule definitions” that will be part of mask data checking.

Danping provided the following observation on the market opportunity for ILT relative to improvements in exposure systems, “ILT can be used to squeeze more performance from an existing tool.”  In that sense, ILT may enable extended utilization of existing scanners.

Danping shared a forecast that “Both EUV and 193i masks will commonly incorporate curvilinear shapes in 2023.”  (Source:  eBeam Initiative)

ILT Future

Danping offered three forecasts for ILT technology.

  • adoption of deep learning techniques

As mentioned above, the ILT algorithm shares a great deal in common with the computation and optimization techniques of deep neural network methods.  The figure below illustrates how deep learning could be adopted.

“A trained deep learning model could be used to generate mask data, followed by a small number of ILT iterations.  ILT mask data could be derived in 15% of the previous runtime.”, Danping mentioned.

  • increased use of curvilinear design data

In addition to silicon photonics structures, the opportunity to use curvilinear data directly in circuit layouts at advanced process nodes may soon be adopted.  (Consider the case where metal “jumpers” are used on layer Mn+1 to change routing tracks for a long signal on layer Mn.)  The industry support for curvilinear data representation would enable this possibility, although it would also have a major impact on the entire EDA tool flow.

  • a full “inverse etch technology” (IET) flow to guide ILT

An earlier figure showed a “full loop” flow for mask data generation, incorporating post-etch results.  Rather than basing the ILT error function on computational models of the resist expose/develop profile, the generation of the cost function would be derived from the final etched material image model, as illustrated below.

(DOM:  dimension of mask;  ADI:  after photoresist develop inspection;  AEI:  after etch inspection)

Significant effort would be needed to construct the “digital twin” models for etch processes.  However, the benefits of a comprehensive mask data-to-process flow optimization would be great.

Summary

ILT will clearly expand beyond its current (memory-focused) applications.  The industry efforts to support a standard for efficient and comprehensive curvilinear data representations – for both mask and design data – will help to accelerate the corresponding EDA and fabrication equipment enablement.  As Danping put it, “It is not a question of if, but when and how many layers will use ILT.”

-chipguy

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Unlock first-time-right complex photonic integrated circuits

Unlock first-time-right complex photonic integrated circuits
by Raha Vafaei on 06-01-2022 at 10:00 am
Categories: Ansys, Inc., EDA, Events

EPDA overview

The capacity and energy efficiency challenges from the growing appetite for high-speed data along with advanced applications such as LIDAR and quantum computing are driving demand for increasingly large-scale photonic integrated circuits (PIC). With an ever-increasing number of components on a single photonic chip, manual techniques focused on the physical layout of components are becoming no longer feasible.  In electronics, where circuits range to billions of transistors, the industry owes much of its success to standardized process design kit (PDK)-centric electronic design automation (EDA) workflows. Photonics, like electronics, needs reliable, scalable, and automated PDK-centric design flows as demonstrated in this webinar from June 28th, “Design a silicon photonic ring-based WDM transceiver with EPDA”.

Automated generation of foundry compatible compact model libraries

In electronics, IC designers focus on their gate-level simulations without worrying about the in-depth complexities at the transistor-level or process compatibility of the actual physical implementation.  This separation of the logic -level design frees IC designers to focus on high level functionality and is mainly enabled thanks to reliable and consistent software tool chains that break down the complexities of large-scale system design via multiple layers of abstraction, as well as the availability of accurate model libraries provided in foundry PDKs. Photonics has been evolving along the same lines to enable scalable design from concept to a working photonic chip.

In device-level simulation, the physical geometry of the materials is defined, and its effects are simulated in multiple physical domains via compute intensive solvers. These computationally demanding simulation methods at the component level are not feasible for addressing entire photonic circuits or even single devices with large geometries. To address photonic design at large scale, abstract design methods are needed. Like the electronics industry, photonic devices at the component level are abstracted into compact models and represented as blocks that can be connected in a schematic design environment to create specific functionalities. Each building block has input and output ports with a defined behavioral response both in time and frequency domains. Today most advanced PIC designers start with a schematic that captures the targeted functionality of the overall system in terms of smaller, hierarchical compact models. The accuracy of a circuit simulation is dependent on the accuracy of the models in its building blocks which are defined based on component-level simulations, measurements from device characterization, or a combination of both.

Accurate models not only need to capture the complex interplay of underlying multiphysics effects in photonic devices but also must be manufacturable at a high yield. After all, yield is what makes a design commercially viable. Process variation is inherent to manufacturing and includes statistical correlations of individual circuit elements in addition to spatially dependent variability, all of which can significantly impact the performance of individual devices and the overall circuit. Statistical models are needed for yield analysis to account for process variability and ensure that the designs will behave as intended after fabrication.

To successfully create such models, designers require seamless multiphysics simulation workflows that enable optimization of custom components with built-in capabilities to account for manufacturing variability and ensure compatibility with a foundry process. Even with access to comprehensive multiphysics solvers and yield analysis capabilities, enabling PIC design in the face of lacking standards around generation of compact model libraries (CMLs) is still extremely challenging. Without standards, deciding what equations and parameters to use for encapsulating all the relevant phenomena of each component into its respective compact model can be a daunting task. Additionally, circuit designers want access to varying versions of foundry specific CMLs that cover a large set of comprehensive and parametrized device models. Manually generating and maintaining such libraries is an extremely challenging, cumbersome, and error-prone process which hinders engineering productivity and simply does not scale. Ansys’ Lumerical suite of products enable comprehensive multiphysics simulation of photonic components, accurate time and frequency domain simulation of PICs, automated generation of statistical photonic CMLs as well as yield analysis which in turn enable standardization of a PDK centric design flow.

Schematic-driven flows for co-designing electro-photonic circuits

The design workflow discussed so far describes how multiple optical functionalities can be combined to create photonic circuits. In real designs, photonic circuits are connected to electronic circuits and it’s their combined functionality and performance that must be optimized. Circuit simulators in electronics model signals as voltages and currents, but there are unique requirements for photonic circuit simulation methods. Optical signals carry both amplitude and phase, have a wavelength, are bi-directional and multi-mode in nature. Photonic circuit simulators must capture all these phenomena.

On the layout side, unlike the Manhattan shapes in electronics, photonic designs require support for curvilinear geometries which also creates complex design rule checking (DRC) and layout versus schematic (LVS) challenges. Ansys Lumerical and Cadence jointly developed state-of-the-art electronic-photonic design automation (EPDA) solutions that use best in class photonic and electronic tools to eliminate the design scaling limitations both in the front-end and in the back end of the design flow.

An overview of the EPDA design flow is depicted in the figure

PICs include many active opto-electronic blocks such as lasers, photodetectors and modulators that have associated electronic drivers and tunning circuits. Co-simulation of the electronic and photonic circuits captures the tight interactions between the optical and electrical domains.  Consider the electrical feedback loop comprised of monitoring photodetectors and associated TIA sub-circuits used in tuning the resonant wavelength of modulators in a ring-based transceiver design. Even though this use case doesn’t necessarily require a high-speed feedback loop, there is still continuous interaction between the detection and the tuning blocks and, given the multi-channel topologies of transceiver designs, designers would need to keep track of millions of datapoints being exchanged between optical and electrical circuit simulators.  You can learn about building compact models, curvilinear photonic layout, co-design, co-simulation, and schematic-driven layout with back-annotation in our webinar Design a silicon photonic ring-based WDM transceiver with EPDA.

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Coding Guidelines for Datapath Verification

Coding Guidelines for Datapath Verification
by Bernard Murphy on 06-01-2022 at 6:00 am
Categories: EDA, Synopsys

multiplier min

It has been an article of faith that you can’t use formal tools to validate datapath logic (math components). Formal is for control logic, not datapath, we now realize. We understood the reason – wide inputs (32-bit, 64-bit or more) fed through a multiplier deliver eye-watering state space sizes. State space explosions also happen ultimately in control logic, however there a bounded check is often sufficient to meet a coverage need. But what does coverage mean for a multiplier proof? Checking a subset of the state space isn’t good enough. The check must be exhaustive, demanding a formal-based approach. An equivalence check between RTL and a C/C++ reference model is how the VC Formal DPV app meets this objective. Of course, there are some usage guidelines for these checks. Synopsys recently released a webinar on C/C++ coding styles for datapath verification with DPV.

First understand the method

Equivalence checking here doesn’t work the same way as for RTL/gate equivalence. The C (or could be C++, I’ll just use C in what follows) is untimed and may have no obvious correspondence points with RTL other than inputs and outputs. Therefore the DPV team work with something they call transaction equivalence. Given equivalent inputs the C and RTL models will generate equivalent outputs, ignoring timing.

DPV is based on HECTOR technology first developed in the Synopsys Advanced Technology Group 20 years ago and first deployed in 2008. Over the years, DPV has evolved into a high value app in VC Formal.

Which provides a lot more freedom in software style than you would expect, if you thought this method would require SystemC. (Though it does also support SystemC datatypes.) Formal methods in software are subject to some of the same constraints for RTL, though synthesizability (in the RTL sense) is not one of them.

A few sample guidelines

A number of the guidelines are not absolute restrictions. You can view them as helpful to accelerate validation. Others, such as setting upper bounds for loops, are probably essential to ensure proofs finish in reasonable time. Here are a few examples:

  • In C modeling, simulation, debug and the execution function are often intermixed. You should separate these for equivalence checking. DPV defines a macro to aid in conditionally ignoring all that peripheral stuff, or you can just refactor to present the checker with an unmixed function.
  • Unsurprisingly you need to provide guidance on loop bounds. This is not as restrictive as you might think. You can still use while-loops or for-loops with variable upper bounds but with a mechanism to otherwise bound the loop, e.g. an exit on the loop test parameter exceeding a fixed value. DPV even supports a pragma to specify a bound.
  • There are a few other recommendations, such as writing templates with easily recognized constant sized variables, also avoiding non-portable accesses e.g. byte-wise access through char* since behavior will be different on big-endian versus little endian machines.

Want to know more?

VC Formal DPV has already been widely adopted among blue-chip semiconductor, systems and AI companies so the technology is well-proven. If you’d like to learn more about how to write efficient C/C++ code for DPV, register for the webinar.

Also read:

Very Short Reach (VSR) Connectivity for Optical Modules

Bigger, Faster and Better AI: Synopsys NPUs

The Path Towards Automation of Analog Design

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Importance of an Analytics Platform Before Migrating to the Cloud

Importance of an Analytics Platform Before Migrating to the Cloud
by Kalar Rajendiran on 05-31-2022 at 10:00 am
Categories: NetApp, Semiconductor Services

TCS NeurEDA Advisor Architecture

After many years of hesitancy to jump with both feet in, semiconductor companies are seriously considering implementing cloud strategies and making required investments. Their concern though is, how much investment is it going to take? Some of the block-and-tackle challenges they face in implementing a cloud strategy are listed below.

  • Performing a cloud candidature assessment to arrive at the best cloud strategy.
  • Identifying the best storage technology to efficiently solve the complex riddle of Hybrid cloud HPC storage.
  • Establishing an EDA harness that seamlessly manages hybrid cloud EDA workflows.
  • Laying guard rails around cloud costs and establishing mechanics to predict EDA costs of operation.

This blog will discuss the importance of leveraging an analytics platform to drive and dictate the cloud strategy and implementation. A good analytics platform such as TCS NeurEDA™ can help match workloads with existing compute resources and deliver more without additional infrastructure investments. Subsequent blogs  will focus on each of the above four challenges and how to cost-effectively overcome those challenges.

The demand for semiconductors has never been greater and is expected to keep increasing due to emerging technologies such as 5G, AI, Acceleration, Edge and the Internet of Things (IoT). This has sparked a new wave of innovation in the semiconductor industry and companies who can meet such ASIC/SoC needs will likely rise to the top in future markets. These growth opportunities drive a significant increase in consumption of HPC infrastructure (CAGR of approximately 17% over the next five years) at a scale that has not been seen in the past.  Much of this HPC compute demand could be attributed to EDA design workloads.

Semiconductor companies rely on ‘on-demand’ access to large HPC server farms to meet the chip design and verification processes. The engineering environments are coming under tremendous stress, owing to the increase in complexity and new chip variants getting introduced. The need to verify more complex chips is creating a need to significantly increase infrastructure investments. When faced with aggressive silicon tapeout schedules, EDA compute infrastructure is expected to support at least 1.5X of normal actual capacity. This poses several operational challenges to the team responsible for the EDA infrastructure and logistics. The situation gets more aggravated when the team is asked to support the engineering efforts for producing twice the number of chip variants. This is not the time to go through the age old process of procurement cycles for compute and storage hardware and software licenses.

When faced with a situation like this, two questions may pop up. Can one magically arrange for doing more with less? Is the cloud the magic wand that solves all scalability challenges? Harnessing and analyzing the data from existing HPC server-farms can provide deep insights that can answer these two questions. The analysis will provide a view on the workload characteristics of EDA processes for all phases from front-end runs all the way to tapeout.

Doing More With Less

TCS’ analysis of data from several EDA server-farms has provided them critical insights into evaluating the efficiencies of EDA job management and the sufficiency of existing compute resources. The insights have revealed that lack of advanced analytics on EDA operations and job management typically leads operations teams to decide on augmenting capacity as the only option. In reality, the lack of automated queue management software may be misleading one to believe that the server farms are being optimally utilized. For instance, measuring the utilization of servers as a whole as opposed to the available core hours may lead to the conclusion that EDA servers are always busy. Imagine reserving a multicore server for a single threaded job. When measured at the server utilization level, it will look like the resource is being fully utilized. However, when the utilization is granularly measured in core hours and analyzed, a different picture will emerge.

Workloads characterization is critical to identify the right kind of resources to allocate for optimizing utilization. For example, certain PDV Regression workloads may be more suitable for running on fewer core instances as these workloads are not very good at multi-core/multi-threading.

Is The Cloud The Magic Wand That Solves All Scalability Challenges?

There have been debates in the past on whether semiconductor companies could benefit from the cloud. But nowadays there is predominant belief across the industry that moving to the cloud may be a must for handling EDA workloads.

NetApp and TCS offer EDA transformational software framework to move EDA teams from scarcity of infrastructure to abundance. They offer a set of transformational strategies that could lay the path to a modern digitized EDA environment. Farming the historic server farm data, available as cluster logs, is a critical source of truth, and when analyzed in context could reveal several opportunities for improvement based on the workload characteristics. However, companies struggle to create a foundation platform that continuously collects and analyzes the data without human intervention.

TCS NeurEDA™ Advisor offers a reference architecture to create an event-driven EDA analytics platform, on which ML assisted server farm analytics models could be developed. The objective of these models is to provide actionable insights by analyzing the current utilization, server farm efficiency, barriers to developer productivity, etc. These insights are extracted from the existing infrastructure, scheduler and tool logs.

The next blog will discuss how the parameters extracted through the above framework will help perform a cloud candidature assessment to arrive at the best cloud strategy.

Also Read:

NetApp Simplifies Cloud Bursting EDA workloads

NetApp Enables Secure B2B Data Sharing for the Semiconductor Industry

NetApp’s FlexGroup Volumes – A Game Changer for EDA Workflows

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0.55 High-NA Lithography Update

0.55 High-NA Lithography Update
by Tom Dillinger on 05-31-2022 at 6:00 am
Categories: Events, Foundries, Intel Foundry
4 Comments

mask infrastructure 0 55

At the recent SPIE Advanced Lithography + Patterning Conference, Mark Phillips from Intel gave an insightful update on the status of the introduction of the 0.55 high numerical aperture extreme ultraviolet lithography technology.  Mark went so far as to assert that the development progress toward high-NA EUV would support production deployment in 2025. This article summarizes the highlights of Mark’s presentation, including a forecast beyond the 0.55NA generation.

The high numerical aperture system with the 13.5nm wavelength source will enable the improved resolution required for sub-13nm half-pitch exposure, as well as greater image contrast for better printed line uniformity.  (The resolution of an optical system is inversely proportional to the NA.)  The resolution for high-NA EUV litho is often quoted as “13nm to 8nm half-pitch”. 

Parenthetically, Mark described the transition to production high-NA lithography in 2025, as depicted in the ASML tool roadmap figure below.  Intel has been actively collaborating with ASML, as will be discussed shortly.  Yet, Mark did not cover topics that are commonly of interest to SemiWiki reads – e.g., a forecast for the number of high-NA EX:5000 systems to be released by ASML, the number of mask layers transitioning to 0.55NA, etc.

(The footnotes in the figure above next to system releases indicate that the initial wafer-per-hour specifications may start at a dose of 20mJ/cm**2 (250W), expanding to 30mJ/cm**2 (500W) in subsequent product updates.)

History

Mark began the presentation with a review of the introduction of the 0.33NA EUV technology.  He recounted the difficulties in achieving target source power and availability in the development cycle for first-generation systems in the 2014-2017 timeframe.  The figure below depicts the system uptime (blue), downtime (red), and 4-week rolling average (green) in the Q4 2014 to Q1 2015 interval.

Wafer cost assessments reflected the increased tool cost, mask cost, and the throughput impact of the 0.33NA transition.

“Pitch division lithography (multi-patterning) at 193i was working well.”, Mark indicated.  “The lithography infrastructure needed in conjunction with the EUV transition was not fully available.  The compelling reason to move to 0.33NA EUV was the impact of pitch division on the edge placement error (EPE).  The overlay alignment complexity with pitch division grew tremendously.”   The figure below illustrates an example of the mask alignment dependencies to which Mark referred, as an increasing number of double-pattern mask layers were used.

Mark indicated that the transition to 0.55NA EUV will be easier from a cost analysis perspective, when addressing the replacement of a dual-patterned 0.33NA layer with a single 0.55NA mask, compared to the earlier cost tradeoff when replacing 193i masks with a single 0.33NA mask, as shown below.  (More on “half-field printing” with 0.55NA shortly.)

EUV infrastructure

The discussion of EUV lithography tends to focus on the ASML scanners – yet, there is a rich and complex set of interdependent technologies that need to accompany any change in the exposure system:

  • resists
    • dose sensitivity, viscosity, coat uniformity vs. thickness, achievable resolution, and understanding of the photon/ion/electron interactions within the material upon exposure
  • mask blank quality
    • flatness, defects, coefficient of thermal expansion
  • patterned mask quality
    • defects, reflectivity/extinction of mask absorber layers
  • mask defect inspection technology – resolution and throughput
  • pellicles
    • transmissivity, uniformity, compatibility with exposure to high energy illumination, post-pellicle attach defect inspection

Mark complimented the larger lithography industry on the corresponding progress made in all these areas, with specific mention of the inspection metrology system providers.  He said, “By 2019, all of the infrastructure systems for 0.33NA EUV were ‘green’, although improvements are still needed in the transmission, uniformity, and power resiliency of pellicles.” 

The chart below from ASML illustrates the direct relationship between the pellicle transmittance and wafer throughput, with a goal of “advanced pellicle materials” in 2025 providing >94% transmission.

0.55 High-NA Transition

Mark shared the goals of upcoming process node transitions:

    • 7nm node: 18nm half-pitch
    • 5nm node: 13nm HP
    • 3nm node: 10nm HP

He then reviewed various facets of the 0.55NA infrastructure.

  • EUV EXE:5000 System

“The confidence level in the availability of the next-generation EUV scanners is high.  These systems leverage many of the existing sub-systems in the first generation NX:3000 series.”, Mark said.

The figure below illustrates the new sub-systems (in purple) for the high-NA EUV system, and the sub-systems ported from the current series.

“The projection optics is a critical, new module, to be sure.  The collaborative development between Zeiss and ASML is progressing well.”, Mark said.  (The specifications for the Zeiss mirrors in the next-gen system are pretty amazing.)

As to the requisite EUV resists, Mark indicated that there is still active development on both chemically-amplified resists (CAR) and metal-oxide resists.  “There are several optimization parameters still being evaluated, include the resist type, viscosity, thickness, and energy dose to achieve the target resolution, developed resist profile, and line edge uniformity.”, Mark indicated.

The figure below shows SEM and atomic force microscope profile results for a 0.55NA resist experiment, at 20nm spun thickness (using 0.33NA exposure).

Mark noted that moving from a resist thickness of ~37.5nm for 0.33NA process steps to the much thinner layer for 0.55NA requires detailed attention to the resist viscosity and spin process steps. (The thinner resist maintains a 2:1 aspect ratio for the resist height to width.  Note that the depth-of-field for exposure is reduced for higher NA optical systems, another consideration in the selection of the resist thickness.  Also note that thinner resists result in reduced SEM image contrast, requiring continuing development for improved, high throughput resist metrology.)

  • high-NA EUV masks

The 0.55NA systems have adopted a unique innovative optical path.  The increase in the numerical aperture of the optical field necessitated a corresponding change in the mask-to-wafer reduction for exposure.  The projection optics utilizes an anisotropic reduction factor – i.e., 4X reduction in the x-dimension and 8X in the y-dimension.  (Mark credited ASML and Zeiss with the idea for this innovation.)  Yet, as illustrated in the figure below, a traditional 6” mask dimension would not support a “full reticle” 26mm X 33mm field – the 8X demag y-range exceeds the mask height.

As a result, there will be a dual “half-field” mask exposure sequence for each high-NA EUV layer.

Mark indicated the remainder of the 0.55NA EUV mask infrastructure will be strongly leveraging the existing technologies developed for 0.33NA.  As depicted in the figure below, there is “no show stopper” in the path to production.

As an aside, Mark said, “The metrology challenges associated with the transition to (gate-all-around) RibbonFET devices far exceed those related to high-NA EUV mask inspection and measurement.” 

Timeline to Production

In a separate talk at the SPIE Advanced Lithography conference, ASML and imec indicated they are setting up a high-NA EUV system prototype facility in Veldhoven, The Netherlands, to be on-line in 2023.  The lab will allow further development of resist and methodology processes by the lab partners.

Mark indicated, “Intel will continue to partner closely with ASML, work with the high-NA researchers at this lab.  We anticipate installing a pilot tool system in Oregon in late 2023 or early 2024, with production in 2025.”

The Future – 0.7NA Systems

Mark concluded his talk with a brief discussion on future high-NA development, for even greater resolution.  (One could argue that the economic nature of Moore’s Law is under duress, but certainly not the lithographic characteristics.)

Mark posited that the next target could be:

  • 7NA
  • non-integer mask reduction optical path (e.g., 7.5X in the y-dimension, 5X in the x-dimension)
  • the emergence of new mask materials and dimensions

Mark said, “We need a very low thermal expansion material (LTEM) for mask blanks.  We will need better absorbers.  And, we will need a new ‘standard’ mask size.”  The figure below indicated how a 300mm round (775um thick substrate) could be applied.

“Using a 300mm round mask would leverage a great deal of existing subsystem experience work with these dimensions.”, Mark suggested.

Summary

Intel is collaborating with ASML for early high-NA system availability in 2024, with a production date target in 2025.  The confidence level in these dates is relatively high, due to the significant leverage of experience with 0.33NA, from re-use of scanner subsystems to major achievements in mask metrology and inspection technology.

Although significant development remains in the selection of resists and pellicles for high-NA exposure, the optical system in the new scanner is the critical path – “as it should be”, according to Mark.

The adoption of 0.55NA lithography will enable sub-13nm half-pitch critical dimensions, consistent with Intel’s process roadmap beyond the 18A node.

-chipguy

Also read:

Intel and the EUV Shortage

Can Intel Catch TSMC in 2025?

Intel Best Practices for Formal Verification

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Using EM/IR Analysis for Efinix FPGAs

Using EM/IR Analysis for Efinix FPGAs
by Daniel Payne on 05-30-2022 at 10:00 am
Categories: EDA, Events, Siemens EDA

XLR min

I’ve been following the EM/IR (Electro-Migration, IR is current and resistance) analysis market for many years now, and recently attended a presentation from Steven Chin, Sr. Director IC Engineering of Efinix, at the User2User event organized by Siemens EDA. The Tuesday presentation was in the morning at the Marriott Hotel in Santa Clara, and was in the track for the mPower and Calibre PERC tools.

Steven Chin, Efinix

Efinix

Steven started with an overview of Efinix, how they were founded in 2012, and their product is a low power and efficient FPGA, which is easier to use. Efinix is endorsed and invested by: AMD/Xilinx, Samsung, Alibaba, HKX, Henderson, AIM, and MAVCAP. Their FPGA technology is built with an array of something called an eXchangeable Logic & Routing Cell (XLR), which is used either as a logic or routing matrix. This approach was chosen to remove the traditional congestion challenge of other FPGA architectures, producing a low power, and a 4X better Power-Peformance-Area (PPA), while reaching 100% utilization ratio.

XLR cell

The XLR cell can be fabricated in any foundry process, which helps lower the costs. The first product series was Trion FPGAs, and the second generation of their technology is named Titanium FGPAs.

Design Challenges

The Titanium FGPAs use a 16nm process, and contain from 35K to 1 million Logic Elements (LE), and the design goal was to achieve the highest performance at the lowest power, while minimizing IC layout area. IP had to be integrated from many vendors, and there were multiple power domains  for core cells, analog, memory and IO.

Running EM/IR analysis was key to ensuring adequate power distribution, avoiding hotspots and increasing the silicon yields.

EM/IR Analysis Approaches

The first EM/IR vendor tool used before mPower couldn’t handle the capacity, even when using hierarchical mode. It didn’t handle multiple power domains well, and required a DSPF netlist, which limited analysis to small-sized layouts. Having to use LEF files was a pain, and on top of all that, the CPU run times were quite slow. Looking at the results to find what needed fixing in the IC layout was also tedious.

Using mPower was a big improvement for the engineering team, because they could run the entire chip analysis flat, no abstractions required, making for accurate results. mPower works with a standard Calibre flow, so no need for DSPF and LEF files at all. The power grid was analyzed using RC parasitics based on the xACT tech file. It was easy to toggle between layout and results viewing, making the debug of metal levels for IR drop a quick process.

Here’s the mPower flow used by Efinix:

mPower tool flow

mPower Usage

Starting inputs for Calibre are the schematic and layout files, and running LVS creates an SVDB file, then used as an input to mPower. Estimated power is another input, and mPower is run flat, reports are read, the failing areas are fixed, and then the tool is run until no errors are reported. Engineers liked using mPower for EM/IR analysis, because it has RVE integration, results are easy to browse, results are fast allowing iterations to complete within a day. Here’s what the GUI looks like:

mPower GUI

Run times for mPower on a full-chip Titanium FPGA was just 22 hr, 25min, while using 1.22TB of RAM. Results from a full-chip run showed hotspot tracing and that a IO power cell needed fixing with a 50mV drop. IC layout progressed, and within a week some core block issues were found and the drop was down to 37mV. After fixing the core block issues, the IR drop was reported at 13mV. While tracing the IR drop reports the team found a PLL issue with M4 not strapped properly, so they fixed that within a day.

Efinix found that they could run mPower on full-chip static IR drop analysis within a day, and that the tool found violations that were missed from manual power grid checks. RAM usage and run times have improved since using mPower in early 2021. The improved reliability of their FPGA family of devices means that fewer customer returns happen, and that helps business.

Looking Ahead

Expect ever larger devices, more IP blocks, and migration to smaller process nodes from Efinix. These bigger FPGAs will demand CPU and capacity progress for mPower. Tool users want more flexible methods to mix sources: average, PWL, DC and FSDB currents at the transistor, cell and block levels. The GUI should support the added methods. Finally, 3DIC analysis is desired.

Summary

The team at Efinix evaluated mPower in early 2021, and taped out their first product in the middle of 2021, while a second product taped out in the end of 2021. Using mPower has saved the Efinix team at least a week on every ECO iteration near tape out, because the previous flow required so much manual prep work. Having fast run times, accuracy, and memory efficiency with mPower for EM/IR analysis helped them meet project deadlines.

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