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Keynote Sneak Peek: Ansys CEO Ajei Gopal at Samsung SAFE Forum 2023

Keynote Sneak Peek: Ansys CEO Ajei Gopal at Samsung SAFE Forum 2023
by Daniel Nenni on 06-19-2023 at 10:00 am
Categories: Ansys, Inc., Chiplet, EDA, Events, Foundries, Samsung Foundry

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As one of the world’s leading chip foundries, Samsung occupies a vital position in the semiconductor value chain. The annual Samsung Advanced Foundry Ecosystem (SAFE™) Forum is a must-go event for semiconductor and electronic design automation (EDA) professionals. Ajei Gopal, President and CEO of Ansys, has the honor of delivering the opening keynote for this year’s SAFE Forum on June 28th at 10:15 a.m. in San Jose, California.

Ansys is the world leader in both system and electronic multiphysics simulation and analysis, with a strong reputation in the semiconductor market for the reliability and accuracy of its Ansys RedHawk-SC family of power integrity signoff products. Ajei’s keynote, “The 3Ps of 3D-IC,” draws from the company’s unique market position that encompasses chip, package, and board design. Leading semiconductor product designers have adopted 2.5D and 3D-IC packaging technologies that allow multiple, heterogeneous silicon die to be assembled or stacked in a small form-factor package. This provides huge advantages in performance, cost, and flexibility — but heightens analysis and design challenges, including thermal analysis, electromagnetic coupling, and mechanical stress/warpage. Samsung Foundry has been on the forefront of enabling 3D-IC with manufacturing innovations and design reference flows that include best-of-breed solutions like those offered by Ansys.

Learn how to Clear 3D-IC Hurdles

Ajei will present an executive perspective of the challenges facing multi-die chip and system designers. Ansys is a multibillion-dollar company with a deep technology background in an array of physics, from chip power integrity to thermal integrity, mechanical, fluidics, photonics, electromagnetics, acoustics, and many more. This broad portfolio gives Ansys a unique perspective of how 3D-IC technology is compressing traditional chip, package, and board design into a single, new, interlinked optimization challenge.

Ajei will explain how this new reality creates three sets of hurdles for chip design teams that threaten to slow the broader adoption of 3D-IC technology by the mainstream IC market. In response to these challenges, Ajei will present his “3Ps,”: which suggest a program of thoughtful solutions for how the design community can tackle these obstacles and move 3D-IC design toward widespread adoption.

One of the 3Ps stands for partnerships, which are key to Ansys’ successful collaboration with Samsung Foundry. It is clear to any experienced observer of the EDA market that the complexity of today’s design challenges have grown beyond the ability of any one company to solve. This is just as true for semiconductor design tools as it is for the semiconductor manufacturing equipment industry.  – No one vendor delivers all the equipment used in a fab, and no one software vendor can meet all design tool requirements. The way forward is to engage deeply with ecosystem initiatives like SAFE and ensure that customers have access to the best-in-class tools for every step of their design process.

Register for the Samsung Foundry Forum and SAFE Forum and join Ansys in fostering industry collaborations and partnerships to improve the capabilities of the semiconductor industry. Visit the Ansys booth at the SAFE exhibit (June 28 @ Signia by Hilton, San Jose, CA) to speak with EDA experts on 3D-IC design techniques and requirements.

Also Read:

WEBINAR: Revolutionizing Chip Design with 2.5D/3D-IC design technology

Chiplet Q&A with John Lee of Ansys

Multiphysics Analysis from Chip to System

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Application-Specific Lithography: 28 nm Pitch Two-Dimensional Routing

Application-Specific Lithography: 28 nm Pitch Two-Dimensional Routing
by Fred Chen on 06-19-2023 at 6:00 am
Categories: Lithography

Brightfield (red) and darkfield (purple) sidelobes in 84 nm

Current 1a-DRAM and 5/4nm foundry nodes have minimum pitches in the 28 nm pitch range. The actual 28 nm pitch patterns are one-dimensional active area fins (for both DRAM and foundry) as well as one-dimensional lower metal lines (in the case of foundry). One can imagine that, for a two-dimensional routing pattern, both horizontal and vertical lines would be present, not only at 28 nm minimum pitch, but also larger pitches, for example, 56 or 84 nm (2x or 3x minimum pitch, respectively). What are the patterning options for this case?

0.33 NA EUV

Current 0.33 NA EUV systems are unable to simultaneously image both horizontal and vertical 28 nm line pitch, as they each require incompatible illumination dipole illuminations (Figure 1). Hence, two exposures (at least) would be needed for a two-dimensional layout. In fact, even unidirectional 28 nm pitch could require double patterning [1].

Figure 1. Vertical lines require the X-dipole (blue) exclusively while the horizontal lines require the Y-dipole (orange) exclusively.
High-NA EUV

Planned high-NA (0.55 NA) EUV systems can image both horizontal and vertical 28 nm pitch lines simultaneously, but runs into a different problem for the 56 nm and 84 nm pitches. When the dipole illumination targets the 28 nm anchor pitch, the central obscuration removes the first diffraction order for the 56 nm pitch. The 56 nm pitch case essentially becomes the 28 nm pitch. Thus, it would have to be exposed separately with different illumination. The central obscuration also removes the first and second diffraction orders for the 84 nm pitch, causing sidelobes to appear in the intensity profile [2]. The sidelobes are valleys for the brightfield case, and peaks for the darkfield case (Figure 2).

Figure 2. Brightfield (red) and darkfield (purple) sidelobes in 84 nm pitch for 28 nm pitch dipole illumination with 0.55 NA. The first and second diffraction orders have been removed by the central obscuration of the pupil.

These sidelobes lead to random photon numbers crossing the printing threshold around the sidelobe locations, leading to stochastic defects (Figures 3 and 4).

Figure 3. 40 mJ/cm2 absorbed dose, 84 nm pitch, brightfield case. The dark spots in the orange space indicate locations of stochastic defects corresponding to the sidelobe valleys in Figure 2.

Figure 4. 40 mJ/cm2 absorbed dose, 84 nm pitch, darkfield case. The narrow orange lines are the result of sidelobe printing, corresponding to the sidelobe peaks in Figure 2.

Figure 4. 40 mJ/cm2 absorbed dose, 84 nm pitch, darkfield case. The narrow orange lines are the result of sidelobe printing, corresponding to the sidelobe peaks in Figure 2.

DUV immersion lithography with SAQP and selective cuts

Surprisingly, the more robust method would involve DUV lithography, when used with self-aligned quadruple patterning (SAQP) and two selective cuts [3]. This scheme, shown in Figure 5, builds on a grid-based layout scheme developed by C. Kodama et al. at Toshiba (now Kioxia) [4].

Figure 5. Flow for forming a 2D routing pattern by SAQP with two selective cuts. One cut selectively etches the covered green areas (1st spacer), while the other selectively etches the covered purple areas (core/gap). The etched areas are refilled with hardmask (dark blue). The final pattern (orange) is made by etching both the remaining green and purple areas.

Figure 5. Flow for forming a 2D routing pattern by SAQP with two selective cuts. One cut selectively etches the covered green areas (1st spacer), while the other selectively etches the covered purple areas (core/gap). The etched areas are refilled with hardmask (dark blue). The final pattern (orange) is made by etching both the remaining green and purple areas.

Of course, where available, EUV self-aligned double patterning (SADP) may also be used as an alternative to DUV SAQP, but the two selective etch exposures will still be additionally needed. While SAQP has an extra iteration of spacer (or other self-aligned) double patterning over SADP, this extra complexity is much less than the staggering infrastructure difference between EUV and DUV. Conceivably, players without EUV are still able to continue to produce chips with two-dimensional interconnecting patterns, at least down to ~25-26 nm pitch.

References

[1] D. De Simone et al., Proc. SPIE 11609, 116090Q (2021).

[2] F. Chen, Printing of Stochastic Sidelobe Peaks and Valleys in High NA EUV Lithography, https://www.youtube.com/watch?v=sb46abCx5ZY, 2023.

[3] F. Chen, Etch Pitch Doubling Requirement for Cut-Friendly Track Metal Layouts: Escaping Lithography Wavelength Dependence, https://www.linkedin.com/pulse/etch-pitch-doubling-requirement-cut-friendly-track-metal-chen/,2022.

[4] T. Ihara et al., DATE 2016.

This article first appeared in LinkedIn Pulse: Application-Specific Lithography: 28 nm Pitch Two-Dimensional Routing 

Also Read:

A Primer on EUV Lithography

SPIE 2023 – imec Preparing for High-NA EUV

Curvilinear Mask Patterning for Maximizing Lithography Capability

Reality Checks for High-NA EUV for 1.x nm Nodes

Podcast EP168: The Extreme View of Meeting Signal Integrity Challenges at Wild River Technology with Al Neves

Podcast EP168: The Extreme View of Meeting Signal Integrity Challenges at Wild River Technology with Al Neves
by Daniel Nenni on 06-16-2023 at 10:00 am

Dan is joined by Al Neves, Founder and Chief Technology Officer at Wild River Technology. Al has 30 years of experience in design and application development for semiconductor products and capital equipment focused on jitter and signal integrity. He is involved with the signal integrity community as a consultant, high-speed system-level design manager and engineer.

Dan explores signal integrity challenges of high performance design with Al. Wild River’s unique combination of process, products and skills are explained by Al, along with the motivation for the company’s approach to addressing signal integrity. It turns out success demands an all-or-nothing approach across the entire design and development process.  The best partner is an organization with the expertise and attitude to win, no matter what it takes.

The views, thoughts, and opinions expressed in these podcasts belong solely to the speaker, and not to the speaker’s employer, organization, committee or any other group or individual.

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Requirements for Multi-Die System Success

Requirements for Multi-Die System Success
by Daniel Nenni on 06-16-2023 at 6:00 am
Categories: Chiplet, EDA, Synopsys

Synopsys Chiplet Report 2023

Chiplets continue to be a hot topic on SemiWiki, conferences, white papers, webinars and one of the most active chiplet enabling vendors we work with is Synopsys. Synopsys is the #1 EDA and #1 IP company so that makes complete sense.

As you may have read, I moderated a panel on Chiplets at the last SNUG which we continue to write about. Hundreds of thousands of people around the world have read our chiplet coverage making it the #1 trending topic on SemiWiki for 2023 and I expect this to continue into 2024, absolutely.

In fact, Synopsys just released an industry insight report titled “How Quickly Will Multi-Die Systems Change Semiconductor Design?” that is well worth the read. The report also includes insights on multi-die systems from Ansys, Arm, Bosch, Google, Intel, and Samsung. Additionally, Synopsys CEO Aart de Geus wrote the opening chapter:

“As angstrom-sized transistors intersect with multi-die Si-substrates, we see classic Moore pass the baton to SysMoore,” writes de Geus. “Today, Synopsys tracks more than 100 multi-die system designs. Be it through hardware / software digital twins, multi-die connectivity IP, or AI-driven chip design, we collaborate closely with the leading SysMoore companies of tomorrow.”

Here is the report introduction:

For many decades, semiconductor design and implementation has been focused on monolithic, ever-larger and more complex single-chip implementation. This system-on-chip approach is now changing for a variety of reasons. The new frontier utilizes many chips assembled in new ways to deliver the required form-factor and performance.

Multi-die systems are paving the way for new types of semiconductor devices that fuel new products and new user experiences.

This Synopsys Industry Insight brings together a select group of keystone companies who are advancing multi-die systems. You’ll read the thoughts of senior executives from various levels of the technology stack. You’ll also hear from Synopsys’ CEO, its president and a panel of Synopsys technology experts. We’ll discuss our achievements, what lies ahead and how we are partnering with the industry to drive change.

Synopsys also recently completed an excellent webinar series on the topic which is well worth your time. You can watch this On-Demand HERE.

Synopsys Chiplet Webinar Series abstract:

The industry is moving to multi-die systems to benefit from the greater compute performance, increased functionality, and new levels of flexibility. Challenges for multi-die systems are exacerbated and require greater focus on a number of requirements such as early partitioning and thermal planning, die/package co-design, secure and robust die-to-die connectivity, reliability and health, as well as verification and system validation. Attend this webinar series to find out about some of the essential requirements that can help you overcome multi-die system challenges and make your move to multi-die systems successful.

Topics include:
  • Multi-Die System Trends, Challenges and Requirements
  • Benefits of Early Architecture Design for Multi-Die Systems
  • Innovations in Multi-Die System Co-Design and System Analysis
  • Successful Connectivity of Heterogeneous Dies with UCIe IP
  • Identifying and Overcoming Multi-Die System Verification Challenges
  • Optimizing Multi-Die System Health from Die to Package to In-Field

Bottom line: Chiplets are a disruptive technology driving the semiconductor design ecosystem without a doubt. If you want to explore chiplets in greater detail Synopsys would be a great start.

Also read:

Chiplet Interconnect Challenges and Standards

Chiplet Q&A with Henry Sheng of Synopsys

Chiplet Q&A with John Lee of Ansys

Multi-Die Systems: The Biggest Disruption in Computing for Years

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Crypto modernization timeline starting to take shape

Crypto modernization timeline starting to take shape
by Don Dingee on 06-15-2023 at 10:00 am
Categories: PQShield, Security

CNSA Suite 2.0 crypto modernization timeline

Post-quantum cryptography (PQC) might be a lower priority for many organizations, with the specter of quantum-based cracking seemingly far off. Government agencies are fully sensitized to the cracking risks and the investments needed to mitigate them and are busy laying 10-year plans for migration to quantum-safe encryption. Why such a bold step, given that experts still can’t say precisely when quantum threats will appear? PQShield has released its first installment of an e-book on PQC and crypto modernization subtitled “Where is your Cryptography?” outlining the timeline taking shape and making the case that private sector companies have more exposure than they may realize and should get moving now.

Ten crypto years is not that much time

Folks who survived the Y2K scramble may recall thinking it was far away and probably not as big a problem as all the hype projected. In retrospect, it ended up being a non-event with almost no catastrophic failures – but only because organizations took it seriously, audited their platforms, vendors, and development efforts, and proactively made fixes ahead of the deadline.

PQC has some of the same vibes, with two exceptions. There is no firm calendar date for when problems will start if not mitigated. Many of today’s platforms have crypto technology deeply embedded, and there are no fixes for quantum threats to public-key algorithms short of PQC redesign. It’s fair to say that if an organization doesn’t explicitly understand where platforms have PQC embedded, all platforms without it must be considered vulnerable. It’s also fair to say that the potential for lasting damage is high if a problem starts before a plan is in place.

That makes the NSA advisory on the Commercial National Security Algorithm Suite 2.0 (CNSA Suite 2.0) noteworthy. Released in September 2022, it identifies a crypto modernization timeline for six classes of systems with a target of having all systems PQC-enabled by 2033.

 

 

 

 

 

 

 

 

Those earlier milestones for some system classes in the timeline starting in 2025, combined with requiring new full-custom application development to incorporate PQC, shorten the ten-year horizon. PQShield puts it this way in their e-book:

“The message for [public and private sector] organizations is both clear and urgent: the time to start preparing for migration to PQC is now, and that preparation involves assessing and prioritizing an inventory of systems that use cryptography, and are candidates for migration.”

Where to start with crypto modernization

Many veterans who guided organizations through Y2K have retired – but left behind a playbook that teams can use today for crypto modernization. Initial steps involve a risk assessment looking at internally-developed and vendor-supplied systems. Mitigation strategies will vary, with some considerations including how sensitive the data a system handles is, how long that data possibly lives, and if the system is public-facing.

 

 

 

 

 

 

 

 

 

PQShield makes two vital points here. First, it may not be possible, especially for vendor-supplied systems, to make an immediate replacement. Enterprise-class system replacements need careful piloting not to disrupt operations. The good news is for most commercial application and system vendors, PQC will not be a surprise requirement.

The second point is that hybrid solutions may overlap with both PQC and pre-quantum legacy crypto running, with a containment strategy for the legacy systems. This overlap may be the case for infrastructure, where the investment will be enterprise-wide, and the priority may be protecting public-facing platforms with PQC first.

Moving to an industry-specific discussion for PQC

After discussing infrastructure concerns in detail, PQShield devotes about half of this e-book installment to industry-specific considerations for PQC. They outline ten industries – healthcare, pharmaceuticals, financial services, regulatory technology, manufacturing, defense, retail, telecommunications, logistics, and media – highlighting areas needing specific attention. The breadth of the areas discussed shows how many systems we take for granted today use cryptography and will fall vulnerable soon.

Crypto modernization is a complex topic, made more so by the prevalence of crypto features in many vendor-supplied systems organizations don’t directly control. Awareness of timelines in place, along with places to look for vulnerabilities, is a meaningful discussion.

To download a copy of the e-book, please visit the PQShield website:

Cryptography Modernization Part 1: Where is your Cryptography?

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S2C Accelerates Development Timeline of Bluetooth LE Audio SoC

S2C Accelerates Development Timeline of Bluetooth LE Audio SoC
by Daniel Nenni on 06-15-2023 at 6:00 am
Categories: EDA, Emulation, Prototyping, S2C EDA

actt

S2C has been shipping FPGA prototyping platforms for SoC verification for almost two decades, and many of its customers are developing SoCs and silicon IP for Bluetooth applications.  Prototyping Bluetooth designs before silicon has yielded improved design efficiencies through more comprehensive system validation, and by enabling hardware/software co-design prior to silicon availability.  When Bluetooth IP and SoC prototypes can be connected directly to real system hardware, running at hardware speeds, running real software prior to silicon, the resulting design efficiencies enable reduced development times, and higher quality products.

Bluetooth Low Energy (“BLE”) is a wireless communication technology that is used in a wide variety of applications including smart home devices, fitness trackers, and medical devices such as Neuralink’s Brain-Computer Interface – applications that require low-power operation, and short-range wireless connectivity between devices (up to 10 meters).  The Bluetooth protocol was originally introduced by the Bluetooth Special Interest Group (“Bluetooth SIG”) in 1998, followed by Bluetooth Low Energy (BLE) in 2009, and most recently the Bluetooth Low Energy Audio (“BLE Audio”) specification was released in 2022.  BLE Audio focuses on higher power efficiency than the classic version of Bluetooth, provides for higher audio quality than standard Bluetooth, and introduces new features – and was the largest specification development project in the history of the Bluetooth SIG.

One provider company of silicon IP and SoC design services that chose S2C’s FPGA-based prototyping solutions for their SoC verification and system validation platform was Analog Circuit Technology Inc. (“ACTT”).  ACTT was founded in 2011 and specializes in the development of low power physical IP and full SoC design services.  ACCT’s portfolio includes ultra-low power analog/mixed-signal IP, high reliability eNVM, wireless RF IP, and wired interface IP.  ACTT’s IP is widely used in 5G, Internet of Things (“IoT”), smart home, automotive, smart power, wearables, medical electronics, and industrial applications.

For one of its BLE projects, ACTT planned for a design verification and system validation platform that would take on several significant challenges;

  1. A System-level Verification platform for a BLE Audio SoC that would enable comprehensive validation of the entire system’s functionality, and would also support industry regulation compliance testing.
  2. A Hardware/Software Co-Design platform that would provide the software development team with a platform for early software development and hardware/software co-design.
  3. A Stability Testing platform – and as it turned out, several issues were surfaced by the verification platform that required highly-targeted debugging to ensure product stability and performance standards compliance.

Working together with ACCT on their BLE Audio project, ACCT selected S2C’s VU440 Prodigy Logic System prototyping hardware platform, prototyping software, and debugging tools for a comprehensive FPGA prototyping platform.  As part of their complete prototyping solutions, S2C offers a wide range of versatile daughter cards (“Prototype-Ready IP”), such as I/O expansion boards, peripheral interface boards, RF interface boards, and interconnect cables.  S2C’s Prototype-Ready IP supports prototyping interfaces for JTAG, SPI FLASH, UART, I2S, SD/MMC, and RF, with speeds of up to 60MHz.  S2C’s off-the-shelf Prototype-Ready IP enables faster time-to-prototyping, and reliable plug-and-play interconnection to S2C prototyping platforms.

ACTT’s Deputy General Manager, Mr. Yang, offered an enthusiastic retrospective of ACTT’s use of S2C’s FPGA-based prototyping platform: “During the development of our BLE Audio SoC, we effectively used S2C’s Prodigy Logic System for hardware verification and concurrent hardware/software development.  This innovative approach enabled us to complete the software SDK development well ahead of the chip product’s tape-out phase, resulting in a remarkable timesaving of approximately 2 to 3 months in our overall product development timeline.”

Through committed collaboration with customer-partners, such as ACTT, S2C has a reputation for stimulating independent innovative thinking about SoC verification, and enhancing its customers’ competitiveness in their respective markets. By working closely with its customer-partners, S2C fosters a thriving collaborative working environment that encourages the timely exchange of ideas, resources, and SoC development expertise. With a shared vision of success, S2C and its customer-partners strive to achieve successful SoC development outcomes like ACCT’s, that delivers compelling value to our customer-partners.

About S2C:

S2C is a leading global supplier of FPGA prototyping solutions for today’s innovative SoC and ASIC designs, now with the second largest share of the global prototyping market. S2C has been successfully delivering rapid SoC prototyping solutions since 2003. With over 600 customers, including 6 of the world’s top 15 semiconductor companies, our world-class engineering team and customer-centric sales team are experts at addressing our customer’s SoC and ASIC verification needs. S2C has offices and sales representatives in the US, Europe, mainland China, Hong Kong, Korea and Japan. For more information, please visit: www.s2cinc.com

Also Read:

S2C Helps Client to Achieve High-Performance Secure GPU Chip Verification

Ask Not How FPGA Prototyping Differs From Emulation – Ask How FPGA Prototyping and Emulation Can Benefit You

A faster prototyping device-under-test connection

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Semico Research Quantifies the Business Impact of Deep Data Analytics, Concludes It Accelerates SoC TTM by Six Months

Semico Research Quantifies the Business Impact of Deep Data Analytics, Concludes It Accelerates SoC TTM by Six Months
by Kalar Rajendiran on 06-14-2023 at 10:00 am
Categories: Analytics, proteanTecs

Design Costs Comparison

The semiconductor industry has been responding to increasing device complexity and performance requirements in multiple ways. To create smaller and more densely packed components, the industry is continually advancing manufacturing technology. This includes the use of new materials and processes, such as extreme ultraviolet lithography (EUV) and 3D stacking. To meet performance requirements, the industry is developing new chip architectures that enable more efficient data processing and power consumption. This includes open-domain-specific-architectures (ODSA) incorporating specialized processors and artificial intelligence (AI) accelerators. To reduce costs and improve performance, the industry is integrating more components onto a single chip, resulting in System on Chip (SoC) designs or opting for multi-die systems using chiplets-based implementations. There is also increasing levels of collaboration within the ecosystem including the equipment suppliers, foundries, package and assembly houses.

At the same time, time-to-market (TTM) is taking on more and more importance for product companies. In today’s fast evolving markets, the market window for a product may be just two years. A company cannot afford to be late to any market, let alone these kind of fast moving markets. Thus, each company utilizes its own tested and proven ways of deriving TTM advantages to get to market first. Of late, deep data analytics is being leveraged by many companies to accelerate their SoC product development efforts. By leveraging deep data analytics, design issues can be caught early in the development process, reducing the need for expensive and time-consuming re-spins. It can also identify potential performance bottlenecks and optimization opportunities. In essence, deep data analytics can not only reduce TTM but also help improve product performance, increase power efficiency and enhance reliability of a product. The product company gets to enjoy bigger market share at significantly improved return on investment (ROI) and longer term customer satisfaction.

proteanTecs is a leading provider of deep data analytics for advanced electronics monitoring. Its solution utilizes on-chip monitors and machine learning techniques to deliver actionable insights during development through production and in-field deployment. The company hosted a webinar recently where Rich Wawrzyniak, Principal Analyst for ASIC and SoC at Semico Research, presented a head-to-head comparison of two companies designing a similar multicore SoC on a 5nm technology node. One of the two companies in this comparison leveraged proteanTecs technology in its product development and gained a six-month TTM advantage over the other.

The webinar is based on a Semico Research white paper, which we covered in the article, “How Deep Data Analytics Accelerates SoC Product Development.”

Here are some excerpts from the webinar.

The Cost Edge

Below is a design costs comparison table for two competing solutions for the same application based on current industry design and production costs. Company A’s solution leveraged proteanTecs analytics-based design methodology and Company B’s solution used standard methodology. The solution is a data center accelerator SoC product, details of which are shared by Rich in the webinar. Company A’s cost savings amounted to about 9% over Company B.

The Time-to-Market (TTM) Benefit

Using proteanTecs approach for deep data analytics, Company A met their market window with on-time entry, allowing it to capture the majority of the target market. The company gained a 6-month TTM advantage over Company B. It also recovered its design investment even as their market was still growing, allowing for increased revenues and profitability.

In-Field Advantage

As highlighted in the Figure below, proteanTecs analytics solution not only helps during design, bring up and manufacturing phases but also after a product has been deployed in the field. This helped Company A monitor for and correct potential problems in the field under real world operating conditions. This kind of analytics insights could be used for preventive maintenance and fine tuning for power consumption and product performance in the field. Marc Hutner, Senior Director of Product Marketing at proteanTecs, presented this information during the webinar.

Cloud-Based Platform Demo

To conclude the webinar, Alex Burlak, Vice President, Test & Analytics at proteanTecs, showed a demo of the proteanTecs cloud-based analytics platform. He highlighted the platform’s capabilities and revealed the different types of insights users receive from proteanTecs’ on-chip monitors, also called Agents.

Summary

Anyone involved with semiconductor product development will find the information presented in the webinar very useful. You can watch the webinar on-demand here.

Also Read:

Maintaining Vehicles of the Future Using Deep Data Analytics

Webinar: The Data Revolution of Semiconductor Production

The Era of Chiplets and Heterogeneous Integration: Challenges and Emerging Solutions to Support 2.5D and 3D Advanced Packaging

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TSMC Doubles Down on Semiconductor Packaging!

TSMC Doubles Down on Semiconductor Packaging!
by Daniel Nenni on 06-14-2023 at 6:00 am
Categories: Chiplet, Foundries, TSMC
4 Comments

TSMC 3DFabric Integration

Last week TSMC announced the opening of an advanced backend fab for the expansion of the TSMC 3DFabric System Integration Technology. It’s a significant announcement as the chip packaging arms race with Intel and Samsung is heating up.

Fab 6 is TSMC’s first all-in-one advanced packaging and testing fab which is part of the increasing investment in packaging TSMC is making. The fab is ready for mass production of the TSMC SoIC packing technology. Remember, when TSMC says mass production they are talking about Apple iPhone sized mass production, not engineering samples or internal products.

Today packaging is an important part of a semiconductor foundry offering. Not only is it a chip level product differentiator, it will take foundry customer loyalty to a whole new level. This will be critical as the chiplet revolution takes hold making it much easier for customers to be foundry independent. Chiplet packaging however is very complex and will be foundry specific which is why TSMC, Intel, and Samsung are spending so much CAPEX to secure their place in the packaging business.

The TSMC 3DFabric is a comprehensive family of 3D Silicon Stacking and Advanced Packaging Technologies:

  • TSMC 3DFabric consists of a variety of advanced 3D Silicon Stacking and advanced packaging technologies to support a wide range of next-generation products:
    • On the 3D Si stacking portion, TSMC is adding a micro bump-based SoIC-P in the TSMC-SoIC®family to support more cost-sensitive applications.
    • The 2.5D CoWoS®platform enables the integration of advanced logic and high bandwidth memory for HPC applications, such as AI, machine learning, and data centers. InFO PoP and InFO-3D support mobile applications and InFO-2.5D supports HPC chiplet integration.
    • SoIC stacked chips can be integrated in InFO or CoWoS packages for ultimate system integration.
  • CoWoS Family
    • Aimed primarily for HPC applications that need to integrate advanced logic and HBM.
    • TSMC has supported more than 140CoWoS products from more than 25
    • All CoWoS solutions are growing in interposer size so they can integrate more advanced silicon chips and HBM stacks to meet higher performance requirements.
    • TSMC is developing a CoWoS solution with up to 6Xreticle-size (~5,000mm2) RDL interposer, capable of accommodating 12 stacks of HBM memory.
  • InFO Technology
    • For mobile applications, InFO PoP has been in volume production for high-end mobile since 2016 and can house larger and thicker SoC chips in smaller package form factor.
    • For HPC applications, the substrateless InFO_M supports up to 500 square mm chiplet integration for form factor-sensitive applications.
  • 3D Silicon stacking technologies
    • SoIC-P is based on 18-25μm pitch μbump stacking and is targeted for more cost-sensitive applications, like mobile, IoT, client, etc.
    • SoIC-X is based on bumpless stacking and is aimed primarily at HPC applications. Its chip-on-wafer stacking schemes feature 4.5 to 9μm bond pitch and has been in volume production on TSMC’s N7 technology for HPC applications.
    • SoIC stacked chips can be further integrated into CoWoS, InFo, or conventional flip chip packaging for customers’ final products.

“Chiplet stacking is a key technology for improving chip performance and cost-effectiveness. In response to the strong market demand for 3D IC, TSMC has completed early deployment of advanced packaging and silicon stacking technology production capacity, and offers technology leadership through the 3DFabricTM platform,” said Dr. Jun He Vice President, Operations / Advanced Packaging Technology & Service, and Quality & Reliability. “With the production capacity that meets our customers’ needs, we will unleash innovation together and become an important partner that customers trust in the long term.”

TSMC’s customer centric culture will be a big part of the chiplet packaging revolution. By working with hundreds of customers you can bet TSMC will have the most comprehensive IC packaging solutions available for fabless and systems companies around the world, absolutely.

TSMC Press Release:
TSMC Announces the Opening of Advanced Backend Fab 6, Marking a Milestone in the Expansion of 3DFabric™ System Integration Technology

Also Read:

TSMC Clarified CAPEX and Revenue for 2023!

TSMC 2023 North America Technology Symposium Overview Part 1

TSMC 2023 North America Technology Symposium Overview Part 2

TSMC 2023 North America Technology Symposium Overview Part 3

TSMC 2023 North America Technology Symposium Overview Part 4

TSMC 2023 North America Technology Symposium Overview Part 5

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The Opportunity Costs of using foundry I/O vs. high-performance custom I/O Libraries

The Opportunity Costs of using foundry I/O vs. high-performance custom I/O Libraries
by Stephen Fairbanks on 06-13-2023 at 10:00 am
Categories: Certus Semiconductor, IP

signal 2023 06 07 192908

The original vision for Certus Semiconductor in 2008 was to leverage production I/O Libraries from more significant partners, starting with Freescale, and take it to smaller external customers for licensing.  This IP was proven and validated, with an excellent silicon track record and big company support; in our minds, we thought, “What small company wouldn’t want to use it!”  A year later, we had not sold a single I/O Library license.

Instead, every customer looked at the offerings and said, “This is not much different from the foundry IP, which is free, and despite a few minor advantages, we see no benefit in licensing it.”  This could have been the end of our story and the original business model. Still, our customers were very good at pointing us toward our future business model with this final statement, “Now, if the IO had this feature or higher performance, then we would license it.”

Our vision of an IP company shifted, and we fine-tuned our core business, designing custom best-in-class, high-performance I/O libraries that meet or exceed our customer’s market needs. Custom design services and support were added to the mix, and over time our standard IP offerings grew to a significant library of leading IP.

Today we are firmly both an IP licensing company and a custom design services company. Still, the most popular I/O Libraries grow from our custom portfolio, offering features, benefits, and capabilities our customers want that do not exist anywhere else in the semiconductor industry.

When asked, “How do you compete against free IP?” about the foundry or freely available third-party I/O libraries, I respond, “Opportunity Cost.”

In economic theory, opportunity cost is the value of what you lose when choosing between two or more options. Ideally, when you decide, you feel your choice will have better results for you regardless of what you lose by not choosing the alternative.

Engineers are very good at understanding opportunity costs regarding  I/O tradeoffs when it is quantifiable.  They can quickly determine the specific benefits of a custom I/O when they consider it has lower power, freeing up their power budgets for other blocks; or smaller footprints where they can compare the cost of saved silicon area versus the licensing fees. Such metrics allow simple calculations to guide the decision to use free I/O libraries or purchase a custom I/O license.

Conversations with sales, marketing leads, and product architects are where the hidden, and many times more significant, opportunity cost discussions surrounding I/O libraries happen.  They understand the subjective benefits of a custom I/O library better than the design engineers.   For example, adding an additional I/O protocol to a bank of I/O may open a new market or industry for the product.  If by licensing a custom I/O library, you can double or triple your available market space, is that not worth it?  By choosing a free I/O library, what does the loss of that potential market cost you?

Discussing with a Marketing lead what we can do with an I/O design is always fun.  As soon as you start to mention new features or electrical interfaces that can easily be added to a set of I/O’s, you can begin to see them get excited about potential new markets, potential new customers, and new business opportunities!

One of my favorite questions is, “If you had a wish list for this product’s I/O capability, what would it include?”  There have been many situations where a program director or marketing lead begins mentioning a feature they wanted because they saw a market opportunity but didn’t think it possible.  As soon as we offer to add it in, the excitement is real!  Some of the best custom designs we have done in the past were built off of a wish list of features given to us by the customer, many times with features they didn’t think possible but also features we wouldn’t have considered adding without their input.

Personal favorites of such collaborative designs are our 12V-30V interfaces in standard 40nm and 28nm low voltage CMOS processes, with no special masks, used for MEM’s and RF products.  Additional fun examples are precision tristate-able PWM GPIOs and a specialty die-to-die low-power high-speed interface for MCMs.

Very few areas of chip design can enable new markets, and unique design socket wins, then I/O features.  I/O design flexibility and options directly impact the variety of systems and market a part can be sold into.  By allowing our team to collaborate with our customers’ marketing leads, we have been lucky to design many fascinating libraries for the industries.

At a conference in 2017, I gave a presentation titled “Fear not to Customize.”   In that presentation, I explored several examples of how I/O custom features enabled our customers to leverage new opportunities, grow their markets, and expand their design wins.  The principles of that presentation are still valid today.  The last statement is one of my favorites, “Fear not to customize, instead let your competitors fear it.”

I still stand by that belief, telling my customers always to be bold and open to discussing with us or requesting custom I/O features.  In many cases, we have already implemented that feature in a different node—the only fear they should have ar the opportunity costs of not customizing.   Product architects and marketing must dream big and consider any design requests that enable new markets and opportunities and expand product impacts on the industry, even if those features seem implausible.  We never know what unique products will come from such collaborations and dreams.

Certus Semiconductor will be present at DAC 2023, so you’ll have an opportunity to learn more about the opportunity costs of using foundry I/O versus high-performance I/O libraries.  More importantly, you’ll have the chance to brainstorm with us new ideas about how a unique I/O design could reimagine your product and your market.

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An Automated Method to Ensure Designs Are Failure-Proof in the Field

An Automated Method to Ensure Designs Are Failure-Proof in the Field
by Rob vanBlommestein on 06-13-2023 at 6:00 am
Categories: EDA, Synopsys

fusa white paper semiwiki

I don’t know about you, but when I think of mission-critical applications, I immediately think of space exploration or military operations. But in today’s world, mission-critical applications are all around us. Think about the cloud and how data is managed, analyzed, and shared to execute any number of tasks that have safety and security implications. Or in home IoT-based applications where security systems or smoke alarms should reliably operate and send alerts when something goes awry. What about your self-driving car? One failure could cause serious damage or fatality. If you look, you’ll find that mission-critical applications exist in every aspect of our lives from travel to medical to energy to manufacturing to connectivity.

SoCs are at the heart of these mission-critical applications so how do we ensure that these SoCs don’t fail in the field? How do we make sure that these designs are resilient against random hardware failures? Systematic failures are often detected and fixed during IC development and verification, but random failures in the field are unexpected and can be difficult to plan against leading to serious implications. Devices need to not only be reliable, and function properly as expected, but also resilient against random failures that can occur. Devices need to be able to either recover from these events or mitigate them.

Devices in the field also need to be built to last. Aging effects can be factored into the reliability of the design during the development phase using models, DFM, test, and simulation. However, random failures must be accounted for during the design phase. Designing in safety mechanisms or safety measures (SMs) is key to ensure mission-critical designs are not affected by random failures such as single event upsets (SEUs) during the lifespan of the device.

Adding SMs, which are generally in the form of redundancy, into a design to protect against SEUs is not a new concept – it has been around for decades. However, this effort has largely been manual. Manually inserting SMs is painstaking and error prone as physical placement constraints and routing considerations need to be accounted for to ensure that these SMs don’t have any adverse cascading effects on elements such as reset, power, or clock network signals.

Synopsys synthesis and implementation tools provide a fully automated approach to inserting the SMs to make mission-critical design much more resilient. Synthesis can automatically insert the elements while the place and route (P&R) tools will take care of the physical implementation challenges such as placement distance and routing independence of signal nets. We have drafted a white paper to describe the process of adding these SMs and analyzing and verifying that they meet requirements from RTL to GDSII. Download the white paper “An Automated Method for Adding Resiliency to Mission-Critical SoC Designs” to learn more.

An Automated Method for Adding Resiliency to Mission-Critical SoC Designs

Adding safety measures to system-on-chip (SoC) designs in the form of radiation-hardened elements or redundancy is essential in making mission-critical applications in the Aerospace and Defense (A&D), cloud, automotive, robotics, medical, and Internet-of-Things (IoT) industries more resilient against random hardware failures that occur. Designing for reliable and resilient functionality does impact semiconductor development where these safety measures have generally been inserted manually by SoC designers. Manual approaches can often lead to errors that cannot be accounted for. Synopsys has created a fully automated implementation flow to insert various types of safety mechanisms, which can result in more reliable and resilient mission-critical SoC designs.

This paper discusses the process of implementing the safety mechanisms/measures (SM) in the design to make them more resilient and analyze their effectiveness from design inception to the final product.

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