SemiWiki – Page 121 – The Open Forum for Semiconductor Professionals

July 20, 2023July 20, 2023

The Efabless Generative AI Challenges and Why They Matter

Last week, Efabless announced the second edition of its AI Generated Open-Source Silicon Design Challenge series. As we discussed in earlier blogs, the first challenge was a great success with twelve submissions and six successful designs created in just three weeks. The contestants used natural language prompts to create Verilog and implemented their designs using the Efabless chipIgnite platform and its OpenLane open-source design flow. The first-place winner was a co-processor by Hammond Pearce at New York University; you can read the story here. Silicon for the winners will be fabricated by Efabless and the devices are expected back at the end of October. The second challenge has the same guidelines but the time to design is extended from three weeks to two months.

There is obviously lots of interest in Generative AI in chip design. It promises to speed and simplify the design of chips, making custom silicon economically feasible across a previously unimaginable diversity of designs to meet the breadth of requirements for IoT and Machine Learning. That being said, there are still lots of questions. Are the data sets large enough to enable the LLM models required? How will verification be done to the appropriate levels of completeness? How will people learn and adapt to this new approach? Will the chips work? Will people actually trust that they do work?

Efabless plans to address these concerns and accelerate the emergence of the new world. They believe that the key is to engage the maximum number of potential users to drive the maximum number of designs, enable collaboration and sharing of experiences and designs and, last but far from least, to provide a full path to manufacturing because “the proof is always in the pudding.” The answer lies in open source and community models, an approach that Efabless has proven over the past several years.

Here is how:

Open Source is fundamental. By putting prompts and designs in the public domain they can be studied by others and used as starting points for future designs. In short order a vast array of examples will be created to expand the potential data sets. The use of the open source design flows and the automation offered by Efabless expands the number of potential designers (and therefore the number of designs) by lowering barriers to entry.

Community engagement adds to the success. It was remarkable how contestants openly collaborated in the first challenge, sharing their learnings in both design and verification. As the number of contestants grows it stands to reason that the collective insights will grow exponentially with it.

Prototyping is key. Last but not least, Efabless has addressed the last mile to manufacturing, making it both fast and affordable at scale. This enables attractive incentives for people to participate in the journey and very importantly it rapidly closes the loop to show which prompts, methods and, ultimately, AI generated designs are most effective.

Mike Wishart, CEO, has described the very logical fit of generative AI with Efabless and its mission to simplify design and open it to everyone. It now seems that Efabless will be a key enabler in accelerating its adoption.

Also Read:

Efabless Celebrates AI Design Challenge Winners!

Why Generative AI for Chip Design is a Game Changer

A User View of Efabless Platform: Interview with Matt Venn

July 20, 2023March 7, 2024

Reducing Electronic Systems Design Complexity with AI

Reducing Electronic Systems Design Complexity with AI
by Kalar Rajendiran on 07-20-2023 at 6:00 am
Categories: AI, EDA, Siemens EDA

Siemens Reducing Complexity with AI Whitepaper Graphics

In the world of electronic systems design, complexity has always been a major challenge. As technology advances and demands for more efficient and powerful electronic devices grow, engineers face increasingly intricate design requirements. These complexities often lead to longer design cycles, increased costs, and potential design flaws. Siemens EDA recognizes the urgent need for innovative solutions to overcome these obstacles. The company has identified artificial intelligence (AI) as a technology that could offer tremendous leverage for innovation. AI encompasses computational technologies that enable machines to reason and infer without human intervention. AI solutions can analyze large volumes of data to identify patterns and trends, improving processes and providing recommendations for better decision-making.

Siemens EDA has been making significant investments in AI technologies and applying them to various product areas, including PCB design, autonomous driving systems, smart factory floor management and smart city management. The company recently published a whitepaper that delves into how the application of AI technology can address the challenges in printed circuit board (PCB) design.

Challenges in PCB Design

PCB electronic systems engineers face challenges in designing complex, fast ICs that require adequate power, cooling, signal integrity, and thermal integrity. They must deliver high-performance PCBs and interconnected electronic systems within shrinking time-to-market windows while minimizing power consumption. Understanding PCB design and EDA tools involves a steep learning curve and engineers often learn on the job. Component selection is another challenge that requires extensive research and analysis of datasheets.

Leveraging AI

AI can mine completed designs to identify patterns and guide designers to the next logical step, improving design quality and efficiency. AI can develop models based on historical information to recommend viable component options, speeding up the selection process. Integrate this with real-time visibility into component supply chain and it turns into a powerful capability.

The ultimate goal of AI-driven electronic design is for AI algorithms to generate PCB designs and manufacturing outputs, reducing design time and eliminating costly mistakes.

Generative Design

Generative design is an innovative approach that uses algorithms and computational methods to automatically generate and optimize design solutions based on specified parameters and constraints. It combines the power of artificial intelligence, machine learning (ML), deep learning (DL) and advanced simulation techniques to explore a vast design space and produce optimized and efficient designs.

Benefits of Leveraging AI in Electronic Systems Design

Generating component models, such as symbols, physical geometries, and simulation models, is time-consuming. AI technologies like natural language processing and image recognition can automatically process datasheets and generate the required models, reducing manual effort and leveraging domain knowledge.

Schematic connectivity, establishing connections between components, is another manual task. ML models trained on completed designs can recommend components and suggest pin-to-pin connections, accelerating the design process.

Dynamic reuse of functional blocks and intelligent database management can be achieved by training DL models, enabling design tools to predict potential functions of blocks and suggest reusable placement and routing options.

Constraints, such as layout, high-speed design, manufacturing, and test rules, are usually entered manually, posing a risk of errors. AI can recommend constraint sets and values based on the current design and knowledge from released designs, streamlining the process.

Layout tasks like component placement and routing are time-consuming. AI systems can recommend placement and routing strategies based on completed designs, and advanced routing methodologies like sketch routing can be applied. Auto routing and analysis tools can also benefit from AI/ML algorithms to generate optimal routes and perform accurate simulations.

Summary

AI is increasingly important in enhancing operational productivity and user expertise. In PCB design, AI is particularly valuable in automating manual processes and enabling entry-level users to perform tasks that previously required expert knowledge. By leveraging AI technologies, decision-making can be accelerated, mundane processes can be automated, new users can work more efficiently, and the performance and manufacturability of multi-domain systems can be optimized.

As part of the Siemens Xcelerator portfolio, AI-driven tools enable electronic systems design companies to leverage AI technologies and bring futuristic products to market. Siemens continually identifies new use cases where AI can be applied to improve design tools and invests time and resources in enhancing existing algorithms or developing innovative methodologies to address challenges.

This whitepaper is a valuable read for everyone involved in the electronic systems design process.

July 19, 2023July 22, 2023

Has Electronics Bottomed?

Has Electronics Bottomed?
by Bill Jewell on 07-19-2023 at 6:00 pm
Categories: Semiconductor Intelligence, Semiconductor Services
3 Comments

The current slump in the electronics market began in 2021. Smartphone shipments versus a year earlier turned negative in 3Q 2021. The smartphone market declines in 2020 were primarily due to COVID-19 related production cutbacks. The current smartphone decline is due to weak demand. According to IDC, smartphone shipments were 269 million units in 1Q 2023, the lowest level in almost ten years since 262 million units were shipped in 3Q 2013. In its June forecast, IDC projected smartphone unit shipments will drop 3% in 2023. However, we could have reached the bottom of the decline. IDC estimated 1Q 2023 smartphones were down 14.5% from a year earlier, following an 18.3% year-on-year decline in 4Q 2022. IDC 2Q 2023 estimates are not yet available, but Canalys puts 2Q 2023 smartphones down 11% from a year ago. This could signify the bottoming of the downturn and the beginning of a recovery. Smartphones could show positive year-to-year growth by 4Q 2023.

PCs experienced a COVID-19 related boom in 2020 after years of flat to declining shipments. After peaking at 57% in 1Q 2021, PC shipment year-to-year change has steadily declined, hitting a low of minus 29% in 1Q 2023. IDC’s estimate of 56.9 million PCs shipped in 1Q 2023 is the lowest since 54.1 million PCs were shipped in 1Q 2020. IDC’s 2Q 2023 estimates indicate the beginning of a recovery, with PCs down 13% from a year ago versus down 29% in 1Q 2023. 2Q 2023 PC shipments were up 8.3% from 1Q 2023, the strongest quarter-to-quarter growth since 10% in 4Q 2020. IDC’s June PC forecast was a 14% decline in 2023. The second half of 2023 would need to grow 12% from the first half to meet the 14% decline for the year. This scenario seems reasonable since it would only require about 5% to 6% quarter-to-quarter growth. PCs could return to positive year-to-year change by 4Q 2023 or 1Q 2024.

China is the world’s largest producer of electronics – including TVs, mobile phones and PCs. China production data shows a turn towards improvement. Three-month-average unit production versus a year ago for May 2023 shows color TVs up 8% after negative change in the first quarter of 2023. Mobile phones were down 3.3%, an improvement from double-digit declines in January and February 2023. PCs were still weak with a 17% decline but improved from 20% plus declines earlier in 2023. Total China electronics production in local currency (yuan) was positive in May with a 1.0% three-month-average change versus a year ago. Electronics change had been negative in the first three months of 2023.

Electronics production data for other significant countries in Asia show differing trends. Japan bounced back from a weak 2022 to show three-month-average change versus a year ago of 8.4% in April 2023. In contrast, Taiwan experienced strong growth in 2022, but slowed to 5.1% in April 2023. Vietnam also showed strong growth in 2022 but turned negative in February 2023. Vietnam was down 10.8% in May 2023, but improved slightly to a 7.8% decline in June. South Korea electronics production has been volatile, experiencing double-digit growth in late 2022, but falling to a 12.4% decline in May.

Electronics production for the 27 nations of the European Union (EU) and for the United States has been on a deceleration trend in the last several months. U.S. three-month-average change versus a year ago peaked at 8.1% in November 2022 and has decelerated each month since, reaching 2.8% in April 2023. EU 27 production growth peaked at 22% in October 2022 and has since slowed to 4.2% in April 2023. UK production growth is down from its peak of 17% in October 2022, but has held in the 8% to 11% range for the first five months of 2023.

A near-term turnaround in the electronics markets is far from certain. Global economies are expected to be generally weak in the second half of 2023. Trading Economics projects U.S. GDP growth will slow from 2.0% in 1Q 2023 and 1.9% in 2Q to a 0.1% decline in 3Q before bouncing back to a modest 0.6% growth in 4Q. The Euro area and the UK are expected to have relatively low GDP growth in the last half of 2023 ranging from 0.1% to 0.4%. China is forecast to have lower GDP growth in the second half of 2023 compared to the first half. Japan’s second half 2023 should be slightly lower than in the first half.

The good news is we have probably reached the low point in the electronics downturn. However, the recovery could be slow. A significant return to growth may not happen before 2024.

Semiconductor Intelligence is a consulting firm providing market analysis, market insights and company analysis for anyone involved in the semiconductor industry – manufacturers, designers, foundries, suppliers, users or investors. Please contact me if you would like further information.

Bill Jewell
Semiconductor Intelligence, LLC
billjewell@sc-iq.com

Also Read:

Semiconductor CapEx down in 2023

Steep Decline in 1Q 2023

Electronics Production in Decline

July 19, 2023August 3, 2023

WEBINAR: Driving Golden Specification-Based IP/SoC Development

WEBINAR: Driving Golden Specification-Based IP/SoC Development
by Daniel Nenni on 07-19-2023 at 10:00 am
Categories: Agnisys, EDA, Events

Correct By ConstructionGoldenSpec BasedIP SoCDevelopment

The ever-increasing demands placed on Intellectual Property (IP) and System-on-Chip (SoC) development teams have resulted in an ever-increasing need for automation solutions that can boost productivity without contributing to further risk. Certainly, demands for automation have long been the drivers behind the growth of the EDA industry, and, in turn, the expansion of the many market segments and application spaces that EDA has come to serve. However, mounting chip complexity, in combination with demanding customers and ever-shrinking market windows, poses its own set of roadblocks to those much-needed automation solutions.

REGISTER HERE FOR THE REPLAY

Working closely with so many market makers and leading-edge startups across a wide variety of applications, Agnisys got to see, first-hand, the many challenges being faced by those development teams. This resulted in Agnisys deciding to take aim at specification automation solutions that could address those same challenges. We asked ourselves what could be done to generate the required files for design, software, verification, validation, and documentation for semiconductor development directly from executable specifications.

Due to the ubiquity of registers in chips, and partly to their sheer numbers, Agnisys focused on the automation of register design, verification, programming, validation, and documentation. It was uncommon for a hardware software interface (HSI) to define thousands to millions of registers, with a correspondingly large API to access them. Consequently, the process of manually designing and programming all these registers came to prove daunting.

To eliminate that excessive burden, specification automation just made sense. If you could specify your registers using an unambiguous, executable format, then it would be possible to automatically generate all sorts of files for everyone on your project team. And when the specification changes, as is always the case, the files for each team member can be regenerated to reflect those inevitable changes.

No doubt many of you may have already developed a do-it-yourself (DIY) register automation solution. With standard formats such as SystemRDL, it can certainly seem easy enough to write a script or program to read the specification and generate the register-transfer-level (RTL) design code. But the real-world application of DIY solutions seldom works to plan.

By focusing both certified and standards-compliant specification automation on the problem, much can be done to improve and accelerate productivity. And, with front-end automation advances that encompass an innovative register information management system to capture hardware functionality and an addressable register map in a single “executable” specification, it is now possible for downstream code and documentation for the addressable registers, sequences, and interrupts to be generated from the single specification. Add to this design process the elimination of the inherent specification inefficiencies, and you can not only reduce the high costs of design, but you can also improve quality and time to market.

Taking the wish lists of our customers, we developed specification automation solutions that can quickly and efficiently create correct-by-construction reusable designs. Not only can our user quickly and comprehensively verify registers and memories, but they can also swiftly generate device drivers, as well as automatically generate derived documentation for tech-pubs, lab, internal and external customer.

And in the design process, inefficiencies can be eliminated. Errors can be prevented from entering the system by giving appropriate error messages in the specification itself. Users can carefully manage register information – and any inevitable changes – throughout the design process, thereby increasing productivity for the entire development team with auto generation of register database information delivered in the formats desired by the various teams. Ultimately, design costs are reduced by reducing iterations that are the result of a lack of accurate communication between various teams.

REGISTER HERE FOR THE REPLAY

Also Read:

The Inconvenient Truth of Clock Domain Crossings

Can We Auto-Generate Complete RTL, SVA, UVM Testbench, C/C++ Driver Code, and Documentation for Entire IP Blocks?

ISO 26262: Feeling Safe in Your Self-Driving Car

July 19, 2023October 4, 2023

Back to Basics – Designing Out PPA Risk

Back to Basics – Designing Out PPA Risk
by Bernard Murphy on 07-19-2023 at 6:00 am
Categories: Arteris, IP

I wrote earlier about managing service-level risk in SoC design, since the minimum service level a system can guarantee under realistic traffic is critical to OEM guarantees of dependable system performance. An ABS design which might get bogged down in traffic under only 0.1% of scenarios is of no use to anyone. That said, meeting target PPA goals remains a core benchmark for successful designs. PPA is still, presuming an architectural design and IP which should be able to meet those goals, a primary source of risk for high-complexity SoC designs in advanced processes.

The reason is simple to understand. Advanced designs depend on advanced architectures with high levels of parallelism connecting many cores through a very complex web of communication interconnect. That interconnect contributes 12% or more of the area to the design, it contributes important power consumption over and above contributions from the cores and, since it spans across what are typically very large chips, efficient design is critical to performance. PPA goals are dependent on system design, functional design and physical floorplan, and they can’t be guaranteed securely without balancing all three together.

It all hinges on a floorplan

It’s difficult to consider floorplan constraints without a floorplan. Fortunately, some sense of how major functions should layout in the design should be available as early as product planning, even if it is only a hand sketch. Blocks from that sketch can be placed as physical constraints to guide a NoC design planning tool.

This will allow you to evaluate topologies (a tree in the example above), NoC component placement, and resource utilization within the available area. By visualizing the NoC design within the floorplan, you can identify areas of underutilization or excessive resource allocation. This insight helps in optimizing area utilization, reducing unnecessary resource duplication, and improving overall area efficiency.

Planning in this view also allows for approximate delay estimation through routes, in turn enabling you to plan latency minimization along latency critical paths or to add pipelining in paths that can handle increased latency. At the same time, you can weigh tradeoffs between bandwidth and network link widths. A wide link will support higher bandwidth but may increase congestion in that area, which should be readily apparent in an elaborated view of the plan.

Other options you might also consider to minimize area/congestion are compression/decompression (handled at initiators/targets) and traffic multiplexing through long-routes. You still provide mechanisms for these methods; the floorplan view helps highlight the need to make those choices as you are architecting the NoC.

Later in the design schedule, when a more complete floorplan is available, these options can be fine-tuned to optimize to that floorplan. Given the early optimization defined above, this really will be fine-tuning rather than a NoC rip-up and redesign that might be possible if the first design proves insufficiently flexible to adapt to the floorplan.

A very nice advantage of NoC architectures over crossbar structures is that they can be internally controlled for dynamic and static power, just as you can control other logic in the design. Clock gating is an option of course, but in the context of this topic, it is also worth considering power gating and voltage scaling options (commonly late-stage optimizations in this case). Taking advantage of these options depends on access to power/voltage domains, necessarily localized in the floorplan. You should have information about domain support for function blocks (CPUs, GPUs, etc.), suggesting possibilities for domain support in nearby NoC elements.

Design out PPA risk or hope for the best?

Interconnect design in complex SoCs built in advanced processes can be a significant contributor to PPA risk and, therefore, to missing target specs or design schedules. This risk is very much a factor of the close coupling between architecture, microarchitecture and implementation in today’s advanced designs.

That risk is very manageable when considering interconnect design within the context of the SoC floorplan, estimated initially and later refined. Check out Arteris IP’s FlexNoC 5 to get more details on how you can remove risk from your SoC designs.

July 18, 2023June 3, 2024

Points teams should consider about securing embedded systems

Points teams should consider about securing embedded systems
by Don Dingee on 07-18-2023 at 10:00 am
Categories: IoT, Secure-IC, Security

Wishful thinking once prevailed that embedded systems, especially small embedded devices, rarely needed security, and if they did, simply installing a “secure” operating system or a security chip would keep them safe. Connecting devices big and small on the Internet of Things (IoT) shattered such insular thinking by exposing the massive scale of possible exploits. Secure-IC is challenging stale design assumptions to raise awareness about securing embedded systems in a new white paper.

Risks become unbounded when all devices connect

How about a straightforward question to start the discussion: Will your new product contain electronics? Back in the day, embedded systems relied on an air gap for security. Hacking into an embedded system meant bringing a cable, or more recently, a USB thumb drive, and physically connecting to the system. If the system was behind a locked door, even better.

Expectations have changed. Even the most mundane electronic devices now often have a wireless connection to communicate with the things around them. Many homes have Wi-Fi thermostats, cameras, doorbells, TVs, soundbars, and small or large appliances. My bike computer is on Wi-Fi. People also have Bluetooth earbuds and other sensors connected to a smartphone or smartwatch, which connects to Wi-Fi or a 5G network. Late-model cars have 5G connections for services as well.

Here’s where the skeptics interject, “Yeah, but no hacker wants to spend effort getting into your bike computer – there’s nothing of value there.” Hackers go after much juicier targets like servers with personally identifiable information (PII) or financial records. That skepticism increases the risk because designers and users either overlook securing embedded systems entirely or misunderstand the implications of their vulnerabilities. Billions of connected devices drive risks to unbounded levels if security isn’t designed in from the start.

A broader case for securing embedded systems

Headlines of websites taken down by distributed denial of service (DDoS) attacks are familiar. Ever think about where the DDoS attack came from? There must be server farms or a network of laptop and desktop machines in different countries generating all that internet traffic aimed at one site, right? Not necessarily.

Enterprise network security can be complex at scale, but generally, one knows where to start. When somebody spins up an application server, they think of securing it from the outside world. A bunch of application servers may sit behind a firewall or other security appliances in an enterprise setting, again points where security is at the forefront and managed accordingly.

Securing embedded systems should start from the perspective that there is no “there.” The same embedded device can be in my home, your home, and a million other homes. If someone learns how to get into one device, they can probably get into most of them. That leads to a specific vulnerable device, like a baby monitor or a doorbell, exposing privacy in various ways. But it also leads to a broader possibility – a network of vulnerable devices used en masse can do something, like a DDoS attack. As Secure-IC puts it in their white paper:

A single system security flaw opens a path to millions of opportunities for hacking.

Hackers using a manufacturer’s device maliciously create reputational harm for the manufacturer and perhaps manufacturer liability for damages inflicted – often at no risk for the hackers if they can’t be identified. Risk also extends beyond a specific device. Anything using the same model of operating system, embedded processor, or security chip can have the same vulnerabilities if unaddressed.

Nine points to consider for embedded systems security

Designers are often not experts on securing embedded systems, and even experienced teams can run into security potholes – but there is help from firms specializing in the arena. Secure-IC discusses these and more ideas and presents nine points designers must consider before designing a device in their new white paper. Point #5 is not to be understated: security cannot be added in later; it starts when the design project starts. See more discussion on that and the other eight points by downloading a copy here:

Embedded Systems and Security

July 18, 2023July 16, 2023

Analog Circuit Migration and Optimization

Analog Circuit Migration and Optimization
by Daniel Payne on 07-18-2023 at 6:00 am
Categories: EDA, MunEDA

WiCkeD Flow, analog circuit optimization

The MunEDA User Group Meeting (MUGM) has been an annual event since 2006, and this year there were some 80 participants from many customers that attended to share their experiences and learn how to get the best EDA tool results. I’ve been able to view the presentations and archived videos, so will share some of the interesting successes in specific tool categories.

There were two presentations from engineers at ST Microelectronics on how they performed analog circuit migration and optimization with the help of design automation software. Caroline Vaganay from ST Microelectronics works in their PDK and Design Flows group, and she compared the WiCkeD tool from MunEDA for analog circuit migration versus another vendor across three internal designs.

Their criteria in comparing EDA tools for analog circuit migration were:

Specification-driven circuit optimization
Pre-defined corners, statistical corners
SPICE simulators supported
Design migration and exploration
Accuracy – confidence, local minima, feasibility
Run times
Usability
Pricing
Support

Three circuits were used in their benchmarks:

OPAMP
Voltage Reference
Bandgap

The general design flow for the WiCkeD tool is shown below:

For the OPAMP circuit designed at 0.25um they wanted to look for better trade-off options by improving Vio and Icc across all PVT corners, achieving a PGB > 20 MHz. Optimization results showed that all performance values were within specs at nominal and worst case corners, and the runtime was only 4h 5min to complete 7,455 simulations. The performance robustness improved and the total yield improved from 14% to 71% at worst case conditions.

Their second circuit to optimize was a Voltage Reference Buffer using 40nm technology, with objectives to improve current recopy across PVT corners to minimize any process variation impacts. WiCkeD was directed to change design parameters to reduce the local variation, resulting in standard deviation improvements on performance metrics:

DELTA_PC_X10 lower, 46%
DELTA_PC_X10 upper, 44%
DELTA_PC_X8, lower, 38%
DELTA_PC_X8, upper, 45.7%

Caroline’s final benchmark circuit was a Bandgap reference in 0.18um, with objectives to optimize the resistor network to get a minimum compensated curvature over the full temperature range, while showing stability and reaching PSRR, consumption and bandwidth goals.

The WiCkeD optimizer was able to meet all performance goals and DC conditions in just 8,107 simulations, taking 9h 40min of simulation time. With MunEDA tools they beat other tools by speed and accuracy, finding solutions when others couldn’t.

Schematic Porting Tool – SPT

Maxime Blattes from ST Microelectronics shared his evaluation of SPT, and their steps used to port a schematic were:

Store parameters from the source schematic
Find the corresponding devices in a mapping table
Apply a translation and rotation to the new instance
Reconnect the wire on the new pins
Apply parameters to new instances with scaling
Run update parameters procedure

Their previous flow with Cadence Virtuoso required customization that was difficult for non-CAD engineers, and required a Skill developer. The promise of a porting tool was in saving time and talent. SPT is a GUI-based tool, making it easier for engineers to use quickly for tasks like symbol mapping, property mapping, and automatically extracting a schematic. The longest part of porting before was solving the wire updating issue, now automated with SPT.

Designers that are not CAD engineers can use SPT on their own, create any needed templates quickly, and learning the tool in a short time. What took them just 30 minutes using SPT required about 2 days before using SKILL coding.

A third presentation by Matthias Sylvester of MunEDA was a demo of SPT where he ported an example schematic from 180nm to 90nm of a 3 pin to 3 pin MOS design, then a 3 pin to 4 pin MOS. His main points about SPT for schematic porting were:

SPT remembers to recalculate all properties
Uses your hierarchy
Ports between all process nodes and fabs
SPT can stretch the new schematic as needed
Connectivity is checked before and after porting
SPT was more powerful and convenient than other tools

MunEDA SPT

Summary

Analog circuit migration and optimization can be either a manual or automated process, and the WiCkeD tool from MunEDA has been used for 15 years at companies like ST Microelectronics to automate the process, producing results that are meeting specifications like area, yield, performance and robustness. Yes, analog design is still part art and part engineering, but using EDA automation tools gives your engineers better results in less time than manual methods. The Schematic Porting Tool – SPT, is a fast way to migrate any schematic between nodes and fabs.

Visit MunEDA at the 60th DAC, booth 1407 in Moscone West, July 10-12th.

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July 17, 2023March 7, 2024

Calibre’s next move – Correct-by-Construction IC Layout Optimization

Calibre’s next move – Correct-by-Construction IC Layout Optimization
by Peter Bennet on 07-17-2023 at 10:00 am
Categories: EDA, Siemens EDA

Siemens EDA’s next move in its Calibre shift left strategy is the addition of correct-by-construction IC layout optimization for the most critical emerging physical design challenges. Calibre’s new DesignEnhancer product supports both custom and digital ICs and is already in use by several leading IC design companies. It targets three problem areas: optimization of vias, power grids and faster, higher quality decoupling capacitor and filler cell insertion.

But why get a signoff and verification tool involved in implementation and how is this better than the current P&R flow solutions ?

The principle’s nothing new – Calibre’s always had some design fixing capabilities. And it’s already tightly integrated with all leading layout flows.

But the critical reason is that layout tools aren’t always that good at some of the tasks they’ve traditionally been asked to do. Whether that’s slowness in the case of filler insertion or lack of precision in what they do – since they don’t have signoff quality rule-checking – meaning either later rework or increased design margining.

This matters on today’s highly complex designs and advanced process technologies. Users noticed the costs in design cycle time, quality and performance and pushed Siemens to make the Calibre capabilities available earlier in the flow where these were superior.

Via and Power Grid Optimization – Calibre DesignEnhancer Via & Pge

The importance of via resistance in leading edge processes makes more precise via implementation important. Designers need a more accurate picture of both timing and IR drop from the initial routing step. Leaving it any later means potential over-design for timing closure and late rework for IR drop and EM issues.

But that’s not possible without signoff quality DRC decks and rule checking. Hence Calibre’s new DesignEnhancer Via that supports both signal and power grid and via optimization by integrating Calibre into the layout flow both immediately after routing and with integrated incremental optimization after design ECO routes.

Siemens show a typical via optimization from DesignEnhancer Via below:

The improved version on the right clearly has more vias.

But the optimization isn’t limited to that – we also want to use the best possible vias (and perhaps in some local cases this means fewer). Layout tools can’t always make the best decisions here and may compromise. Calibre’s signoff quality DRC means that DesignEnhancer Via can do this. And that translates to more precise timing and reduced IR drop (particularly on SoC designs) as shown below:

No one wants to get through to design signoff and find late EM and IR drop problems that a better power grid and power routing might have avoided much earlier in the flow. DesignEnhancer Pge (Power Grid Enhancer) provides optimization of already Calibre clean power routing for both interconnect wiring and vias so that a more precise power grid can be used from much earlier in the implementation flow.

This example shows the potential for inserting further power routing and reducing IR drop.

Again, results can show dramatic reductions in IR drop.

Better Filler and Decap insertion run time and quality – DesignEnhancer Pvr

Inserting filler, decap and ECO cells has long been a painfully slow part of the P&R flow. But Calibre has always been able to insert these cells far more quickly and with more precise user control. Design Enhancer Pvr now shifts that capability back into those P&R flows.

Of course, none of that’s any real help if it doesn’t run any faster. Which it does – an order of magnitude faster – and that’s the full round-trip time from the layout tool DB:

Summary

Today’s increasingly complex design and process technologies are exposing gaps in the implementation design flow. Siemens is showing some real creativity in their shift-left strategy. What’s unique about the new Calibre DesignEnhancer product is the addition of automated, analysis-aware, Calibre correct-by-construction layout optimization at an earlier stage in the flow where it makes a real difference in reducing IR drop.

Customers already have results to prove this really does cut through to reduced design cycle time and better design quality. Design kits are available for the major foundries and supported for all major layout design flows (both custom and digital), which already have tight and efficient Calibre integration, making user adoption straightforward.

Siemens state their mission for Calibre is to make chip design to tapeout as fast and easy as possible for its customers – so it’s against that standard this product should be judged.

Expect to see more information from Siemens EDA following this product launch.

Calibre DesignEnhancer

Also Read:

The Siemens Digital Industries Software View of AI and its Impact on System Design

Siemens Enhances Supply Chain Visibility with Real-Time Intelligence for its Xcelerator Platform

Transforming the electronics ecosystem with the component digital thread

July 17, 2023July 17, 2023

The Inconvenient Truth of Clock Domain Crossings

The Inconvenient Truth of Clock Domain Crossings
by Anupam Bakshi on 07-17-2023 at 6:00 am
Categories: Agnisys, EDA

Almost everything that we do in chip design and verification was invented to raise the abstraction above schematics and polygons. Register-transfer-level (RTL) design, functional simulation, logic synthesis, floorplanning, and more fall into this category. Even the notion of binary circuits is an abstraction. Underneath all this, the real world is analog, and the fundamental effects of electricity and silicon can’t be ignored or abstracted away.

One of these inconvenient truths is metastability, which can occur wherever a signal crosses between flip-flops on asynchronous clocks, called a clock domain crossing (CDC). If the input to the receiving flip-flop changes too close to its active clock edge, the flip-flop can take an indeterminate value before settling to a one or zero. If the flip-flop feeds the indeterminate value to downstream logic, the circuit may produce incorrect results.

Since there’s no way to avoid metastability, best practices for CDC design require that the downstream logic receives only valid values. The classic way to ensure this is to use a synchronizer consisting of two flip-flops on the receiving clock. If properly designed, there is a very high probability that the signal will have settled before it is clocked into the second flip-flop. Thus, only valid values are passed on to the rest of the circuit.

Multi-bit signals such as data buses require another approach since the bits may have different delays and an incorrect data value may be loaded into the receiving flip-flops. The best way to handle this is a handshake synchronizer, which creates a multi-cycle path (MCP) for the data bits so the inputs to the receiving flip-flops will be stable by the time the values are clocked in. This ensures that there is no metastability.

One common location for CDCs is the control and status registers (CSRs) used by low-level software to control and monitor chip hardware. CSR blocks have a software interface from which programs running on host systems (such as device drivers) or code running on the chip’s own embedded processors can write or read the registers. The software interface and register blocks themselves are usually in the system bus clock domain.

CSR blocks also have a hardware interface from which the rest of the chip can read or write the registers. The hardware uses this interface to read configuration values, communicate status back to the software, handshake with the software, and exchange data. Since the rest of the chip is almost always on a different clock than the system bus, there is a CDC that must be handled properly. Typically, two handshake synchronizers are used, one for the write path and one for the read.

Agnisys provides a pushbutton solution for clock domain crossings related to register blocks. Our IDesignSpec™ Suite helps chip architects and engineers create an executable specification for CSRs and automatically generate outputs for software and hardware teams. This includes generating the RTL code for the register block (in VHDL, Verilog, SystemVerilog, or SystemC) plus a bus slave and decode logic specific to the system bus protocol (AHB, APB, AXI, TileLink, or proprietary).

If the registers are in a different clock domain than the system bus, our solution also generates RTL for all the synchronization logic plus assertions for use in formal CDC verification. We support all three types of synchronizers discussed plus other options, including two-level flip-flops, mux, handshake, async FIFO synchronizers, and custom synchronizer blocks. We also handle cases in which the register block is in its own separate clock domain, distinct from the system bus and the rest of the hardware design.

We have many users who have benefitted from this automation. They do not need to worry about CDCs at all: they simply tell us their preferred synchronizer style and we generate everything for them. We have a lot of experience with CDCs and synchronization, and we are sharing our expertise with the rest of the industry. We are actively participating in the new Clock Domain Crossing Working Group within the Accellera Systems Initiative, focused on creating a standard for CDC abstraction models.

Should you want to have a discussion about clock domain crossing or any other design challenges, or would like to see a demo of the latest enhancements to our IDesignSpec Suite please contact us directly.

Agnisys is here to help you accelerate your IP/SoC front-end development with the industry’s leading Golden Executable Specification Solutions.

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July 15, 2023July 19, 2023

SEMICON West 2023 Summary – No recovery in sight – Next Year?

SEMICON West 2023 Summary – No recovery in sight – Next Year?
by Robert Maire on 07-15-2023 at 6:00 am
Categories: AI, Events, Semiconductor Advisors, Semiconductor Services
2 Comments

-SEMICON well attended but bouncing along the biz bottom
-Recovery seems at least a year away with memory even more
-AI creates hope but not impactful- Disconnect tween stocks & reality
-AMAT me too platform- Back end benefits from chiplets

SEMICON busy but subdued

SEMICON is certainly back to pre-covid levels or perhaps better. The show has turned its focus primarily to smaller tool makers or sub suppliers with larger companies having no floor presence and only doing private meetings in hotels. In general the show is a bit sparse but still a great place to network.

The general tone was positive for the long term but subdued and negative for the near term as we continue to bounce along the bottom in the current down cycle with no particular detectable change in momentum over the last 6 months or more.

Recovery at least a year away, likely longer for memory

This down cycle feels a lot like the downturn of 2000 which was fairly long lived. We see a similar pattern of over capacity that was brought about by the YTK buildup and in the current case the post Covid build up.

As we have also seen in the past, so called industry analysts always seem to suggest the downturn will be short lived and we will see a recovery in 6 months. Then six months comes around with no recovery and they kick the can down the road for another six months, saying the recovery is just another 6 months away.

Our view from the beginning of this downturn is that this downturn is fundamentally different , more systemic and therefore longer. It appears we have been correct so far in our more pessimistic projections.

We are already over a year in the current downturn which makes it one of the longer down cycles, at least as compared to more recent cycles.

We think that given current macro economic outlook coupled with semiconductor industry demand/capacity balance that we are at least a year off from a recovery.

The recent down month for TSMC revenues is certainly not a very good trend.

Memory will certainly take longer to recover as the supply demand imbalance is far worse than foundry or logic.

HBM is only bright spot in memory but far from enough

High bandwidth memory is the only bright spot in an otherwise ugly supply/demand imbalance. HBM is being driven by the AI craze which is clearly fantastic but is way to small overall to make up for the vast majority of memory applications which remain very weak.

Memory makers will certainly do everything to reallocate production to HBM which could eventually swamp demand and reduce premium pricing but at the very least it will help the acceleration of AI which will be good for the rest of the chip industry.

Fab project delays likely to increase as downcycle stretches

In short cycles of the past, new fab projects continue without much delay as by the time the building shell is done the industry is already in a recovery and equipment move in coincides with an upturn which works out.

The combination of a longer downcycle and a more tepid recovery will likely delay the many anticipated fab projects. Even though it seems like we continue to hear new projects every week, its almost a certainty that not all of them will ever get built let alone built on time.

TSMC is clearly having issues in Arizona. Intel is at least a year and probably a lot more delayed in Ohio.

Yet we still hear of new projects in Europe, Israel, Japan etc;. What we could eventually see is that given the likely over supply, chip makers will pick and choose to continue fab projects in countries and areas that offer the best economics and delay/cancel those that are not as attractive

What will Intel choose when faced with its current excess capacity situation with fabs planned for Arizona, Ohio, Europe & Israel? There is no way that all are going to be built….especially on time….it would be throwing gasoline on an already raging bonfire.

Memory is in far worse oversupply, with excess inventory, reduced production and loss making pricing. Some memory makers , such as Micron , would have a hard time even affording a fab project until we are firmly into an upturn. For memory that could be into 2025 with Boise not starting to come on line until 2027 and beyond and Clay NY years behind that probably into 2030’s.

Delays will require re-work of CHIPS for America

We have previously said that the CHIPS Act needs a “re-work”. The downcycle clearly was just way unlucky timing but it means that many of these now delayed fab projects will fall well outside of the 5 year time window originally scoped out for CHIPS.

If you are Micron, you are likely past the intended CHIPS Act window with most projects.

Getting enough HR talent for the chip industry is obviously a larger problem than first thought. Materials such as rare earth elements that we have been warning about for several years are now turning into the problem we anticipated as they became a weapon.

We wonder when CHIPS act money will have to be re-allocated to insure supply of critical rare earth element refining capacity which is non existent in the US.

In short circumstances have radically changed since the CHIPS act was envisioned and we need to quickly adjust or risk wasting money and time.

We still don’t have any plans for back end and packaging as all the lime light has been focused on front end fabs.

No big announcements at SEMICON – Only a “me too” platform from AMAT

There were no significant technology announcements at SEMICON and the only product announcement was AMAT with a “platform” change that goes to a “linear” configuration rather than a circular configuration for tool chambers

This is pretty much a “me too” announcement that follows in the foot steps of Lam’s “Sense.I” platform, announced a long while ago, to reduce footprint by going both linear and vertical.

Many manufacturers have been down this road as a linear configuration allows higher density versus circular “”mainframe” based designs that were more about accommodating the wafer handling robots. AMEC in China has long had a linear design along with an ill fated etch tool from Intevac or the “slingshot” from Semitool over a decade ago…..nothing new here.

BESI back end beneficiary of 3D packaging

The one significant thing, which is not particularly new, is the increased focus on packaging due to “more than Moore”, Chiplets and 3D packaging etc;.

Die & wafer bonding, die stacking and attach, interposer technologies and all things related to packaging multiple die are clearly very hot and in great demand.

BESI, has been in the packaging business forever and has worked very hard in relative obscurity in the little recognized dark recesses of chip making that was previously taken for granted. Obscure no more….Now they are working with the likes of AMAT that want to focus on the newly important back end of the industry where BESI has great technology and a long rich history. It has ben 27 years since we worked on the IPO of a little Dutch company that is finally in the spotlight…….

Disconnect between semiconductor reality and stock prices continues

Semiconductor stocks remain hot for no good reason whatsoever. We poke to a number of industry executives who privately commented that the disconnect was crazy and were fearful of a correction.

While we certainly agree with all the hype of AI and perhaps even more so than some of the optimistic bull cases….we think AI could be way bigger than the internet.

The disconnect is that while this is all great for the semiconductor industry it is not the be all, end all, that is the sole driver of chips that many people assume. Much as with the internet revolution, the supporting semiconductor infrastructure is critical to its functioning but sooner or later becomes a bit more mundane as telecommunications devices have become over time.

The chip stocks are acting like AI is going to double chip demand and launch the industry out of its current downcycle neither of which will likely happen.

AI is great for chips but not the savior that a global macroeconomic recovery would be.

The stocks

While SEMICON West seems back to its old self, the performance of the industry is far from it yet the stocks are acting as if it were…..

What to do?

Buy into the thundering herd mentality or risk being left in the dust.

Perhaps the real answer is to be increasingly selective and not just buy into a random sampling of chip stocks.

Looking for laggards or beaten down names that have yet to recover and lightening up on those that have been overheated.

We would want to be more defensive, perhaps a bit more biased to the small cap side.

Right now, the tidal wave that is AI is raising every boat in chips to new heights but sooner or later investors will be more selective.

Our concern is that as realization of a longer downturn comes about, investors patience may get tested and they may look for greener pastures while waiting on a recovery that is taking longer.

Time waits for no one.

Also Read:

SEMICON West 2023 Summary – No recovery in sight – Next Year?

Micron Mandarin Memory Machinations- CHIPS Act semiconductor equipment hypocrisy

AMAT- Trailing Edge & China Almost Offset Floundering Foundry & Missing Memory