Dr. Wei has served as CEO & CTO of Easy-Logic since 2020.  Prior to this role, Dr. Wei served as CTO since 2014 where he constructed the core algorithm and the tool structure of EasyECO.  As the CEO, Dr. Wei focuses on building a strong company infrastructure.  In his CTO role he interfaces with strategic ASIC design customers and leads the field support efforts to seamlessly align EasyECO’s technology with emerging industrial needs.  Wei worked at Agate Logic as an FPGA P&R algorithm developer prior to pursuing his PhD degree.

Dr. Wei received his PhD in Computer Engineering from the Chinese University of Hong Kong and both his MS and BS degrees of Computer Science and Technology from Tsinghua University.

Tell us about Easy-Logic

Easy-Logic was founded in year 2014 by a group of PhD graduates with their supervisor from the Chinese University of Hong Kong.  While in the school, they analyzed the EDA solutions for ASIC design industry and realized that functional ECO demands were growing at an alarming rate, but the EDA industry didn’t respond to it.

They participated in the CAD contest of ICCAD International Conference using the functional ECO-related algorithms developed in their research, won world champions 3 times in a row (2012- 2014).  Worth mentioning, in 2012, the contest subject was functional ECO provided by Cadence. Their algorithm performed twice as good compared to any other contender’s.

With a strong combination of the required product development expertise, Easy-Logic set its course for empowering the ASIC project teams to quickly react to functional ECOs at a substantially lower overall cost.

After the product EasyECO was first introduced in 2018, positive responses from the design industry surprised the young entrepreneurs.  The number of customer evaluation requests overwhelmed the startup, and Easy-Logic quickly became a rising star in the EDA industry.  Currently the customer base extends across Asia and North America, among them, many world’s top-tier semiconductor providers.

What problems are you solving?

Easy-Logic Technology is a solution provider for Functional ECO issues in the ASIC design.

A Functional ECO requirement occurs when there is a change in the RTL code that fixes, or modifies, the chip function.  Functional ECO means inserting only a small patch into the existing design (i.e., pre-layout, cell routing, or even post-mask) to make sure the logic function of patched circuit is consistent with revised RTL.  The purpose is to quickly implement the RTL change without re-spinning the whole design.

The design team may receive Functional ECO requests at any stage of the design process.

Depending on the design stage, the required RTL change ripples through design constraints like multi-clock domain and low power design rules, the DFT test coverage requirements, physical restrictions of the layout change, eventually metal changes, and timing closures.  There is no reliable correlation between the complexity of RTL change and the success of layout ECO even if the RTL change looks simple, where a ECO failure means project re-spin.

At present, most IC design companies still need to invest a lot of manual work in functional ECO because market leading EDA tools are not yet capable of effectively addressing challenging ECO issues.  Each design revision mentioned above requires a skilled engineer to crack down the problem based on the nature of the RTL change and the characteristics of the ASIC design.

Easylogic ECO’s automatic design flow efficiently solves functional ECO problems for design teams.

What application areas are your strongest?

Almost all ASIC designs require Functional ECOs, however, each different application has its unique ECO challenges.  Fortunately, EasylogicECO is structured to handle all challenges.

For example,

1. HPC has challenges on deep optimization which leads to larger differences between netlist and RTL structure, posing greater challenges for ECO algorithms.
2. AI chips comprise a significant amount of arithmetic logic, requiring specialized algorithms for arithmetic logic ECO.
3. Automotive area has challenges on scan chain fixing as test coverage is critical.
4. Consumer products, such as panel controllers, have challenges adopting subsequent functional ECOs as their products need to be versatile and are revised frequently.

EasylogicECO’s core optimization algorithm lays the foundation for all general optimizations on top of the general algorithm. Algorithm designed for each specific application scenario enables identifying and handling the application challenge automatically.

What keeps your customers up at night?

As mentioned earlier, there is no guarantee for the success of functional ECO and each failed functional ECO job means a project delay from weeks to months. The closer it gets to the tape-out stage, the greater the challenges in achieving success.  A re-spin when the design is close to tape out might even kill the product, so the enormous pressure on the success of ECO task, within the shortest ECO turnaround time, sometimes pushes designers over the edge.

Functional ECO is never a simple job.  Its importance has become an industry consensus, and yet, to this day, major EDA companies still couldn’t provide any satisfactory solutions.  The nagging uncertainty of whether the ECO task can be successful is extremely stressful.

What does the competitive landscape look like and how do you differentiate?

Most ASIC design companies still must invest a lot of manpower on complex functional ECO cases as the solutions provided by major EDA vendors couldn’t get the job done efficiently.

Easy-Logic is a newcomer in the functional ECO landscape.  Easy-Logic’s flagship product, EasylogicECO, deploys patented optimization algorithms to create a combination of

1. The smallest ECO patch
2. The easiest tool to address complex cases
3. The most suitable tool flow to address the depth of ECO design changes

That differentiates EasylogicECO from other solutions.

What new features are you working on? 

Functional ECO requires a complete design flow/toolchain.  Following Functional ECO, DFT ECO, PR ECO, Timing ECO, Metal ECO are also required.  Currently, there is no complete solution available for all these needs.  Easy-Logic is committed to developing a toolchain for the complete functional ECO process, enabling customers to easily navigate from an RTL change to a GDS2 change.

How do customers normally engage with Easy-Logic?

The easiest way is to send an email to the Easy-Logic Customer Response Team through the Contact Us form on the Easy-Logic website.  The Easy-Logic field team will reach out to the sender shortly.

Now that travel is open, Easy-Logic will appear in many conference events, the next one being DAC 2023 in San Francisco.  Please make an appointment before the event, or simply drop by, for a detailed solution discussion.

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