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Introduction to FinFET technology Part I

Introduction to FinFET technology Part I
by Tom Dillinger on 04-18-2012 at 6:00 pm
Categories: FinFET, Foundries, Intel Foundry, TSMC

This is the first of a multi-part series, to introduce FinFET technology to SemiWiki readers. These articles will highlight the technology’s key characteristics, and describe some of the advantages, disadvantages, and challenges associated with this transition. Topics in this series will include FinFET fabrication, modeling, and the resulting impact upon existing EDA tools and flows. (And, of course, feedback from SemiWiki readers will certainly help influence subsequent topics, as well.)

Scaling of planar FET’s has continued to provide performance, power, and circuit density improvements, up to the 22/20nm process node. Although active research on FinFET devices has been ongoing for more than a decade, their use by a production fab has only recently gained adoption.

The basic cross-section of a single FinFET is shown in Figure 1. The key dimensional parameters are the height and thickness of the fin. As with planar devices, the drawn gate length (not shown) separating the source and drain nodes is a “critical design dimension”. As will be described in the next installment in this series, the h_fin and t_fin measures are defined by the fabrication process, and are not design parameters.


Figure 1. FinFET cross-section, with gate dielectric on fin sidewalls and top, and bulk silicon substrate
The FinFET cross-section depicts the gate spanning both sides and the top of the fin. For simplicity, a single gate dielectric layer is shown, abstracting the complex multi-layer dielectrics used to realize an “effective” oxide thickness (EOT). Similarly, a simple gate layer is shown, abstracting the multiple materials comprising the (metal) gate.

In the research literature, FinFET’s have also been fabricated with a thick dielectric layer on top, limiting the gate’s electrostatic control on the fin silicon to just the sidewalls. Some researchers have even fabricated independent gate signals, one for each fin sidewall – in this case, one gate is the device input and the other provides the equivalent of FET “back bias” control.

For the remainder of this series, the discussion will focus on the gate configuration shown, with a thin gate dielectric on three sides. (Intel denotes this as “Tri-Gate” in their recent IvyBridge product announcements.) Due to the more complex fabrication steps (and costs) of “dual-gate” and “independent-gate” devices, the expectation is that these alternatives will not reach high volume production, despite some of their unique electrical characteristics.

Another fabrication alternative is to provide an SOI substrate for the fin, rather than the bulk silicon substrate shown in the figure. In this series, the focus will be on bulk FinFET’s, although differences between bulk and SOI substrate fabrication will be highlighted in several examples.



Figure 2. Multiple fins in parallel spaced s_fin apart, common gate input

Figure 2 illustrates a cross-section of multiple fins connected in parallel, with a continuous gate material spanning the fins. The Source and Drain nodes of the parallel fins are not visible in this cross-section – subsequent figures will show the layout and cross-section view of parallel S/D connections. The use of parallel fins to provide higher drive current introduces a third parameter, the local fin spacing (s_fin).

Simplistically, the effective device width of a single fin is: (2*h_fin + t_fin), the total measure of the gate’s electrostatic control over the silicon channel. The goal of the fabrication process would be to enable a small fin spacing, so that the FinFET exceeds the device width that a planar FET process would otherwise provide:

s_fin < (2*h_fin + t_fin)

Subsequent discussions in this series will review some of the unique characteristics of FinFET’s, which result in behavior that differs from the simple (2*h + t) channel surface current width multiplier.

The ideal topology of a “tall, narrow” fin for optimum circuit density is mitigated by the difficulties and variations associated with fabricating a high aspect ratio fin. In practice, an aspect ratio of (h_fin/t_fin ~2:1) is more realistic.

One immediate consequence of FinFET circuit design is that the increments of device width are limited to (2h + t), by adding another fin in parallel. Actually, due to the unique means by which fins are patterned, a common device width increment will be (2*(2h+t)), as will be discussed in the next installment in this series.

The quantization of device width in FinFET circuit design is definitely different than the continuous values available with planar technology. However, most logic cells already use limited device widths anyway, and custom circuit optimization algorithms typically support “snapping” to a fixed set of available width values. SRAM arrays and analog circuits are the most impacted by the quantized widths of FinFET’s – especially SRAM bit cells, where high layout density and robust readability/writeability criteria both need to be satisfied.

The underlying bulk silicon substrate from which the fin is fabricated is typically undoped (i.e., a very low impurity concentration per cm**3). The switching input threshold voltage of the FinFET device (Vt) is set by the workfunction potential differences between the gate, dielectric, and (undoped) silicon materials.

Although the silicon fin impurity concentration is effectively undoped, the process needs to introduce impurities under the fin as a channel stop, to block “punchthrough” current between source and drain nodes from carriers not controlled electrostatically by the gate input. The optimum means of introducing the punchthrough-stop impurity region below the fin, without substantially perturbing the (undoped) concentration in the fin volume itself, is an active area of process development.

Modern chip designs expect to have multiple Vt device offerings available – e.g., a “standard” Vt, a “high” Vt, and a “low” Vt – to enable cell-swap optimizations that trade-off performance versus (leakage) power. For example, the delay of an SVT-based logic circuit path could be improved by selectively introducing LVT-based cells, at the expense of higher power. In planar fabrication technologies, multiple Vt device offerings are readily available, using a set of threshold-adjusting impurity implants into masked channel regions. In FinFET technologies, different device thresholds would be provided by an alternative gate metallurgy, with different workfunction potentials.

The availability of multiple (nFET and pFET) device thresholds is a good example of the tradeoffs between FinFET’s and planar devices. In a planar technology, the cost of additional threshold offerings is relatively low, as the cost of an additional masking step and implant is straightforward. However, the manufacturing variation in planar device Vt’s due to “channel random dopant fluctuation” (RDF) from the implants is high. For FinFET’s, the cost of additional gate metallurgy processing for multiple Vt’s is higher – yet, no impurity introduction into the channel is required, and thus, little RDF-based variation is measured. (Cost, performance, and statistical variation comparisons will come up on several occasions in this series of articles.)

The low impurity concentration in the fin also results in less channel scattering when the device is active, improving the carrier mobility and device current.

Conversely, FinFET’s introduce other sources of variation, not present with planar devices. The fin edge “roughness” will result in variation in device Vt and drive current. (Chemical etch steps that are selective to the specific silicon crystal surface orientation of the fin sidewall are used to help reduce roughness.)

The characteristics of both planar and FinFET devices depend upon Gate Edge Roughness, as well. The fabrication of the gate traversing the topology over and between fins will increase the GER variation for FinFET devices, as shown in Figure 3.



Figure 3. SEM cross-section of multiple fins. Gate edge roughness over the fin is highlighted in the expanded inset picture. From Baravelli, et al, “Impact of Line Edge Roughness and Random Dopant Fluctuation on FinFET Matching Performance”, IEEE Transactions on Nanotechnology, v.7(3), May 2008.

The next entry in this series will discuss some of the unique fabrication steps for FinFET’s, and how these steps influence design, layout, and Design for Manufacturability:

Introduction to FinFET technology Part II

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Linley Tech Mobile Conference

Linley Tech Mobile Conference
by Paul McLellan on 04-18-2012 at 2:14 pm
Categories: Events, IP
2 Comments

I went to part of the Linley Tech Mobile Conference. This is the current incarnation of what started life as Michael Slater’s Microprocessor Report, and the twice-yearly Microprocessor Forum. These very technical analysis organizations seem to work well when they are a small group of analysts working together to cover an area of technology, but they don’t seem to scale very well once they are bought by the bigger companies with their high overhead of vice-presidents and sales teams. Microprocessor Report had its own history moving into Ziff-Davis, then Cahners/Reed and In-Stat and now back to its roots in the Linley Group. And as if to emphasize my point, a week ago NPD group apparently shut down In-Stat completely and laid off 30 analysts.

We all know the background to mobile microprocessors: smartphones and tablets are growing like crazy. Smartphones currently have 25% CAGR expected from 2011-15, an tablets even faster, at 54% CAGR although from a much smaller base (which means they triple over the period). By the 2015 smartphone growth should start to be leveling off in the classic S-curve. Everyone seems to be predicting that tablets won’t replace smartphones (I agree) nor PCs (I’m not so sure, I use mine more and more).

The rise of the smartphone has created a huge change in vendors: Samsung and Apple have pretty much taken all the money. Nokia has shrunk from #1, RIM is in trouble. Up and comers are Huawei, ZTE and LG.

Also Motorola which is about to be part of Google. My expectation is that Google will sell Motorola as soon as they can. They really bought it for the patents (to defend their Android licensees against Apple and others) and Wall Street will hate it if Google keeps it. They hate businesses that mix very different margins such as hardware and software. When I was running Compass and we were trying to sell the company, Bala Iyer, the CFO of VLSI, told me, “Wall Street will give me credit just for shutting you down; if we get any money for you, it’s icing on the cake.” I’m sure they are telling Google the same thing. But how much Motorola is worth without the patents is unclear (of course it would have a patent license to everything, but not the rights to sublicense). After all, it is not in any sense the market leader in smartphones or even Android phones. So I’m not sure who would buy them. Chinese companies are the ones rumored to be interested but I don’t quite see why, say, Huawei would want it.

In terms of semiconductor suppliers, it is the story of the rise of Qualcomm and Samsung and the decline of TI (who have exited the baseband business). A smartphone involves two primary sub-systems, the application processor and the baseband chip (which runs the radio interfaces). There has been a trend towards integrating these on the same chip but that trend has been interrupted since neither Samsung nor Apple do it, and they are such a large part of the market. Apple, for example, builds its own application processors (A4, A5) and uses Qualcomm for baseband. But the trend towards integation, plus Apple and Samsung rolling their own means there is only perhaps 20% of the market available to sell a merchant baseband processor. One big advantage of keeping the two subsystems in separate chips is that the whole radio interface (which doesn’t change so fast) doesn’t need to be requalified each time a new version of the application processor is created.

Apple’s new iPad uses the A5X application processor. This is a huge chip using a quad-core Power-VR GPU. The GPU alone is 60mm[SUP]2[/SUP] of die area which is larger than the whole of Nvidia’s Tegra2. But it has to do more than HD and can maintain a frame rate of 50fps on the iPad’s 3 megapixel display. And Apple has enough margin on the new iPad to bury the cost.

Intel and MIPS are trying to challenge ARM’s dominance of the application processor. In principle Android allows alternative architectures painlessly since Apps are distributed as Java bytecodes (which is architecture neutral). In practice, many Android Apps, especially games, incorporate native ARM code making things rather more painful. The solutions are not attractive:

  • pay developers to port (OK for Angry Birds but doesn’t really scale to the whole ecosystem)
  • use JIT emulation (as Apple themselves did to get legacy powerPC code to run on Intel-based Macs) but since the reason for using ARM code is usually performance this might not work
  • get a virtuous cycle going whereby developers don’t want to miss out as the Intel/MIPS phones grow. Chickens and eggs come to mind.

That day, EETimes reported rumors that MIPS had engaged Goldman to help them find a buyer for the company. At the small exhibition that evening the MIPS employees manning their table looked a bit glum. “want to license a microprocessor? Or how about buying…like…the whole company?”

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Analog Circuit Optimization

Analog Circuit Optimization
by Daniel Payne on 04-18-2012 at 2:06 pm
Categories: Uncategorized
6 Comments

Gim Tan at Magma did a webinar on analog circuit optimization, so I watched it today to see what I could learn about their approach. Gim is a Staff AE, so not much marketing fluff to wade through in this webinar.

The old way of designing custom analog circuits involves many tedious and error prone iterations between front-end (Schematic Capture, circuit simulation) and back-end (layout, DRC/LVS, extraction):


The Maga-based custom IC design flow uses:

  • Model-based cells called FlexCells in Titan ADX:
  • Circuit simulator, FineSim SPICE
  • Floorplan, Titan AVP
  • Automated routing, Titan SBR
  • Automated IC layout migration, Titan ALX


Titan AMS has the following tools:

  • Schematic Capture
  • Analog Simulation Environment (wafeforms, cross-probing)
  • Schematic Driven Layout (SDL), uses iPDK or pCells or IPL
  • Layout Editor
  • Process Verification (violation analysis in a GUI)

Foundry support for Titan AMS:

  • TSMC: 180nm, 65nm, 40nm, 28nm. AMS Reference flow 2.0
  • TowerJaxx: 180nm, AMS Reference flow
  • LFoundry: 150nm

Titan Analog Design Accelerator (ADX)

  • Optimize, re-size schematics
  • Process porting
  • Feasibility studies

The design flow with Titan ADX is:

With this flow you can start by importing your old schematics and transistor-level netlists. What’s unique about this flow is the use of FlexCell, which adds a mathematical view using Matlab equations for a circuit along with the traditional views: Schematic, Layout, Testbench

There are ready-made FlexCells for you to start using right away and to help learn model behavior, intent and set constraints. Here’s an example two-stage PMOS Op-Amp FlexCell:

A predecessor to Titan ADX was a technology from Barcelona Design where they used a proprietary modeling language called Flamingo. The learning curve for Matlab should be much shorter than for the old Flamingo code.

Once you’ve defined your analog design as a FlexCell then you can do analog IP optimization with Titan ADX:

Titan ADX is model-based optimization, not simulation based, so that makes it quite unique in the EDA industry. Synopsys also has a simulation-based optimizer (acquired Analog Design Automation), so it will be interesting to see the new product roadmap and if Titan ADX is carried forward.

Magma has a library of FlexCells that you can use:

TSMC is using FlexCells to retarget their own IP for customers as needed. Fraunhoffer is also offering FlexCells.

Titan ADX flow:
[LIST=1]

  • Choose a FlexCell, un-sized schematic
  • Choose a technology
  • Define your specifications and scenarios
  • Optimize
  • Output is a sized schematic netlist


    PLL Migration
    A traditional migration to a different 65nm process node takes 7 weeks (circuit design, functional verification, physical design, physical verification), while with ADX the same task is doe in 1 week or a 7X improvement in time. This kind of improvement assumes that you have all the required FlexCells in place before hand. If you had to write and verify new FlexCell models then that would decrease the time improvement.


    Real Customers
    So far this model-based optimization approach sounds unique and powerful, however who is really using it? Panasonic and TSMC plus the following are using it:

    One Model, Multiple Results
    Using FlexCells and Titan ADX you can optimize for either power or area, or something in between:

    Summary
    Magma offers model-based optimization in Titan ADX which is a different approach than simulation-based optimization. This model-based approach is certainly more elegant than the brute force simulation-based optimization approach, and you’ll have to decide if you can just quickly use the existing FlexCells off the shelf or have to invest in writing your own MATLAB equations for new FlexCells.


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    Changing your IC Layout Methodology to Manage Layout Dependent Effects (LDE)

    Changing your IC Layout Methodology to Manage Layout Dependent Effects (LDE)
    by Daniel Payne on 04-18-2012 at 12:38 pm
    Categories: EDA, Siemens EDA
    6 Comments

    Smaller IC nodes bring new challenges to the art of IC layout for AMS designs, like Layout Dependent Effects (LDE). If your custom IC design flow looks like the diagram below then you’re in for many time-consuming iterations because where you place each transistor will impact the actual Vt and Idsat values, which are now a function of proximity to a well:


    Source: EE Times, Mentor Graphics

    Analog designs are most sensitive to variations in Vt and current levels, especially for circuit designs that need precise matching.

    Engineers at Freescale Semiconductor wrote a paper about Layout Dependent Effects and presented at CICC to quantify how much Vt and Idsat would change based on the location of MOS devices to the edge of a well.


    Well Proximity Effect (WPE), Source: Freescale Semiconductor

    What they showed was Vt became a function of proximity to the well edge and its value could shift by 50mv:


    Vt variation. Source: Freescale Semiconductor

    Drain current levels can vary by 30% based on proximity to the well edge:


    Id variation. Source: Freescale Semiconductor

    EDA developers at Mentor Graphics decided to create a different IC design methodology to provide earlier visibility to the IC design team about how LDE is impacting circuit performance. Here’s the new flow:


    Source: EE Times, Mentor Graphics

    Design constraints about matching requirements are entered at the schematic design state, then fed forward into an LDE estimator module for use during placement. A constraint would define the maximum change in Vt or Id levels between transistors that require matching.

    While layout placement is being done the LDE estimator module can quickly determine how each MOS device Vt and Id values are impacted, then compare that to the design constraints provided by the circuit designer, all before routing is started. The layout designer can continue to rearrange transistor placement until all constraints are passing.

    Notice how there was no extraction and SPICE circuit simulation required during this LDE estimation phase, the layout designer is interactively placing MOS devices and verifying that the layout is passing or failing the constraints set by the circuit designer.

    Test Results
    A two-stage Miller OTA amplifier circuit was designed and put through the new methodology.

    Schematic capture and layout were done with Pyxis, extraction using Calibre and circuit simulation with Eldo. The target Gain and Bandwidth specs were first met by transistor sizing and circuit simulation, with results shown below:


    The first layout iteration was done without the traditional IC flow shown, no LDE estimation was used however the extracted netlist failed both Gain and Bandwidth specs:

    Next, layout was done with the LDE estimator module during placement to give the layout designer early feedback on MOS device constraints. The new layout is slightly different from the previous one and most importantly this new layout meets the Gain and Bandwidth specifications:

    Here’s a table that summarizes the change in Vt and Id values for each MOS device compared between the first placement and final device placement:

    Using the methodology of LDE estimation during placement produced an analog opamp with Vt variations that were up to 10X smaller, and Id variations that were up to 9X smaller.

    Summary
    Analog circuits are most sensitive to LDE effects, so you need to consider a new methodology to quickly provide feedback on how good your layout is while you are still interactively placing MOS devices instead of waiting until routing, extraction and circuit simulation are completed. This new methodology is all about early feedback which will actually speed up analog design closure.


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    ARM Seahawk

    ARM Seahawk
    by Paul McLellan on 04-17-2012 at 8:27 pm
    Categories: Arm, IP

    I wrote on Monday about ARM’s Processor Optimization Packs (POPs). In Japan they announced yesterday the Seahawk hard macro implementation in the TSMC 28HPM process. It is the highest performance ARM to date, running at over 2GHz. It is a quad-core Cortex A15.

    The hard macro was developed using ARM Artisan 12-track libraries and the appropriate Processor Optimization Pack announced on a couple of days ago. Full details will be announced at the CoolChips conference in Yokohama Japan today. It delivers three significant firsts for the ARM hard macro portfolio, as not only is this the first quad–core hard macro, but also the first hard macro based on the highest performance ARMv7 architecture-based Cortex-A15 processor, and it is also the first hard macro based on 28nm process.

    The ARM press release is here. A blog entry about the core is here.

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    Previewing Intel’s Q1 2012 Earnings

    Previewing Intel’s Q1 2012 Earnings
    by Ed McKernan on 04-17-2012 at 9:15 am
    Categories: Foundries, Intel Foundry

    Since November of 2011 when Intel preannounced it would come up short in Q4 due to the flooding in Thailand that took out a significant portion of the HDD supply chain, the analysts on Wall St. have been in the dark as to how to model 2012. Intel not only shorted Q4 but they effectively punted on Q1 as well by starting the early promotion of Ivy Bridge ultrabooks at the CES show in January. Behind the scenes, Intel made a hard switch to ramping 22nm production at three fabs faster than what is typical in order to cross the chasm and leave AMD and nVidia behind. But that is not all, I believe Paul Otellini will take considerable time discussing the availability of wafers at Intel relative to that of TSMC and Samsung in supplying the demands expected to come from this years’ Mobile Tsunami.

    As mentioned in previous writings, the capital expenditures put forth by Intel in 2011 and expected in 2012 point to a company that expects to nearly double in size (wafer capacity) by end of 2013. The single digit PC growth and mid-teen server growth can not soak up all the new wafers. It has to come from another high volume segment. I have speculated that it is Apple and other tablet and smartphone OEMs. In rough numbers it would be on the order of 400MU of mobile processing capacity. Or it can be a combination of processors and 3G/4G silicon. Either way, it was a big bet on Intel’s part to go out and expand their fab footprint.

    In the last few weeks there have been a series of articles on this site and in EETimes that at first argued TSMC was having yield issues at 28nm. As time as gone on, it appears that it was not yield issues but capacity or lack thereof. TSMC’s customers made forecasts two to three years ago, during the worst part of the economic crises that did not account for the step function increase in demand for leading edge capacity to service our Mobile Tsunami build out. The difficulty of any foundry is to modulate the demands of multiple inputs. TSMC has to be aware of double counting that leads to four or five vendors expecting to own 200% of the ARM processor market or wireless baseband chips. Intel, however, did make the bet but probably based on the strength of their process technology.

    But there are intriguing questions on Intel’s side as well. For the past year, I have observed and noted that the ASPs on Intel chips no longer fall every 6 to 8 weeks like they did in their old model. It was part of the strategy to keep competitors gasping for air to keep up. It seems to say that they can set prices at will.

    Even more interesting is the fact that the first Ivy Bridge parts to be introduced are in the mid to high-end range which is different than what they did in the past. The low end Ivy Bridge will not arrive until late Q3. This says there is either very high demand for Ivy bridge or they can’t build enough or both. Ramping production on three fabs means a lot of wafers are headed down the line with the goal of getting yield up sooner. Is the 22nm trigate process one that inherently have lower yield? If the answer is that Intel will get into high yield mode this summer, than they have the flexibility of selling FREE $$$ Atoms into the Smartphone space with the goal of attaching higher ASP based 3G/4G baseband chips – this is my theory as to how they ramp revenue starting late 2012 and through the 2013 year, which is before TSMC and Samsung can catch up on 28nm capacity. Apple, who just launched their new iPAD with the A5X built on the antiquated 45nm process will be taking lots of notes today.

    FULL DISCLOSURE: I am long INTC, AAPL, QCOM, ALTR


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    Laker Wobegon, where all the layout is above average

    Laker Wobegon, where all the layout is above average
    by Paul McLellan on 04-17-2012 at 4:00 am
    Categories: Uncategorized
    4 Comments

    TSMC’s technnology symposium seems to be the new time to make product announcements, with ARM and Atrenta yesterday and Springsoft today.

    There is a new incarnation of Springsoft’s Laker layout family, Laker[SUP]3[/SUP] (pronounced three, not cubed). The original version ran on its own proprietary database. The second version added openAccess to the mix, but with an intermediate layer to allow both databases to work. Laker[SUP]3[/SUP] bites the bullet and uses openAccess as its only native database. This gives it the performance and capacity for 28nm and 20nm flows.

    There are a lot of layout environments out there. Cadence, of course, has Virtuoso. Synopsys already had one of their own and then with the acquisition of Magma have a second one. Mentor is in the space. Some startups are in the space too. Springsoft had an executive pre-release party on Thursday last week (what EDA tool doesn’t go better with a good Chardonnay) and one senior person (who had better remain nameless since I don’t think it was meant to be an official statement of his employer) said that he thought that by the time we get to 20nm there are only going to be a couple of layout systems with the capability to remain standing and Springsoft would be one.

    There are three big new things in Laker[SUP]3[/SUP]. The first is the switch to openAccess. But they didn’t just switch they also re-wrote all the disc access part so that there is a performance increase of 2-10X on things like reading in designs or streaming out gds2. But many intermediate things are also reading and writing stuff to disk so it is not just the obvious candidates that speed up.

    The second is that the previous versions of Laker had a table driven DRC. That has been completely re-written since just simple width and spacing type rules are no longer adequate (‘simple’ is not a word that anyone would use about 28nm design rules, let alone 20nm with double patterning and other weird stuff). The new DRC can handle these types of rules, but it is not positioned as a signoff DRC, it is used by all the rule-driven functions and by place and route. On the “trust but verify” basis, Calibre is also built into Laker in the form of Calibre RealTime that runs continuously in the background giving instant feedback using the signoff rule deck. Since no designer can actually comprehend design rules any more, this is essential. The alternative, as one customer of another product complained, is having to stream out the whole design every 15 minutes and kick off a Calibre run.

    The third big development is an analog prototyping flow. One big difference is that most constraint generation (to tell the placer what to do) is automatically recognized as opposed to the user having to provide a complex text file of constraints. Symmetrical circuits are recognized by tracing current flow, common analog and digital subcircuits such as current mirrors are recognized. The library of matched devices is extendible so that prototyping flow gets smarter over time as the idiosyncrasies of the designer, design or company get captured. There have been numerous attempts to improve the level of automation in analog layout, the hillside is littered with the bodies. This looks to me as if it manages to strike a good balance between automating routine stuff while still leaving the designer in control (analog design will never be completely automatic, let’s face it).

    Laker for a time was regarded somewhat unfairly as “only used by people in Taiwan” where admittedly it has become the dominant tool. But two of the top five fabless semiconductor companies have standardized on Laker, and five of the top ten semiconductor companies are using it. And the hors d’ouvres in the edible spoons at the launch party were pretty neat.

    More details on Laker[SUP]3[/SUP] are here.


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    Soft Error Rate (SER) Prediction Software for IC Design

    Soft Error Rate (SER) Prediction Software for IC Design
    by Daniel Payne on 04-16-2012 at 10:00 am
    Categories: EDA, IROC Technologies

    My first IC design in 1978 was a 16Kb DRAM chip at Intel and our researchers discovered the strange failure of Soft Errors caused by Alpha particles in the packaging and neutron particles which are more prominent at higher altitudes like in Denver, Colorado. Before today if you wanted to know the Soft Error Rate (SER) you had to fabricate a chip and then submit it to a specialized testing company to see the Failure In Time (FIT) levels. It can be very expensive to have an electronic product fail in the field because of Soft Errors and the SER levels are only increasing with smaller process nodes.


    Intel 2117, courtesy of www.cpumuseum.com

    Causes of SER
    Shown below are the three causes of SER:
    [LIST=1]

  • neutrons found in nature can strike Silicon creating alpha particles
  • Impurities in packaging materials emit alpha particles
  • Boron impurities can create alpha particles

    When an alpha particle strikes the IC it can upset the charge in a memory cell or flip-flop, causing it to change states, leading to a temporary logic failure.

    SER Prediction Software
    The good news is that today a company called iROC announced two software tools that will actually allow IC designers to predict and pinpoint the layout and circuit locations that are most susceptible to high FIT levels.

    • TFIT (Transistor Failure In Time)
    • SOCFIT (SOC Failure in Time)

    The TFIT tool reads in something called a Response Model provided by the Foundry, your SPICE netlist, and GDS II layout, it then runs a SPICE circuit simulation using HSPICE or Spectre (can be adapted to work with Eldo, etc.). Output from TFIT is the FIT rate of each cell and it can show you which transistors are most triggered by neutron particles so that you can improve your design sensitivity. This simulation run takes tens of minutes.

    SRAM designers can add Error Correcting Codes (ECC) to their designs to mitigate FIT, however a Flip-Flop has no ECC so one choice is to harden the FF which creates a cell that is 2X or 3X the size and power.

    A FF netlist can be analyzed by TFIT in about 10-20 minutes.

    SER Data has the FIT info for all FF and SRAM cells, including combinational logic.

    SOCFIT can be run on either the RTL or gate-level netlist, and has a capacity of 10+ million FFs. It uses a static timing analysis tool (Synopsys Primetime, Cadence), and can also use simulation tools for fault injection (Synopsys, Cadence). It first runs a static analysis on RTL or gates to determine the overal FIT rate, if your design is marginal then you can run a dynamic analysis using fault injection (typical 10 hour run time). This approach could use emulation to speed up results in the future.

    The SOCFIT tool answers the question, “Which cells are the most sensitive in my design?”

    You can even run SOCFIT before final tapeout, while logic is changing. SOCFIT has been under development for 8 years now, and they’ve seen good correlation between prediction and actual measurement.

    SER Info
    Both memory and logic have SER issues, even FF circuits, but not so much combinational logic because of its high drive.

    One particle can upset multiple memory bits now in nodes like 40nm and smaller.

    SRAM is more sensitive to neutron particles than FFs, then DRAMs are less sensitive because alpha particles impact leakage.

    Flash memory is even less sensitive than DRAM to Single Event Upsets (SEU).

    The FPGA architecture is most sensitive to SER because of the heavy use of FF cells.

    Bulk CMOS is more sensitive than SOI.

    FinFET is new, so iROC is just starting to analyzing that from an R&D viewpoint using 3D TCAD models. You can expect to see more data later in the year.

    TFIT will cover all voltages, and process variations.

    TSMC provides the Response Model input to TFIT, and they have been providing the SER Data to customers based on testing in the past, not simulation.

    iROC – The Company
    iROC (Integrated RObustness On Chip) has a mission to analyze, measure and improve SER on ICs. They’ve been providing SER testing services since 2000, where they bring chips to a Cyclotron and expose them with Neutron beams to replicate 10 years of life in just minutes. iROC also partners with foundries like TSMC and GLOBALFOUNDRIES.

    Competition to the iROC approach are mostly internally developed R&D tools from IDMs.

    Some 500 chips have been tested so far, so iROC understands the problems and how to prevent them from being catastrophic.

    Summary
    iROC is the first commercial EDA company to offer two SER analysis tools used at the cell and SOC levels, the tool results correlate well with actual measurements on silicon chips. This will be an exciting company to watch grow a new EDA tool category in the reliability analysis segment.