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Channel Routing Memories

Channel Routing Memories
by Paul McLellan on 04-23-2012 at 1:12 pm

Back in the early days of ASIC when we had just two and then (wow!) three layers of metal, place and route was done by putting the standard cells in rows with gaps between them and then using a specialized router to do the interconnection. It would use one layer of metal horizontally and one vertically and avoid jogs. This was called a channel router. For digital place and route today we have lots more layers of metal and we are not restricted to keeping our routing contained in the channel.

But memories are different. They have fewer layers of metal and end up with long narrow areas between the memory arrays and around the outside. Memories are also early into new processes and the first that have to deal with more restricted design rules. As a result, there is a need for routing this sort of area with long jogless nets, just like in the old days of 3-layer metal ASICs.

Normal digital place and route, or a shape-based router, does not give the right results, producing too many jogs, too many vias and is not controllable enough by the designer. But a straightforward implementation of a 1980s channel router isn’t adequate either. The connection points are inside the blocks, care needs to be taken feeding signals through the blocks. What is required is a smart way to create the pins that is aware of just how the channel router is going to behave. Otherwise it is too easy to create designs where one pin blocks another route (remember, we are avoiding jogs and vias). The router needs to drive the pin placement.

Pulsic’s spine and stitch router does this. The pin placement is driven by the router so that eventually everything can be routed with long straight wires. There is an example below, although, of course, a real example would likely involve thousands of nets. The spine router with pin placement can do in 30 minutes what used to take a designer doing it manually 3 weeks. Using intelligent pin sorting the router will typically complete over 95% of the nets leaving just a handful where the designer needs to guide the tradeoffs involved.



AMS Design using Co-Simulation

AMS Design using Co-Simulation
by Daniel Payne on 04-23-2012 at 11:13 am

The big three vendors in EDA offer AMS simulation tools but what about simulation choices from other EDA vendors?

It turns out there are two privately held EDA companies that have done business since the 1980’s and have just integrated a Verilog A simulator with a SPICE circuit simulator. The two companies are Aldec with a Verilog A simulator and Tanner EDA with a SPICE circuit simulator. To learn more about this AMS simulation capability I reviewed a webinar from March 8th, 2012.

Jeff Miller presented for Tanner EDA and Jerry Kaczynski for Aldec. Each company has over 30,000 EDA licenses in use worldwide.

The AMS tool flow starts with design capture in S-Edit then an automated netlist out to T-Spice AMS which uses Verilog A in Aldec’s Riveria PRO and SPICE in Tanner’s T-Spice:

Waveforms for analog signals are viewed in the Tanner viewer, while digital signals are viewed in the Aldec tool:

With Riviera-PRO the digital simulator features:

  • Verilog, VHDL, SystemVerilog, SystemC
  • Assertion-based verification
  • Command line or GUI operation
  • Code and functional coverage
  • Transaction-level debugging
  • APIs to communicate
  • Runs on Linux, Windows XP, Vista and Windows 7

This is a co-simulation approach, not a single kernel approach like that offered by Synopsys, Cadence and Mentor. For most AMS netlists the SPICE simulation will usually limit the run time.

The demo showed an ADC design where capture is done in Tanner’s S-Edit tool then netlisted. S-Edit automatically detects what block is netlisted for Spice and for Digital. T-Spice is run on the netlist which then invokes the digital simulator, Riviera-PRO.

Q&A
Q: Does the logic netlist run through the T-Spice input file buffer, causing capacity issues?
A: There isn’t a character limit to T-Spice parsing, so we don’t know of any capacity issues.

Q: Is it better to use a 64 or 32 bit OS for my AMS simulation?
A: It really depends on your memory requirements. For large memory requirements then you could run out of memory space on a 32 bit OS, so then use the 64 bit version on Linux or Windows for Riveria. On the SPICE side you can also use either 32 or 64 bit versions.

Q: Which OS versions are supported for this AMS co-simulation?
A: Windows 32 bit or 64 bit, Linux only 32 bit on the SPICE side.

Q: If I have a mixed signal design can I independently specify a Verilog and SPICE view without using two instance names?
A: Yes, you can specify per instance if this cell is Verilog or SPICE view.

Q: Does this co-simulation work with Active-HDL?
A: Use Riviera PRO for this AMS co-simulation for now. Active-HDL could be added in the future if there’s enough demand, it’s not a technical issue just a demand issue.

Summary
If you already own a Tanner EDA or Aldec simulator and want to start doing AMS simulation for IC designs then this affordable co-simulation approach should be considered. I’d expect to see in the product roadmap a few useful features like:

  • Unified waveform viewer, instead of two viewers
  • Cross-probing between schematic, source and wave form viewer
  • Interactive simulation where you can start, stop, measure and continue

The webinar is online here.


UMC Wins Qualcomm 28nm Second Source Contract!

UMC Wins Qualcomm 28nm Second Source Contract!
by Daniel Nenni on 04-22-2012 at 7:00 pm

This is common knowledge in Taiwan but apparently the guys over at SemiAccurate.com did not get the memo. I hear a name change is in the works: www.RarelyAccurate.com. Remember, these are the same clairvoyants who said TSMC shut down 28nm which as we now know is absolutely false. The QCOM elite stay at the Hsinchu Royal Hotel which is 5 minutes away from UMC HQ. The Royal is also my hangout so I see and hear these guys quite a bit.

TSMC absolutely did NOT halt 28nm production!

This article is titled “UMC Wins Qualcomm’s 28nm Node Contract” but what they mean is second source contract. We all know QCOM is at TSMC 28nm, as is everyone else. QCOM mostly uses the TSMC 28nm LP process for both low power and low cost. TSMC and UMC are the only foundries today with both a 28nm LP (poly/oxynitride) process and 28nm HLP (high k metal gate) processes. GlobalFoundries only has 28nm HLP, so sorry Charlie, QCOM will NOT be “moving majority of production to GlobalFoundries” anytime soon.

If you look through the UMC 2010 annual report you will see that UMC has a handful of customers that do the bulk of the business. Leading those is Texas Instruments. TI went fab-lite 5 years ago and chose TSMC for first source and UMC for second source. First tape-outs go through TSMC because TSMC is always first to market with a new node. Once UMC ramps production the fight for the best wafer price begins and that will go to UMC, which is why TSMC’s profit margins are 31% versus UMC’s 9%.

Does TSMC enjoy doing all of the bleeding edge work only to get shut out when serious production starts? Of course not, it is very frustrating but second sourcing is the nature of the fabless semiconductor business.

TSMC 28nm Yield Explained!

Qualcomm and Broadcom are different as they buy wafers from multiple fabs at 40nm and above: TSMC, UMC, SMIC, and GFI, because that is the way they do business. Other companies like Altera, Nvidia, and Oracle, single source at TSMC which is a much more intimate relationship but capacity can always bite you in the ass which at 28nm it certainly did.

One thing you have to understand is that the Fabless – Foundry relationship is hugely contractual. Fabless companies sign up for a certain wafer count in a defined time period and there are penalties on both sides if it is not met. To my knowledge, based on what I have read and heard at the Royal Hotel, TSMC has fulfilledALL contractual commitments on 28nm. Don’t believe me? Ask that question on the next QCOM or NVDA conference call. “Did TSMC meet the contracted wafer delivery numbers at 28nm thus far?”

The Truth of TSMC 28nm Yield!

What happens if the Fabless Company needs more wafers than in the contract? That is called a “Hot Lot” or a rush order which they pay a premium for, up to 50% I have heard. Correct me if you know otherwise.

20nm will be more of the same. The TSMC 20nm first customer list will be the same as 28nm plus maybe Apple. The same yield drama will ensue only to be debunked. Some will stay at TSMC 20nm, some will second and third source if they can. TSMC’s recent CAPEX increase is for 20nm capacity so the race is definitely on!



Audio IP Subsystems Made Easy with a Complete, SoC-Ready Solution

Audio IP Subsystems Made Easy with a Complete, SoC-Ready Solution
by Eric Esteve on 04-22-2012 at 12:22 pm

After the launch of ARC based complete sound system IP by Synopsys last month, which could be the effective starting point for subsystem IP offering, providing the initiative will be successful (this was not really the case in the past, as we discussed it in our blog), the company proposes a webinar focusing on:

  • The growing complexity of audio requirements for advanced SoC designs
  • How a pre-verified, integrated audio IP subsystem solution, consisting of hardware, software and prototypes reduces integration effort, lowers risk and accelerates time-to-market
  • The feature requirements for implementing audio functionality into a SoC
  • How configuration of a complete audio IP subsystem can be done in hours

Considering that the trend towards internet-connected consumer devices is driving an increase in the audio requirements and complexity of today’s SoCs, and that these designs need to support elements such as multi-channel, high-definition audio formats as well as plug seamlessly into the host application software, Synopsys is offering a pre-verified, although configurable solution. This allows designers to integrate dedicated audio subsystems to offload the audio processing from the host processor, thus reducing design complexity and improving performance and efficiency of the SoC.

To register to this webinar, just go here, and remind that it will be held on Thursday, April 26.

As far as I am concerned, I will carefully monitor this initiative from Synopsys, as the potential move from a single IP function to a complete subsystem, looking very attractive –in theory- may change the IP market behavior as we know it today. Would the initiative be successful, the market changes could be deep, offering opportunities to new comers to enter and generating partnership between small vendors (like it was the case between PHY and Controller IP vendors in the 2005-2010, but unfortunately not yielding as expected). It could be also an opportunity for one of the two others to attack again the IP market, but with a renewed strategy… We will se.

From Eric Estevefrom IPnest


Flexible ASIC Strategy!

Flexible ASIC Strategy!
by Daniel Nenni on 04-21-2012 at 9:00 pm

During my last Taiwan trip I also spent time with Global Unichip. Clearly, in order for the semiconductor industry to thrive we must enable design starts. With the rising costs and complexity of semiconductor design and manufacturing this is a much greater challenge which is why I’m so interested in GUC, for the greater good of the semiconductor ecosystem.

GLOBAL UNICHIP CORP. (GUC), the Flexible ASIC Leader[SUP]TM[/SUP] is based in Taiwan and provides a comprehensive suite of The Flexible ASIC Services[SUP]TM[/SUP] that meet the unique business and technology requirements of today’s innovative technology company.

The design services businesses really took off with the likes of eSilicon, Open-Silicon, and a dozen others, enabling the outsourcing of semiconductor design and operations. Unfortunately that is a very margin centric business which, as it turns out, is very hard to scale. Single digit margins also limit exit strategies which will kill future investment and growth.

GUC provides an unmatched combination of advanced technology, low power and embedded CPU design capabilities and production knowhow through close partnership with TSMC and major packaging and testing companies that are ideal for advanced communications, computing and consumer electronics ASIC applications. The company has the proven ability to maximize the power/ performance sweet spot while delivering the fastest possible time-to-market. GUC’s uncompromising performance provides the absolute best power, speed, quality, yield and on-time delivery. Our goal is to innovate and deliver world class Flexible ASIC Services that elevate IC visionaries to the next level of leadership in their markets.

How is the Full Service Flexible ASIC strategy different? Simple, it’s a matter of changing with the times. Risk adverse start-up fabless companies are no longer a growth market. Medium to large fabless semiconductor companies are where the growth is. Designing high speed semiconductors in the third dimension is Flexible ASIC. Differentiation through custom IP is Flexible ASIC. Providing a higher level of IP abstraction is Flexible ASIC. The future of ASIC is Flexible ASIC.

“We thought it appropriate to adopt the ‘guc-asic.com’ domain name because it more accurately reflects GUC’s positioning and how our customers are beginning to view us,” said Jim Lai, President of GUC. “The name is also very easy to remember
and very easy to type, which clearly offers some major advantages for our shareholders, customers and partners.”

GUC made some interesting changes last week, a new URL (www.guc-asic.com) and a new logo in support of the Flexible ASIC strategy. Honestly, the old logo made me dizzy so this is a good thing. Search engine optimization is also important and the URL is a key part of SEO. Most importantly it sends a strong message to competitors, partners, investors, and customers. Global Unichip Corp. (GUC), the Flexible ASIC LeaderTM, has a scalable business model.

Based in Hsin-chu, Taiwan GUC has developed a global reputation with a presence in China, Europe, Japan, Korea, and North America. GUC is publicly traded on the Taiwan Stock Exchange under the symbol 3443.



Milestones to Building a Successful Technology Software Company

Milestones to Building a Successful Technology Software Company
by Daniel Payne on 04-19-2012 at 11:04 pm

May 31, 2012 at Silicon Valley Bank, Santa Clara, CA

Join us on May 31, 2012 for the first in a series of conversations exploring concepts and best practices for emerging companies. The first conversation will outline the critical milestones which must be conquered to take a start-up from early stages to a strong, growing, sustainable business. [Additional information]
The three participants in this conversation have had serial success with navigating companies through concept to successful liquidity events. The content is geared to founders and executives of software, systems, and semiconductor companies, as well as others interested in getting a birds-eye view of what companies face as they various stages of success.

Jim Hogan, Private Investor
Dean Drako, President and CEO, IC Manage
Ravi Subramanian, President and CEO, Berkeley Design Automation

Date & Time:
Thursday, May 31[SUP]st[/SUP] 2012
6:00 PM Reception
7:00 PM Emerging Companies Conversation
8:00 PM Q&A

Location:
Thursday, May 31[SUP]st[/SUP] 2012
6:00 PM Reception
7:00 PM Emerging Companies Conversation
8:00 PM Q&A

Cost:
There is no charge for this event. Seating is limited, so please register early!

Organized by:

Steve Pollock, Chairman, EDAC Emerging Companies Committee
Georgia Marszalek, Valley PR
Gloria Nichols, Launch Marketing

Sponsored by:
Chip Estimate
EDA Consortium
Silicon Valley Bank


Qualcomm Meets Jerry Sanders at 28nm

Qualcomm Meets Jerry Sanders at 28nm
by Ed McKernan on 04-19-2012 at 8:26 pm

First the good news: 4G LTE design in activity is off the charts as OEMs building smartphones, tablets and Ultrabooks are buying into the capability for product rollouts that will occur starting in September. Now the bad news: there’s not enough to go around until probably well into 2013. For a Company sitting on over $26B in cash, twice as much as Intel, this is a disaster that didn’t have to happen. Now Qualcomm is in panic mode, as it must spend engineering resources and dollars taping out designs to alternative fabs (likely Global Foundries and Samsung). For this misstep, they will probably pay the price of throttling back the 28nm Snapdragon design win effort and hand over market share to Intel.

As mentioned in previous blogs that I have written, there really are only four players left in the semiconductor game outside of memory. It’s Intel, Samsung, Apple and Qualcomm. Of the four, Qualcomm has played the most risk-averse game of poker, not willing to make bets beyond a single penny ante. Qualcomm was satisfied for many years as TSMC’s largest customer, what could go wrong. Plenty. Like having to share the same leading edge factory capacity several times over with other sizeable fabless players (i.e. Altera, Xilinx, nVidia and Broadcom) including some who are your leading and future competitors.

TSMC can’t be faulted for tallying up every customers wafer forecast and dividing by three, four or even five to get to some reasonable expected market demand. But then nobody expected the “end of the world” economic situation in 2008-2009 followed by the Apple driven Mobile Tsunami of iPhones and iPADs that drove right through the downturn. Apple, though, had its supply chain covered with well-managed capacity build outs at Samsung and Toshiba. Vertical Integration is where we are at and Qualcomm is the only one who hasn’t figured it out.

Intel overbuilt on 22nm capacity knowing that a circuit breaker was going to trip with all their competitors tied into the same single Fab source called TSMC. Malcolm Penn of Future Horizons has a great pitch on this, which I highly recommend. The only way to avoid this trap is to return to the Jerry Sanders Real Men Have Fabs strategy. It is the way in which Qualcomm can break away from Broadcom, Marvell and Mediatek. It also is the only way Qualcomm has a shot of going mano-on-mano with Intel as the end game plays out these next 3-5 years.

Intel’s greatest leaps forward, as I witnessed in the 1990s , was when their competitors screwed up during the moment that they were making their own transition to a new process with a new product. The market jumped on the new product in a stepped function manor and demand went through the roof. Everything a day old was immediately obsolete rotting in the channels. I am thinking about the transition from Pentium to Pentium MMX in the mid 1990s as an example.

In the earnings conference call, there was a moment when Steven Mollenkopf, President and COO of Qualcomm said: “Now in some cases also, our OEM partners are, of course, working with us very closely to try to help us accelerate our own supply.” I take this to mean Apple is stepping in to open doors at Samsung in order for Qualcomm to tape out a part that will only go in the iPhone 5. It is a weak position to be in when your customer is needed to open the doors to new capacity. This is likely to be paid back with a pound of flesh.

For those who a year ago thought that the ARM camp was on its way to dethroning Intel and all the pieces were in place, it is time to adjust to the reality that having a Fab Matters, now more than ever. Qualcomm, at roughly half the sales of Intel needs to write a $5B check for a New Fab starting immediately.

FULL DISCLOSURE: I am long AAPL, INTC, QCOM and ALTR


"Mechanics of Creativity" at DAC 2012: Oxymoron?

"Mechanics of Creativity" at DAC 2012: Oxymoron?
by Holly Stump on 04-19-2012 at 8:13 pm

A perennial DAC highlight for me is the panel session sponsored by Women in Electronic Design. This year, it is called “The Mechanics of Creativity: What does it take to be an idea machine?”

Is this an oxymoron?

I interviewed panelist Dee McCrorey , Chief Risk Guru and Innovation Catalyst at Risktaking for Success LLC, to find out.

“Mechanics /Creativity” and “Idea / Machine” seem like oxymorons, but are they?

I think it is an interesting juxtaposition of concepts, a creative one! Mechanics can mean:
• Functional side of mechanics (“mechanics of the brain”)
• Mechanics associated with physical science that deals with energy and its effect on bodies
• Mechanics and the practical application of machines or tools

I like to think of creativity as energy. But creativity by itself is fleeting. We can no longer wait for our muse to visit us. Mechanics of creativity can develop the “on-demand muse,” and we do this by developing a creative mindset that provides us with a continuous source of energy. A creative mindset “feeds” us on a regular basis and eliminates the need to unblock creatively. By integrating the components of a creative mindset these “packets of energy” become part of your creative DNA—you always have something in the creative hopper.

Ron Adner’s book The Wide Lenssays: “Invention used to be 1 percent inspiration and 99 percent perspiration. These days, it’s probably 50 percent collaboration. Companies trying to commercialize innovations won’t succeed unless suppliers, distributors, and other partners can and will do their parts.”

Is creativity a province of “artistic/ intuitive” people, as opposed to “analytical people” or can everyone be creative? Might analytics even have special strengths when they allow themselves to be creative?

Contemplation is not just for introverts. Success in the new world of business demands “whole brain” thinking–people who use the full functionality of their brain; cross back and forth between that of “thinker” and “creative.” These “whole brain adaptives” will model the best in “flexible mindset” thinking. Ambivert: a person who is intermediate between an extrovert and an introvert.

All energy begins with us, but when we expand energy it gains traction and grows stronger. Think about the last time you experienced a “collaborative high,” that buzz you got when you produced something greater than anything you could have done alone. That’s expansion of energy.

Collaboration is a timing thing—bring it in too soon and you risk vetting before you’ve had a chance to fully juice your idea—this is why contemplation and alone time is so important.

“Time to market /Creative flow” are challenging to balance. Thoughts?

At a time when we’re being called on to solve big, complex problems and to innovate at a faster clip we can’t afford to scatter our energies.

In my book, Innovation in a Reinvented World: 10 Essential Elements to Succeed in the New World of Business, Steve Todd, EMC Distinguished Engineer, shares his advice for professionals in preparing them to succeed in the new world of business: “Learn how to think—just think. Set aside time to just be still…The most complex problems will be solved by the “thoughtful ones,” people who just put their feet on the desk and think about solving big problems. The thoughtful employees will survive and thrive in future.”

For more information on Dee McCrorey
For more information on the “Mechanics of Creativity”Pavilion Panel

Join panelists Dee McCrorey of Success LLC, Lillian Kvitko of Oracle, Sherry Hess of AWR, and moderator Karen Bartleson of Synopsys on Monday June 4, at DAC 2012!



The Carbon Decade

The Carbon Decade
by Paul McLellan on 04-19-2012 at 6:00 am

Carbon Design Systems celebrates its 10th anniversary this month. It is a celebration that the company has survived a decade but also bittersweet that the company hasn’t been acquired for a juicy premium. But we just have to accept that EDA is not a business where you can throw together a company in 18 months and sell it for $1B before it makes its first dollar of revenue.

Like any company that has survived for ten years, its mission has changed somewhat. Carbon started life with technology for taking RTL, throwing away detail, and producing C-based models that ran much faster. The models were described as ‘carbonized.’ I think it is great marketing to have a company name that can be used as a verb, although of course there are risks with trademarks since they are only meant to be used as adjectives (like “I copied it using a Xerox brand photocopier” hmm).

But that initial technology has evolved to include the entire system validation ecosystem including embedded software, microprocessors and the rest of the underlying system.

In 2008, Carbon redefined itself as a virtual prototyping company when it acquired SoCDesigner from ARM (who had themselves purchased Axys four years earlier). Using the carbonizing technology they could compile ARM’s RTL code into 100% accurate virtual models, replacing the previous approach (ARMulator etc) of hand-written models.

In 2010 they unveiled Carbon IP Exchange. The Achilles heel of virtual platforms has always been the availability of models since many of the economic and the time-to-market benefits of virtual platforms evaporate if you have to spend too many dollars and too much time creating models. Now through portals like IP Exchange and the Synopsys TLMCentral that problem is starting to be solved, at least for the most common processors and their peripheral families.

The virtual platform space used to be quite crowded but Synopsys purchased Virtio, VaST and CoWare and Intel/WindRiver purchased Virtutech. Carbon (and Imperas) are the only independent company left standing. Bill Neifert, the original founder, is still there too, ten years later, now its CTO. Here’s his blog on the anniversary.