New ARC VPX DSP IP provides parallel processing punch

New ARC VPX DSP IP provides parallel processing punch
by Tom Simon on 10-29-2019 at 6:00 am

The transition to the digital age from a mostly analog world really began with the invention of the A-to-D and D-to-A converters. However scalar processors can easily be overwhelmed by the copious data produced by something as simple as an audio stream. To solve this problem and to really jumpstart the digital age, the development… Read More


New CEVA X baseband architecture takes on multi-RAT

New CEVA X baseband architecture takes on multi-RAT
by Don Dingee on 02-18-2016 at 4:00 pm

What we think of as a “baseband processor” for cellular networks is often comprised of multiple cores. Anecdotes suggest to handle the different signal processing requirements for 2G, 3G, and 4G networks, some SoC designs use three different DSPs plus a control processor such as an ARM core. That’s nuts. What is the point of having… Read More


Vector DSP IP charts course for IoT/M2M

Vector DSP IP charts course for IoT/M2M
by Don Dingee on 11-18-2015 at 4:00 pm

For some time, we’ve been talking about ideas for IoT-specific chips, evolved from garden-variety MCUs or mobile SoCs. I sat in on a fascinating talk from an MCU vendor at ARM TechCon 2015 regarding multi-protocol radio silicon, and a question kept coming from the audience: what about software-defined modems? The vague response… Read More