My name is Sagar, and I’ve been a long-time executive in the semiconductor manufacturing world — holding key positions at large multi-nationals, a leading semiconductor foundry, and partnering with many of the top-tier foundries and OSATs. Since “retiring”, I’ve also spent time advising and investing in start-ups through … Read More
Tag: tsmc
Chip Train Wreck Worsens
-Semi Equip go from bad to worse as TSMC cuts capex
-Numbers will be slashed for December quarter
-So far just a handful of exceptions to blockade but temporary
-China’s response could be very ugly
Fast motion train wreck
Just when some people thought that Fridays department of commerce announcement couldn’t get worse,… Read More
TSMC 2022 Open Innovation Platform Ecosystem Forum Preview
One of my favorite events is just around the corner and that is the TSMC OIP Ecosystem Forum and it’s at my favorite Silicon Valley venue the Santa Clara Convention Center. Nobody knows more about the inner workings of the ecosystem than TSMC so this is the premier semiconductor collaboration event, absolutely.
In my 40 years as a … Read More
Micron and Memory – Slamming on brakes after going off the cliff without skidmarks
-Micron slams on the brakes of capacity & capex-
-But memory market is already over the cliff without skid marks
-It will likely take at least a year to sop up excess capacity
-Collateral impact on Samsung & others even more important
Micron hitting the brakes after memory market already impacts
Micron capped off an otherwise… Read More
Ansys’ Emergence as a Tier 1 EDA Player— and What That Means for 3D-IC
Over its 40+ year history, electronic design automation (EDA) has seen many companies rise, fall, and merge. In the beginning, in the 1980s, the industry was dominated by what came to be known as the big three — Daisy Systems, Mentor Graphics, and Valid Logic (the infamous “DMV”). The Big 3 has morphed over the years, eventually settling… Read More
Application-Specific Lithography: 5nm Node Gate Patterning
It has recently been revealed that the N5 node from TSMC has a minimum gate pitch of 51 nm [1,2] with a channel length as small as 6 nm [2]. Such a tight channel length entails tight CD control in the patterning process, well under 0.5 nm. What are the possible lithography scenarios?
Blur Limitations for EUV Exposure
A state-of-the-art
Does SMIC have 7nm and if so, what does it mean
Recently TechInsights analyzed a Bitcoin Miner chip fabbed at SMIC and declared SMIC has a 7nm process. There has been some debate as to whether the SMIC process is really 7nm and what it means if it is 7nm. I wanted to discuss the case for and against the process being 7nm, and what I think it means.
First off, I want to say I am not going … Read More
The Semiconductor Cycle Snowballs Down the Food Chain – Gravitational Cognizance
-Where are we in the chip cycle? Why is it different this time?
-No one rings a bell to indicate the top or bottom of a cycle
-Could the lack of self-awareness lead to a worse downturn?
-Who will weather the cycle better & come out on top
Gravitational Cognizance
“A cartoon character will not fall until they realize they should
… Read More
Automotive Semiconductor Shortage Over?
Several signs point to an easing of the shortages of semiconductors for automotive applications. However, the production of light vehicles will likely remain below full potential through at least 2023. LMC Automotive’s July forecast of light vehicle production called for 81.7 million units in 2022, up 2% from 2021. LMC’s January… Read More
Intel and TSMC do not Slow 3nm Expansion
The media has gone wild over a false report that Intel and TSMC are slowing down 3nm. It is all about sensationalism and getting clicks no matter what damage is done to the hardworking semiconductor people, companies and industry as a whole. And like lemmings jumping off a cliff, other less reputable media outlets perpetuated this… Read More
