Update on SystemC for High-Level Synthesis

Update on SystemC for High-Level Synthesis
by Tom Dillinger on 03-26-2019 at 12:00 am

The scope of current system designs continues to present challenges to verification and implementation engineering teams. The algorithmic complexity of image/voice processing applications needs a high-level language description for efficient representation. The development and testing of embedded firmware routines… Read More


Project Verification Planning for Analog Designs

Project Verification Planning for Analog Designs
by Tom Dillinger on 02-18-2019 at 12:00 pm

Successful projects leverage the investment in comprehensive methodology and resource planning, covering design and analysis flows – that planning effort is especially important for functional verification.

The emergence of complex SoC designs for advanced automotive applications has led to a major focus on verification… Read More


Architecture for Machine Learning Applications at the Edge

Architecture for Machine Learning Applications at the Edge
by Tom Dillinger on 10-31-2018 at 2:01 pm

Machine learning applications in data centers (or “the cloud”) have pervasively changed our environment. Advances in speech recognition and natural language understanding have enabled personal assistants to augment our daily lifestyle. Image classification and object recognition techniques enrich our social media experience,… Read More


The Latest in Parasitic Netlist Reduction and Visualization

The Latest in Parasitic Netlist Reduction and Visualization
by Tom Dillinger on 10-22-2018 at 12:00 pm

The user group events held by EDA companies offer a unique opportunity to hear from designers and CAD engineers who are actually using the EDA tools “in the trenches”. Some user presentations are pretty straightforward – e.g., providing a quality-of-results (QoR) design comparison when invoking a new tool feature added to a recent… Read More


Advanced Materials and New Architectures for AI Applications

Advanced Materials and New Architectures for AI Applications
by Tom Dillinger on 10-17-2018 at 7:00 am

Over the past 50 years in our industry, there have been three invariant principles:

  • Moore’s Law drives the pace of Si technology scaling
  • system memory utilizes MOS devices (for SRAM and DRAM)
  • computation relies upon the “von Neumann” architecture
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Top 10 Highlights from the TSMC Open Innovation Platform Ecosystem Forum

Top 10 Highlights from the TSMC Open Innovation Platform Ecosystem Forum
by Tom Dillinger on 10-09-2018 at 7:00 am

Each year, TSMC hosts two major events for customers – the Technology Symposium in the spring, and the Open Innovation Platform Ecosystem Forum in the fall. The Technology Symposium provides updates from TSMC on:
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Neural Network Efficiency with Embedded FPGA’s

Neural Network Efficiency with Embedded FPGA’s
by Tom Dillinger on 09-21-2018 at 12:00 pm

The traditional metrics for evaluating IP are performance, power, and area, commonly abbreviated as PPA. Viewed independently, PPA measures can be difficult to assess. As an example, design constraints that are purely based on performance, without concern for the associated power dissipation and circuit area, are increasingly… Read More


Analytics and Visualization for Big Data Chip Analysis

Analytics and Visualization for Big Data Chip Analysis
by Tom Dillinger on 08-28-2018 at 12:00 pm

Designers require comprehensive logical, physical, and electrical models to interpret the results of full-chip power noise and electromigration analysis flows, and subsequently deduce the appropriate design updates to address any analysis issues. These models include: LEF, DEF, Liberty library models (including detailed… Read More


TSMC GlobalFoundries and Samsung Updates from 55DAC

TSMC GlobalFoundries and Samsung Updates from 55DAC
by Daniel Nenni on 08-20-2018 at 7:00 am

One of my favorite traditions at the Design Automation Conference is the Synopsys foundry events (the videos are now available). I learned a long time ago that the foundries are the foundation of the fabless semiconductor ecosystem and your relationships with the foundries can make or break you, absolutely. I also appreciate … Read More


An update on the Design Productivity Gap

An update on the Design Productivity Gap
by Tom Dillinger on 08-03-2018 at 12:00 pm

Over a decade ago, a group of semiconductor industry experts published a landmark paper as part of the periodic updates to the International Technology Roadmap for Semiconductors, or ITRS for short (link). The ITRS identified a critical design productivity gap. The circuit capacity afforded by the Moore’s Law pace of technology… Read More