Top 10 Highlights of the TSMC 2018 Technology Symposium

Top 10 Highlights of the TSMC 2018 Technology Symposium
by Tom Dillinger on 05-04-2018 at 12:00 pm

Here are the Top 10 highlights from the recent TSMC 2018 Technology Symposium, held in Santa Clara CA. A couple of years ago, TSMC acknowledged the unique requirements of 4 different market segments, which has since guided their process development strategy — Mobile, High-Performance Computing (HPC), Automotive, and… Read More


Hard IP for an embedded FPGA

Hard IP for an embedded FPGA
by Tom Dillinger on 04-30-2018 at 12:00 pm

As Moore’s Law enables increased integration, the diversity of functionality in SoC designs has grown. Design teams are seeking to utilize outside technical expertise in key functional areas, and to accelerate their productivity by re-using existing designs that others have developed. The Intellectual Property (IP) industry… Read More


Configurability for Embedded FPGA Hard IP

Configurability for Embedded FPGA Hard IP
by Tom Dillinger on 03-27-2018 at 12:00 pm

IP providers need to evaluate several complex engineering problems when addressing customer requirements – perhaps the most intricate challenge is the degree of IP configurabilityavailable to satisfy unique customer applications. … Read More


An OSAT Reference Flow for Complex System-in-Package Design

An OSAT Reference Flow for Complex System-in-Package Design
by Tom Dillinger on 03-09-2018 at 12:00 pm

With each new silicon process node, the complexity of SoC design rules and physical verification requirements increases significantly. The foundry and an EDA vendor collaborate to provide a “reference flow” – a set of EDA tools and process design kit (PDK) data that have been qualified for the new node. SoC design methodology … Read More


IPC-2581: The Standard for PCB Data Exchange

IPC-2581: The Standard for PCB Data Exchange
by Tom Dillinger on 02-19-2018 at 12:00 pm

The motivations to establish an industry standard data format are varied:

[LIST=1]

  • solidify a “de facto” standard, transitioning its evolution and support from a single company to an industry consortium;
  • aggregate disparate sources of design and manufacturing data into a single representation, with documented semantics;
  • Read More

    Adapting an embedded FPGA for Aerospace Applications

    Adapting an embedded FPGA for Aerospace Applications
    by Tom Dillinger on 01-30-2018 at 4:00 pm

    The IC industry is commonly divided into different market segments – consumer, mobile, industrial, commercial, medical, automotive, and aerospace. A key differentiation among these segments is the characterization and reliability qualification strategy for the fabrication process and design circuitry. For each segment,… Read More


    Scoreboard and Issues Management Tools for PCB Projects

    Scoreboard and Issues Management Tools for PCB Projects
    by Tom Dillinger on 01-16-2018 at 12:00 pm

    The complexity of an SoC design necessitates that the project managers have accurate visibility into the overall design status, spanning the entire range of tasks – from functional simulation error triage, to physical layout verification errors, to electrical analysis results. Flow scripts used by SoC teams parse the log file… Read More


    "The Year of the eFPGA" 2017 Recap

    "The Year of the eFPGA" 2017 Recap
    by Tom Dillinger on 12-22-2017 at 7:00 am

    This past January, I had postulated that 2017 would be the “Year of the Embedded FPGA”, as a compelling IP offering for many SoC designs (link). As the year draws to a close, I thought it would be interesting to see how that prediction turned out.

    The criteria that would be appropriate metrics include: increasing capital investment;… Read More


    7nm SERDES Design and Qualification Challenges!

    7nm SERDES Design and Qualification Challenges!
    by Daniel Nenni on 11-22-2017 at 7:00 am

    Semiconductor IP is the fastest growing market inside the fabless ecosystem, it always has been and always will be, especially now that non-traditional chip companies are quickly entering the mix. Towards the end of the year I always talk to the ecosystem to see what next year has in store for us and 2018 looks to be another year of … Read More


    Design for Manufacturability Analysis for PCB’s

    Design for Manufacturability Analysis for PCB’s
    by Tom Dillinger on 09-29-2017 at 7:00 am

    Chip designers are familiar with the additional physical design checking requirements that were incorporated into flows at advanced process nodes. With the introduction of optical correction and inverse lithography technology applied during mask data generation, and with the extension of a 193nm exposure source to finerRead More