CEO Interview: Srinath Anantharaman of ClioSoft

CEO Interview: Srinath Anantharaman of ClioSoft
by Daniel Nenni on 02-20-2017 at 7:00 am

It will soon be 20 years since ClioSoft started its journey of selling design management software for the semiconductor industry. It was a slow start considering that designs were relatively small and only digital front-end designers had begun to realize the importance of version control and design management. With open source… Read More


Using HSPICE StatEye to Tackle DDR4 Rail Jitter

Using HSPICE StatEye to Tackle DDR4 Rail Jitter
by Tom Simon on 02-15-2017 at 12:00 pm

The world is a risky place, according to Scott Wedge, Principal R&D Engineer at Synopsys, who presented at the Synopsys HSPICE SIG on Feb 2[SUP]nd[/SUP] in Santa Clara. Indeed, the world circuit designers face can be uncertain. Dealing with risk and departure from ideal was a main theme in the fascinating talks at this dinner… Read More


FPGA Design Gets Real

FPGA Design Gets Real
by Tom Simon on 02-08-2017 at 12:00 pm

FPGA’s have become an important part of system design. It’s a far cry from how FPGA’s started out – as glue logic between discrete logic devices in the early days of electronic design. Modern day FPGA’s are practically SOC’s in their own right. Frequently they come with embedded processor cores, sophisticated IO cells, DSP,… Read More


SPIE Advanced Lithography and Synopsys!

SPIE Advanced Lithography and Synopsys!
by Daniel Nenni on 02-01-2017 at 7:00 am

SPIE is the premier event for lithography held in Silicon Valley and again Scotten Jones and I will be attending. EUV is generally the star of the show and this year will be no different now that TSMC has committed to EUV production in 2019.

Last year at SPIE, TSMC presented the history of EUV development from the beginning in 1985 as … Read More


Four Steps for Logic Synthesis in FPGA Designs

Four Steps for Logic Synthesis in FPGA Designs
by Daniel Payne on 01-30-2017 at 12:00 pm

I remember meeting Ken McElvain at Silicon Compilers for the first time back in the 1980’s, he was a gifted EDA tool developer that did a lot of coding including logic synthesis, a cycle-based simulator and ATPG. Mentor Graphics acquired Silicon Compilers with Ken included, and he continued to create another logic synthesis… Read More


Nvidia Drives into New Market with Deep Learning and the Drive PX 2

Nvidia Drives into New Market with Deep Learning and the Drive PX 2
by Tom Simon on 12-03-2016 at 7:00 am

Nvidia has found that video games are the perfect metaphor for autonomous driving. To understand why this is so relevant you have to realize that the way self-driving cars see the world is through a virtual world created in real time inside the processors used for autonomous driving – very much like a video game. It’s a little bit like… Read More


Expert Interview: Rajeev Madhavan

Expert Interview: Rajeev Madhavan
by Daniel Nenni on 11-29-2016 at 12:00 pm

This blog was originally posted on Paysa.com but since Rajeev Madhavan is one of our EDA Heroes I thought it was worth a re-post. In case you do not know Rajeev, he started his EDA career at Cadence then was co-founder and VP of Engineering at LogicVision (acquired by Mentor). Next he was Founder, President, and Chairman of Ambit Design… Read More


ATPG, Automotive and 7nm FinFET

ATPG, Automotive and 7nm FinFET
by Daniel Payne on 11-22-2016 at 4:00 pm

The state of Texas hosted two or our industry’s big technical conferences and trade shows this year: DAC and ITC (International Test Conference). IC designers know about DAC in Austin, and test engineers know about ITC in Dallas. I travelled to Austin to cover DAC this past summer, and I was able to connect with Robert Ruiz … Read More


Ford Motors Discusses Future Mobility Trends at Synopsys Seminar

Ford Motors Discusses Future Mobility Trends at Synopsys Seminar
by Tom Simon on 11-17-2016 at 4:00 pm

Five or ten years ago it would have been hard to imagine someone from Ford Motors giving the keynote at a technology summit at a major EDA company like Synopsys. However, on November 2[SUP]nd[/SUP], Synopsys hosted a seminar on the topic of Automotive Architecture Design and System Testing, and Ford Technical Fellow Jim Buczkowski… Read More


FPGAs allow customization of SEU mitigation

FPGAs allow customization of SEU mitigation
by Don Dingee on 11-16-2016 at 4:00 pm

Teams working on avionics, space-based electronics, weapons delivery systems, nuclear generating plants, medical imaging equipment, and other applications where radiation leads to single-event upsets (SEU) are already sensitive to functional safety requirements. What about automotive applications?

With electronic… Read More