The TSMC OIP Ecosystem Forum is upon us again. I have yet to meet a disappointed attendee so it is definitely worth your time: Networking with more than 1,000 semiconductor professionals, the food, mingling with the 50+ EDA, IP, and Services Companies, the food, and of course the content. The 7nm and 7nm EUV updates alone are worth… Read More
Tag: synopsys
HBM offers SOC’s dense and fast memory options
Dual in-line memory modules (DIMM’s ) with double data rate synchronous dynamic random access memory (DDR SDRAM) have been around since before we were worried about Y2K. Over the intervening years this format for provisioning memory has evolved from supporting DDR around 1995, to DDR1 in 2000, DDR2 in 2003, DDR4 in 2007 and DDR4… Read More
HLS update from Mentor about Catapult
I recall back in the late 1980’s when logic synthesis tools were first commercialized, at first they could read in a gate-level netlist from one foundry then output an optimized netlist back into the same foundry. Next, they could migrate your gate-level netlist from Vendor A over to Vendor B, giving design companies some… Read More
LETI Days 2017: FD-SOI, Sensors and Power to Sustain Auto and IoT
I have attended last week to the LETI Days in Grenoble, lasting two days to mark the 50[SUP]th[/SUP] anniversary of the CEA subsidiary. Attending to the LETI Days is always a rich experience: LETI is a research center counting about 3000 research engineers, but LETI is also a start-up nursery. The presentations are ranging from … Read More
ARM, Infineon, Synopsys, SK Hynix talk AMS Simulation
Every SoC that connects to an analog sensor or device requires AMS (Analog Mixed-Signal) circuit simulation for design and verification, so this year at #54DAC the organizers at Synopsys hosted another informative AMS panel session over lunch time on Monday. What makes this kind of panel so refreshing is that the invited speakers… Read More
First Thoughts from #54DAC!
This was my 34[SUP]th[/SUP] DAC, yes 34. It is a shame blogging did not exist back then because I would have liked to have read thoughts from my eager young mind, or maybe not. The first thing that struck me this year is the great content. Before DAC I review the sessions I want to see and this year there were many more than I had time for. … Read More
Don’t Miss “The IP Paradox” Panel @ #54 DAC!
Despite the strong consolidation in the semiconductor industry, the Design IP market is still growing: from $3 billion in 2015 to $3.4 billion in 2016. That’s why the DAC IP Committee has organized this panel, titled “The IP Paradox: Growing Business Despite Consolidations” (you can see more on the events page: https://dac.com/events… Read More
AIM Photonics Catching Its Stride as They Move into 2nd Year
AIM Photonics held its 2017 Proposers Meetings on May 24[SUP]th[/SUP] in Rochester, NY. The meetings included a review of AIM’s progress and strategic direction by their TRB (technical review board) and a session targeted at PIC (photonic integrated circuit) design for multi-project wafer (MPW) runs. While these discussions… Read More
FD-SOI in Japan?
If you want to get your finger on the Japan FD-SOI pulse, registration is still open for a free, two-day workshop in Tokyo this week organized by the SOI Consortium. This is the 3rd Annual SOI Tokyo Workshop, and there’s a really interesting line-up of speakers.
In case you’re wondering, Japan is doing FD-SOI. In fact… Read More
CDC Verification for FPGA – Beyond the Basics
FPGAs have become a lot more capable and a lot more powerful, more closely resembling SoCs than the glue-logic we once considered them to be. Look at any big FPGA – a Xilinx Zynq, an Intel/Altera Arria or a Microsemi SmartFusion; these devices are full-blown SoCs, functionally different from an ASIC SoC only in that some of the device… Read More