Every SoC that connects to an analog sensor or device requires AMS (Analog Mixed-Signal) circuit simulation for design and verification, so this year at #54DAC the organizers at Synopsys hosted another informative AMS panel session over lunch time on Monday. What makes this kind of panel so refreshing is that the invited speakers are all users of EDA circuit simulators and responsible for AMS IP or chip design. The panel moderator was Farhad Hayat of Synopsys and he gave a brief overview of the SPICE and FastSPICE circuit simulators and how Custom Designer is being used for IC layout. The mantra for 2017 at Synopsys for AMS design is:
- Physically aware IC design (early layout parasitics into SPICE)
- Visually assisted IC layout (templates make you more productive)
- Reliability aware (Monte Carlo simulations, EM and IR analysis)
Sibaek Jung from the CAD Engineering Group was the first panelist to present on the challenges of DRAM design, and their company is #2 in the DRAM market behind #1 Samsung, and ahead of #3 Micron. SK Hynix also designs HBM (High Bandwidth Memory), NAND storage and CMOS image sensors.
Circuit design challenges for DRAM include:
- Coupling capacitors (198.1M parasitic capacitors)
- Slower run times with SPICE
- Simulation of an 8GB design is 2.3X slower than for a 4GB design
- Power-up simulations can take up to 168 hours
To meet these challenges they used the FineSim circuit simulator (acquired from Magma in November 2011) and traded off simulation speed versus accuracy using the ccmodel simulator setting. Running FineSim on 8 cores they saw an increase in speeds of 2-3.4X and were able to get long simulation run times down to a more manageable 17 hours. Even the power-up simulation run times used to take 4 days but now can be speeded up using partitioning and event control by 4X to 10.9X.
This company is most famous for their processor IP business and Tom Mahatdejkul revealed a technique called Large Scale Monte Carlo (LSMC) with the HSPICE circuit simulator.
LSMC is a new feature in HSPICE to manage and dramatically reduce the amount of data created during Monte Carlo runs. At ARM they use this feature for circuit simulation with under 1million runs.
The accuracy of LSMC versus non-LSMC are similar, and so are the run times, the big difference is the amount of disk space used up with the output files. They are reporting30,000X smaller total file size (3.3GB vs 112KB, 26 transistor, 68 nodes, 1 .meas statement) for a logic test cell.
On a memory cell they saw the output file size with LSMC get reduced to just 707KB, versus the non-LSMC size of 2.8GB.
Standard cell libraries are characterized with HSPICE across multiple PVT corners, so disk space is a big deal. ARMr really needs data efficiency for a Monte Carlo approach to be viable. So with LSMC they could characterize a 100 cell library using only 78.4MB of disk space, versus the previous approach which bloated out to 2.31TB disk usage.
With LSMC they are able to run more cells under more corners than before.Now they can run 1M to 10M SPICE runs using LSMC.
Measurements showed that they use the same amount of RAM with LSMC versus non-LSMC. LSMC provides statistical data results, but it is not saving as many data run points.
There’s an internal physical IP group at Synopsys and Marco Oliveira talked about their CAD flows and methodologies to support 2,700 engineers worldwide. Marco’s background includes A2D and D2A converters.
For high yield design they need to simulate across multiple process corners, however Monte Carlo simulations just take too long, so instead they limit their sample size and extract the results. Their approach is called sigma scaling. In one example for an RX termination circuit they did 1,000 MonteCarlo runs with no scaling, then re-ran agin needing just 200 runs with sigma scaling.
As a best practice they use sigma scaling with a factor up to 2, using only 200 simulation runs or more. This technique works with all of their circuit simulators: HSPICE, FineSim and CustomSim.
Our final panelist was Haiko Morgenstern, an MS verification engineer from Infineon based in Munich, Germany. Their company is large with some 40,000 people and they have products in Mobility (Auto), Security (ID cards, NFC), and energy efficiency.
One of their big challenges is how to verify MS designs. They have used UVM testbenches, real number modeling, and UPF for implementation and verification. For verification they are running MonteCarlo simulations with CustomSim and VCS AMS.
On a recent ADC verification there were up to 1 million elements, so CustomSim handles this capacity and can simulate in about 30 minutes run time. The verification engineers can define which block uses which modeling abstraction (transistor, SPICE behavioral, Verilog-A, RTL).Variation block MC is now available in CustomSim runs.
The output results have statistical values as text along with the typical waveforms.Infineon uses scripts to automate the simulation process, and use LSF to distribute jobs across a compute farm. They cando 200 MC runs overnight using LSF on a 1 million element netlist, but they haven’t tried sigma scaling yet.
Synopsys has a family of three circuit simulators: HSPICE, FineSim and CustomSim. The SPICE and FastSPICE market continues to be fiercely competitive, so to stay viable each vendor has to show constant improvement with each new release of their tools. HSPICE got started back in the 1980’s, and over the decades has been able to stay relevant amidst newer tools by adding new features and refactoring the code to be more efficient. FineSim was an early SPICE simulator to exploit parallelism, and CustomSim is the newest simulator offered by Synopsys in the FastSPICE space.