There was a lot to learn at the TSMC Technical Symposium last week, in the keynotes for sure but also in the halls and exhibits. Tom Dillinger did a nice job covering the keynotes in his posts Key Take aways from the TSMC Technology Symposium Part 1 and Part 2 but there was something interesting that many people may have missed in the exhibit… Read More
Tag: soc design
4 goals of memory resource planning in SoCs
The classical problem every MBA student studies is manufacturing resource planning (MRP II). It quickly illustrates that at the system level, good throughput is not necessarily the result of combining fast individual tasks when shared bottlenecks and order dependency are involved. Modern SoC architecture, particularly … Read More
Speaking about the Internet of Trust on April 21
Five minutes to ruin a reputation built over 20 years, as Warren Buffett put it, holds true in personal relationships. On the Internet of Things, reputations can disappear in five seconds. How do we move from merely intelligent Things to a level where devices have to be Trusted?… Read More
Creating a better embedded FPGA IP product
Our introduction to Flex Logix and its embedded FPGA core IP drew several comments, predominantly along the lines of a few things like this have been tried before. In this installment, we dive into the EFLX cores, the FPGA toolchain, the roadmap, and a powerful integration feature.… Read More
Post-making new Things stand out on the IoT
Sales says this next IoT project is going to be huge. Engineering isn’t so sure. Marketing says we should pilot it to find out. If it were just software, it might not be such a problem, but with hardware comes investment tradeoffs. Without guaranteed volumes of millions of units, are ASICs a realistic option to hit aggressive size,… Read More
Fastest SoC time-to-success: emulators, or FPGA-based prototypes?
Hardware emulators and FPGA-based prototyping systems are descendants of the same ancestor. The Quickturn Systems Rapid Prototype Machine (RPM) introduced in May 1988 brought an array of Xilinx XC3090 FPGAs to emulate designs with hundreds of thousands of gates. From there, hardware emulators and FPGA-based prototyping … Read More
Evaluating the Performance of Design Data Management Software
In the wake of increased global competitiveness and shorter time-to-market windows, there has been a renewed focus by design management on the underlying data management infrastructure of the design teams. An increasing number of systems-on-chip (SoCs) now have some type of analog, digital and/or RF modules, making it imperative… Read More
Maybe not the world, but schedules got eaten
It has been almost five years since Marc Andreessen wrote the words, “Software is eating the world.” The premise of his essay in the Wall Street Journal in 2011 was pretty simple: the technology world has seen its intrinsic value shift from hardware to software. New all-software names have appeared on the list of high flying companies,… Read More
Should there be a 5-second IoT chip rule?
Kids have a tendency to put things in their mouths. Any parent can relate to the statement, “Put that down! You don’t know where it’s been!” After the first child, concern usually relaxes quite a bit. People joke about a 5-second rule on the premise if an object was just dropped on the floor, it may not be contaminated yet.… Read More
Finding under- and over-designed NoC links
When it comes to predicting SoC performance in the early stages of development, most designers rely on simulation. For network-on-chip (NoC) design, two important factors suggest that simulation by itself may no longer be sufficient in delivering an optimized design.
The first factor is use cases. I think I’ve told the story … Read More