Webinar: Design Methodologies for Next-Generation Heterogeneously Integrated 2.5/3D-IC Designs

Webinar: Design Methodologies for Next-Generation Heterogeneously Integrated 2.5/3D-IC Designs
by Herb Reiter on 04-10-2020 at 6:00 am

2d 3d Semiconductor Packaging SemiWiki Cadence

I had the opportunity to preview the upcoming SemiWiki webinar titled: Design Methodologies for Next-Generation Heterogeneously Integrated 2.5/3D-IC Designs. John Park’s message, describing this powerful Cadence solution, really impressed me. That’s why I want to encourage you to register for it and join this SemiWiki … Read More


Why I’m Lowering Semiconductor Equipment Revenue Growth to -6.9% in 2020

Why I’m Lowering Semiconductor Equipment Revenue Growth to -6.9% in 2020
by Robert Castellano on 04-09-2020 at 10:00 am

Applied Materials Lam lower C2

Because of significant $4 billion in equipment pull-ins in Q4 from sales in Asia, I was reducing my semiconductor wafer front-end (WFE) equipment revenue growth from an earlier +5% to 0% in 2020. Now, based on CORVID-19, I am further reducing revenue growth to -6.9%.

Chart 1 also shows the cyclical nature of semiconductors and semiconductor… Read More


Newsflash Chip Equip Blockade Back on!

Newsflash Chip Equip Blockade Back on!
by Robert Maire on 03-29-2020 at 2:00 pm

US China Blockade


Blocking chip sales to Huawei back on front burner
Covid19 & China Trade are equally bad
Long lived Uncertainty could “plague” industry sales going forward
Political Predictability worse than Disease Predictability

Reuters broke a story today that the proposed licensing of chip equipment to prevent “bad… Read More


COVID-19 Chip Cycle – How deep, long and what shape?

COVID-19 Chip Cycle – How deep, long and what shape?
by Robert Maire on 03-26-2020 at 10:00 am

Covid 19 Semiconductors SemiWiki 1

It is a demand driven downturn – harder to predict
It may not be “business as usual” after this virus
What systemic changes could the industry face?

Trying to figure out another cycle-driven by inorganic catalyst

Investors and industry participants in the semiconductor industry who are used to normal cyclical… Read More


Low Energy Electrons Set the Limits for EUV Lithography

Low Energy Electrons Set the Limits for EUV Lithography
by Fred Chen on 03-25-2020 at 6:00 am

Low Energy Electrons Set the Limits for EUV Lithography

EUV lithography is widely perceived to be the obvious choice to replace DUV lithography due to the shorter wavelength(s) used. However, there’s a devil in the details, or a catch if you will.

Electrons have the last word
The resist exposure is completed by the release of electrons following the absorption of the EUV photon.… Read More


A Conversation with Wally Rhines: Predicting Semiconductor Business Trends After Moore’s Law

A Conversation with Wally Rhines: Predicting Semiconductor Business Trends After Moore’s Law
by Daniel Nenni on 03-22-2020 at 10:00 am

Cover Predicting Trends

Wally Rhines is one of the most prolific speakers the semiconductor industry has ever experienced. Wally is also one of the most read bloggers on SemiWiki.com, sharing his life’s story which is captured in his first book: From Wild West to Modern Life the Semiconductor Evolution.

On April 2nd at 10am PDT we will host Wally on a live… Read More


Semiconductor COVID-19 Update!

Semiconductor COVID-19 Update!
by Mark Dyson on 03-22-2020 at 10:00 am

COVID 19 Semiconductors SemiWiki

Last week whilst China started to recover from COVID-19 outbreak, the rest of the world was seriously impacted by the growing number of cases as the number of cases and deaths outside of China grew higher than in China. With the rise, many governments around the world belatedly put in measures to prevent the further spread of the … Read More


TSMC 32Mb Embedded STT-MRAM at ISSCC2020

TSMC 32Mb Embedded STT-MRAM at ISSCC2020
by Don Draper on 03-20-2020 at 6:00 am

Fig. 1. Cross section of the STT MRAM bit cell in BEOL metallization layers between M1 and M5.

32Mb Embedded STT-MRAM in ULL 22nm CMOS Achieves 10ns Read Speed, 1M Cycle Write Endurance, 10 Years Retention at 150C and High Immunity to Magnetic Field Interference presented at ISSCC2020

1.  Motivation for STT-MRAM in Ultra-Low-Leakage 22nm Process

TSMC’s embedded Spin-Torque Transfer Magnetic Random Access Memory (STT-MRAM)… Read More


COVID-19 and Semiconductors

COVID-19 and Semiconductors
by Bill Jewell on 03-18-2020 at 10:00 am

COVID 19 and semiconductors SemiWiki

The threat of COVID-19 (coronavirus) is continuing to spread. As of March 17, the World Health Organization (WHO) reported 179,111 confirmed cases and 7,426 deaths. WHO declared COVID-19 a pandemic as of March 11. Many countries have imposed severe restrictions to slow the spread of the disease, ranging from banning of large … Read More


TSMC’s 5nm 0.021um2 SRAM Cell Using EUV and High Mobility Channel with Write Assist at ISSCC2020

TSMC’s 5nm 0.021um2 SRAM Cell Using EUV and High Mobility Channel with Write Assist at ISSCC2020
by Don Draper on 03-06-2020 at 6:00 am

Fig. 1 Semiconductor Technology Application Evolution

Technological leadership has long been key to TSMC’s success and they are following up their leadership development of 5nm with the world’s smallest SRAM cell at 0.021um 2 with circuit design details of their write assist techniques necessary to achieve the full potential of this revolutionary technology. In addition to their… Read More