Webinar: Target Optimal PPA and Faster Time-to-Market Using Synopsys Cloud Digital SaaS Instance

Webinar: Target Optimal PPA and Faster Time-to-Market Using Synopsys Cloud Digital SaaS Instance
by Admin on 11-16-2022 at 10:42 am

Historically, the digital design process requires in-depth knowledge of each tool in the cycle. Getting up and running involves writing hundreds of lines of script. Many companies lack the resources or in-house expertise. This is where a cloud-based, expert-built digital design flow can deliver a big productivity lift. By

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Quadric’s Chimera GPNPU IP Blends NPU and DSP to Create a New Category of Hybrid SoC Processor

Quadric’s Chimera GPNPU IP Blends NPU and DSP to Create a New Category of Hybrid SoC Processor
by Kalar Rajendiran on 11-01-2022 at 10:00 am

Memory Optimization Equals Power Minimization

Performance, Power and Area (PPA) are the commonly touted metrics in the semiconductor industry placing PPA among the most widely used acronyms relating to chip development. And rightly so as these three metrics greatly impact all electronic products that are developed. The degree of impact depends of course on the specific … Read More


CadenceCONNECT: Building Arm Compute with Cadence Digital Full Flow for Best PPA

CadenceCONNECT: Building Arm Compute with Cadence Digital Full Flow for Best PPA
by Admin on 04-04-2021 at 11:03 am

Arm’s Total Compute approach addresses many different requirements, from low-power edge devices with adequate performance, to data center class processors delivering the highest possible compute throughput. To realize these requirements, there must be a massive shift in the approach to system-on-chip (SoC) design.

CadenceCONNECT:

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CadenceCONNECT: Building Arm Compute with Cadence Digital Full Flow for Best PPA

CadenceCONNECT: Building Arm Compute with Cadence Digital Full Flow for Best PPA
by Admin on 12-10-2020 at 8:54 am

Arm’s Total Compute approach addresses many different requirements, from low-power edge devices with adequate performance, to data center class processors delivering the highest possible compute throughput. To realize these requirements, there must be a massive shift in the approach to system-on-chip (SoC) design.

CadenceCONNECT:

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How ML Enables Cadence Digital Tools to Deliver Better PPA

How ML Enables Cadence Digital Tools to Deliver Better PPA
by Mike Gianfagna on 10-28-2020 at 10:00 am

How ML Enables Cadence Digital Tools to Deliver Better PPA

There has been a lot written about artificial intelligence/machine learning (AI/ML) and its application in the Cadence digital design flow. Most recently, I covered significant verification efficiency improvements in Xcellium ML.  A recent digital-themed white paper from Cadence takes a broader look at the impact of ML on… Read More


Webinar: Extending Innovation with Innovus 20.1 Release (Hebrew)

Webinar: Extending Innovation with Innovus 20.1 Release (Hebrew)
by Admin on 05-26-2020 at 11:42 pm

Overview

The Cadence® Innovus™ Implementation System continues to extend technology innovation to ensure designers can complete ever larger and more complex designs. During this webinar, Cadence will share the latest Innovus Implementation 20.1 release technology highlights.

Topics such as physically aware logic restructuring,

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Prevent and Eliminate IR drop and Power Integrity Issues using Redhawk Analysis Fusion

Prevent and Eliminate IR drop and Power Integrity Issues using Redhawk Analysis Fusion
by Admin on 03-14-2020 at 2:44 am

Tue, Mar 31, 2020 11:00 AM – 12:00 PM MDT

*** This webinar requires that you register with your work email address ***

As we move towards advanced nodes where supply voltage reduces and transistors shrink in size, reliability challenges increase significantly. Designers see more IR drop and power integrity issues, and we… Read More


Computer Vision Design with HLS

Computer Vision Design with HLS
by Bernard Murphy on 08-21-2018 at 7:00 am

I’m on a mini-roll on the subject of high-level design for ML-based systems. No complaints from me, this is one of my favorite domains and is certainly a hot area; it’s great to that EDA vendors are so active in advancing ML-based design. Here I want to talk about the Catapult HLS flow for use in ML design.

Since I’ve covered the ML topic… Read More


Webinar: High-Capacity Power Signoff Using Big Data

Webinar: High-Capacity Power Signoff Using Big Data
by Bernard Murphy on 11-07-2017 at 7:00 am

Want to know how NVIDIA signs off on power integrity and reliability on mega-chips? Read on.

PPA over-design has repercussions in increased product cost and potential missed schedules with no guarantee of product success. Advanced SoCs pack more functionality and performance resulting in higher power density, but traditional… Read More


Webinar: How RTL Design Restructuring Helps Meet PPA

Webinar: How RTL Design Restructuring Helps Meet PPA
by Bernard Murphy on 06-07-2017 at 7:00 am

To paraphrase an Austen line, it is a truth universally acknowledged that implementation, power intent and design hierarchy don’t always align very well. Hierarchy is an artifact of legacy structure, reuse and division of labor, perhaps well-structured piecewise for other designs but not necessarily so for the design you now… Read More