When it comes to building edge devices for the internet-of-things (IoT), you don’t want to have to break the bank to prototype an idea before diving into the deep water. At the same time, if your idea is to shrink an edge device down to it’s smallest dimensions, lowest power and lowest cost, you really want to be able to prototype your… Read More
In my 34 years in IC and EDA, it never ceases to amaze me as to how ingenious designers can be with what is given them. Mentor, a Siemens business, has released a wonderful white paper that is proof of this yet again. The white paper steps through how one of their customers, MEMSIC, used the Tanner tool suite to develop a combination CMOS… Read More
There has been quite a bit of coverage on this already but Bosch building a fab in Dresden is a big deal so let me share my experience, observation, and opinion as us bloggers do. The $1.1B question of course is: Why didn’t Bosch invest in GlobalFoundries FD-SOI fabs in Dresden instead? Automotive and IoT is perfect for FD-SOI,… Read More
As I write about integrated photonics I continue to hear from long-time experts in the field who lament that integrated photonics has been around for decades and other than telecom/datacom, it seems to never be a mainstream technology. It’s hard to argue that this time around it will be different as those people have lived through… Read More
Last Friday I learned something new about IoT by attending a SEMI event in Wilsonville, OR just a few short miles away from where I live in Tualatin. SEMI puts on two events here in Oregon each year, and their latest event on IoT Sensors was quite timely and popular judging by how many attendees showed up. First up was Jeff Miller from … Read More
IoT edge device design means four domains – MEMS, analog, digital, and RF – not only work together, but often live on the same die (or substrate in a 2.5D process) and are optimized for power and size. Getting these domains to work together effective calls for an enhanced flow.
Historically, these domains have not played together … Read More
We spend an inordinate amount of energy tracking the big chip – the application processor – in a mobile device. As we’ve seen this space is coming down to a handful of players. A more interesting competition is heating up around the APU for the rest of chips needed to make a phone.… Read More
The development of leading edge semiconductor technology is incredibly expensive, with estimates ranging from a few to several billion dollars for new nodes. The time to develop a leading edge process is also a critical competitive issue with some of the largest opportunities awarded based on who is first to yield on a new node.… Read More
It was the very first time I attended the LETI days, even if I know the research center for many years. LETI was created in the 60’s, as the subsidiary of the CEA (France agency in charge of Atomic Energy) in charge of Microelectronic. Now, for more than 50 years, 2000 research engineers are working to develop technologies, systems … Read More
Following Moore’s Law down to 10 or even 7 nm labeled feature size demands US $ hundreds of millions of up-front investment, a very large design team and two or more years of development time. These parameters suggest that it only makes sense for very high volume applications to continue on the shrink path to increase SoCs’ functionalities.… Read More
