Next Wednesday is the Common Platform Technology Forum. “Common Platform” is a name that only a committee could have come up with, giving no clue as to what it actually is. As you probably know, there are various process clubs sharing the costs of technology development (TD) and one of them consists of IBM, Samsung and… Read More
Next Tuesday and Wednesday, March 13-14th, is CDNLive in Silicon Valley at the DoubleTree Hotel (which I see we are now meant to call DoubleTree by Hilton, although I still have to think twice not to call it the Red Lion, the group whose CFO at one point was Ray Bingham who was CFO and then CEO of Cadence. Trivia fact for the day).
CDNlive… Read More
As I have been watching the developments in EDA and Semiconductor industry, it is apparent that we remain fragmented unless pushed to adopt a common standard mostly due to business reasons. Foundries are dictating on the rules to be followed by designs, thereby EDA tools incorporating them. Also, design companies needed to work… Read More
This year’s CEO forecast panel was held at Silicon Valley Bank. Bankers live better than verification engineers, as if you didn’t know, based on the quality of the wine they were serving compared to DVCon.
This year the panelists were Ed Cheng from Gradient, Lip-Bu, Aart and Wally (and if you don’t know who they… Read More
Last year, you could claim (like I did in this blog) that Cadence was making money with large VIP port-folio, when Synopsys was managing sales of a large Design IP port-folio (thanks to a successful acquisition strategy in the 2000’s). But the latest acquisitions made by Synopsys of VIP centric companies like nSys or ExpertIO should… Read More
And if, like me, you don’t go to MWC, that’s the right time to get your version of the MIPI IP survey, the 3[SUP]rd[/SUP] version since the first launch in 2010, because IPNEST will give you a good reason to buy it during MWC: you will get it at a lower price. That will apply now and during the event, but only from today, and up to the 3[SUP]rd[/SUP]… Read More
Nandu Bhagwan is CEO of GHz Circuits and has been designing PLL circuits used in ICs for the past 12 years. Mr. Bhagwan did a video interview with John Pierce of Cadence to talk about the challenges of PLL design.… Read More
Even if ExpertIO acquisition by Synopsys, coming after nSys acquisition a couple of months ago, will not have a major impact on Synopsys’ balance sheet, it will again change the Verification IP market landscape. The acquisition of Inventure, a subsidiary of Zuken, will have a major impact on the Interface IP market, even if it’s… Read More
Users of Cadence Virtuoso tools for IC layout and schematics can make their design flow easier by using Design Data Management tools from ClioSoft. Keeping track of versions across schematics, layout, IP libraries and PDKs can be daunting. Come and learn more about this at a Webinar hosted by ClioSoft next Tuesday.… Read More
DesignCon is coming up and the panel discussions look very interesting this year. The one panel session that I recommend most is called, “Analog and Mixed-Signal Design and Verification” which is moderated by Brian Bailey, one of my former Mentor Graphics buddies and fellow Oregonian.… Read More
