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SOC Prototyping with FPGAs from a Smaller Vendor

SOC Prototyping with FPGAs from a Smaller Vendor
by Daniel Payne on 03-23-2012 at 10:43 am

The two large EDA companies offering SOC prototyping with FPGA-based boards are Synopsys and Cadence, however there’s a smaller vendor called Polaris Design Systems that also have a product in this important design verification category. I spoke on Wednesday with Rahm Shastry, CEO of Polaris to learn more about this company and vision. Rahm and I both worked together at Viewlogic in the 90’s.


Q: What is the history of Polaris?
A: I worked at IRIS, an ASIC prototyping company a few years ago, then left in April 2011. Later they asked me to buy the company, so I did and re-named the new company Polaris. Our product has been around for awhile and is based on Altera’s Stratix IV FPGAs, proven, it works.

Q: Who are the competitors in FPGA-based prototyping?
A: There are several:

  • Synopsys has HAPS from Hardi/Synplicity (Xilinix Virtex 6 family).
  • Cadence has OEM of boards made by DINI group (San Diego), Rapid Prototyping Systems. Integrated with Paladium (large emulator), same database.
  • DINI Group, sells just the boards no SW, you are on your own.
  • S2C – A Shanghai-based product. Both Xilinx and Altera boards, successful in China.
  • Roll your own board with FPGAs.

Q: Which FPGA vendor is dominant in prototyping boards today?
A: Xilinx FPGA is a very popular prototyping choice, used by SNPS.

Q: Who is using the Polaris FPGA boards to prototype?
A: We have in Japan: Mitsubishi, Panasonic, Thine Electric and Sharp.

Q: How do engineers decide on a prototyping products?
A: Engineers typically choose their favorite FPGA company first, then buy a prototype system based on that FPGA architecture. The larger the FPGA the more gates, so you need fewer FPGAs to partition. Going from two to Four FPGAs on a board is a big step, so the complexity of partitioning matters. Most FPGAs are limited to 1,100 pins or so.

Q: Does Polaris have a partitioner between FPGAs?
A: For Polaris there is no partitioner, yet. Stay tuned.

Q: What should I look for in a prototype system?
A: Debug support is important – how easy is it to probe and do incremental compiles quickly. What final performance will your prototype runs at is high on the list.

Q: What other approaches are their to logical verification of an SOC?
A: SW Simulator (up to millions of gates), Emulator (good for entire chip), Prototype (run live video or data near speed). You could use each at a specific point in your verification.

Q: What kind of results are Polaris customers seeing?
A: Sharp has used our boards up to 150MHz, even with multiple boards. This allows them to quickly debug their SOC designs at near final product speeds. With an emulator you may get 1MHz or 2MHz of performance which is really kind of slow.

Q: Are those speeds typical?
A: Yes, in our office we have a demo running at 75MHz. A SW Simulator only reaches speeds of about 1KHz.

Q: Tell me more about your office demo.
A: Our demo is a DVD player running a movie (Spider Man) and the DVD output goes to a Polaris board which then converts the signal to a VGA output and displays it live on a screen. We can actually probe signals on the design and show waveforms with live data (sync, clocks). This demo board runs at 75MHz. You just cannot do that kind of speed with any emulator.

Q: What else could I prototype with Polaris?
A: You could run your SmartPhone and even take a phone call using this prototype.

Q: Do you have any plans to support Xilinx-based boards?
A: It’s possible and really depends on customer demand. Our goal is to be FPGA agnostic.

Q: What does Mentor have in this product area?
A: Nothing, yet.

Q: What capacities are there in FPGA devices now?
A: The Virtex 7 has 2 million LUT (10-12 gates), so 20-24 million gates. Two FPGAs gives you 48Million gates, and with that you can handle about 85% of all SOC designs.

Q: Who would be interested in prototyping?
A: SOC designers, because they have both verification pain and a budget.

Q:Why should I use a prototype system instead of just SW simulation?
A: How thoroughly can you verify RTL in SW alone? A few seconds of real HW will show way more results than any SW simulator could achieve in months or years.

Q: Can you share any pricing information?
A: Yes, our Pricing for a single FPGA (up to 15 million gates – Stratix IV) system, daughter cards (multimedia, etc), is $15K list. The multi FPGA board is a PCIE form factor (two large, one controller with SERDES) and has a $30K list price that handles up to 30 million gates. Multiple-boards can be added and connected together.


Daughter Cards

Q: What’s different about the Polaris approach?
A: We support the richest set of daughter cards: Multimedia LCD touchpad, 5.2 Megapixel camera, Dual ASI/SD-SDI transmitter/receiver (HAPS will charge you for daughter cards $$), extendible eco-system, (Altera created the HSMC standard, hundreds of choices). Altera software is also much more stable than Xilinx software (synthesis, P&R).

Q: How difficult is it when Altera upgrades their FPGA products and you have to update your prototyping products?
A: Well, with Altera on the Stratix III to IV the pinouts stayed the same, making our prototype boards quite easy to migrate.

Q: How big is your company?
A: We are a small, private firm, and our FPGA prototyping experience goes back to 2006. We are located in CA.

Summary
You do have choices when it comes to verifying your SOC designs, and FPGA-based prototyping is something worth considering to speed up your verification process and find more bugs sooner than later. Polaris looks to have some good ideas in prototyping at an affordable price.

If Mentor wanted to get into this market segment, then Polaris may be a good candidate to acquire.

Read my blog article on the Synopsys prototyping approach.


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