A New IC Power Integrity Tool

A New IC Power Integrity Tool
by Daniel Payne on 11-12-2013 at 7:00 am

In EDA we have come to expect that only small start-up companies create new tools, however a team at Cadencehas developed a new IC power integrity tool called Voltus from scratch. To learn more I spoke last week with KT Moore, a Group Director at Cadence. I’ve known KT for over a decade, and first met him when he was at Magma marketing… Read More


Data Management in Russia

Data Management in Russia
by Paul McLellan on 11-07-2013 at 5:06 pm

Milandr is a company based in Moscow that makes high reliability semiconductor components for the aerospace, automotive and consumer markets, primarily in Russia. They work with multiple foundries, including X-FAB and TSMC in technologies from 1um down to 65nm. Corporate headquarter and main IC design house is located in Russian… Read More


nVidia: Virtual Platform/Emulation Hybrid

nVidia: Virtual Platform/Emulation Hybrid
by Paul McLellan on 11-05-2013 at 11:57 am

I was the VP marketing at VaST Systems Technology and then at Virtutech. Both companies sold virtual platform technology which consisted of two parts:

  • an extremely fast processor emulation technology that actually worked by doing a binary translation of the target binary code (e.g. an ARM) into the native instruction set of the
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ARM in Samsung 14nm FinFET

ARM in Samsung 14nm FinFET
by Paul McLellan on 10-30-2013 at 4:28 pm

I am at ARM TechCon today. One interesting presentation was made jointly between Samsung, Cadence and ARM themselves about developing physical libraries (ARM), a tool flow (Cadence) and test chips (Samsung). It was titled Samsung ARM and Cadence collaborate on the silicon-proven world first 14-nm FinFET Cortex-A7 ARM CPU and… Read More


MEMS in The World of ICs – How to Quickly Verify?

MEMS in The World of ICs – How to Quickly Verify?
by Pawan Fangaria on 10-29-2013 at 10:00 am

In the modern electronic world, it’s difficult to imagine any system working as a whole without MEMS (Micro-electromechanical Systems) such as pressure sensors, accelerometers, gyroscopes, microphones etc. working in sync with other ICs. Specifically in AMS (Analog Mixed-Signal) semiconductor designs, there can be significant… Read More


Cadence’s Mixed-Signal Technology Summit

Cadence’s Mixed-Signal Technology Summit
by Randy Smith on 10-28-2013 at 1:45 am

On October 10, I attended another Cadence Summit, this one titled the Cadence Mixed-Signal Technology Summit. Recently, I had written about the Cadence Silicon Verification Summit. The verification event was the first of its kind, and I thought it had terrific content. Being more of a digital guy myself, I was unaware that Cadence… Read More


Server Shift to ARM Becomes a Stampede

Server Shift to ARM Becomes a Stampede
by Paul McLellan on 10-19-2013 at 3:00 pm

I have been at the Linley Microprocessor Conference today. This is the one that is not about mobile: about servers, networking, base-stations. Probably the most important story about the whole industry is that the “shift to ARM becomes a stampede.”


In this market it seems to be driven by the 64-bit ARMv8 instruction… Read More


Putting the Ten in Tensilica

Putting the Ten in Tensilica
by Paul McLellan on 10-17-2013 at 3:55 pm

Chris Rowen of Cadence’s Tensilica announced the tenth generation of the Xtensa customizable processor at the Linley Microprocessor Conference yesterday. Chris was one of the founders of Tensilica…back in 1997. I believe that the first version was released in 1999. Over the years the Tensilica business changed.… Read More


GSA hosting “Interface IP: Winners, Losers in 2013” from IPnest

GSA hosting “Interface IP: Winners, Losers in 2013” from IPnest
by Eric Esteve on 10-17-2013 at 5:32 am

The GSA IP Working Group will meet today in San Jose, and the Group has asked IPnest building a presentation dedicated to Interface IP. The timing was perfect, as I have just completed the “Interface IP Survey” version 5, and I was able to use fresh market data. The IP working group will discover the IP vendor ranking, protocol by protocol,… Read More


Spectre from Cadence Goes FastSPICE

Spectre from Cadence Goes FastSPICE
by Daniel Payne on 10-09-2013 at 2:31 am

Transistor-level circuit designers have an insatiable appetite to run numerous SPICE circuit simulations in order to determine circuit speed, current and power across Process, Voltage and Temperature (PVT) conditions. Just look at the number of PVT corners increasing as the technology nodes go to 16nm:

The good news today … Read More