You probably remember Cadence introduced Voltus towards the end of last year at their signoff summit. This was aimed at digital designers. Prior to that they had announced Tempus, their static timing analysis tool. More recently they announced Quantus QRC extraction. All of these tools that end in -us have been re-architected… Read More
Tag: cadence
A Deeper Insight into Quantus QRC Extraction Solution
Last month Cadenceannounced its fastest parasitic extraction tool (minimum 5 times better performance compared to other available tools) which can handle growing design sizes with interconnect explosion, number of parasitics and complexities at advanced process nodes including FinFETs, without impacting accuracy of … Read More
Cadence Results: Good but Palladium under Price Pressure
Cadence announced their 2Q results this afternoon. I listened to the conference call.
You can read all the details of the results in the press release but the big picture is:
- Revenue $379K, net income $23M GAAP or $64M non-GAAP (8, 21c per share, beat estimates by 1c). Equivalent quarter last year was $362M so less than 5% increase)
Palladium’s Little Brother Protium
Today, Cadence announced Protium, a new FPGA prototyping platform for software development. During development of an SoC, the most appropriate methodology changes. In the early days, developing RTL, the primary tool is simulation. Then, as the blocks get bigger or as the whole chip starts to come together, typically simulation… Read More
Cadence Announces Quantus Next Generation Extraction
Today Cadence announced their next generation extraction solution called Quantus QRC. Actually they are technically announcing it tomorrow, since it is being announced at CDNLive in Korea where it is already Tuesday morning.
As with the other recently announced tools that end in -us, Tempus (timing signoff) and Voltus (power… Read More
So Easy To Learn VIP Integration into UVM Environment
It goes without saying that VIPs really play a Very Important Part in SoC verification today. It has created a significant semiconductor market segment in the fabless world of SoC and IP design & verification. In order to meet the aggressive time-to-market for IPs and SoCs, it’s imperative that readymade VIPs which are proven… Read More
What’s New with Circuit Simulation for Cadence?
Every year at DAC I enjoy making the rounds to see what’s new with SPICE circuit simulators, so on June 3rd I met with Xiuya Liand Dan Zhuof Cadence in San Francisco to get an update about their Spectre tool. There’s plenty of competition in the SPICE area from Mentor Graphics (Analog FastSPICE, Eldo, ADiT), Synopsys … Read More
Intel Invests in the Fabless Ecosystem!
During my illustrious career one of the most useful axioms that I use just about everyday day is: “Understand what people say but also understand why they are saying it.” This certainly applies to press releases so let’s take a look at what Intel unleashed during #51DAC (in alphabetical order):
ANSYS And Intel Collaborate… Read More
Product Marketing & the Butterfly Effect
I often feel that product marketing can simultaneously be an underrated and overrated function. More often than not, it suggests product goals, pricing, and positioning. Then the marketing department must defend those positions to both engineering and sales. However, both the engineering and sales departments can claim expertise… Read More
Embedded Vision Summit
I was a the embedded vision conference last week. Jeff Beir, the founder of the embedded vision alliance gave an introduction to the field. The conference was much bigger than previous years and almost everyone is designing some sort of vision product. Half of your brain is used for vision so it goes without saying that vision requires… Read More