One of the questions I routinely ask amongst the fabless semiconductor ecosystem is, “How are the EDA vendors doing?” There are always complaints because, let’s face it, we all like to complain. On occasion however I do hear about a vendor who goes above and beyond the call of duty and it really brightens my day.
Of late, the highest praise has gone to Cadence. I was working in Silicon Valley in the early 1980s when EDA began to flourish. It was mostly DMV (Daisy, Mentor, Valid) when two smaller start-ups merged (ECAD and SDA) in 1988 to create Cadence. I credit Joe Costello with making EDA an exciting place to work. Unfortunately, after Joe left in 1997 Cadence seemed to lose its way. In January 2009 Lip-Bu Tan joined Cadence as President and CEO after serving on the Cadence Board of Directors for five years. To me that was a turning point for Cadence which brought them back to what they are today, an industry leader. Cadence stock agrees as it has more than tripled since Lip-Bu took over as President and CEO.
20nm was a defining node as it required much closer collaboration amongst the fabless semiconductor ecosystem. Double patterning is one example but there are plenty of others. At 16nm we have FinFETs and even more challenges ahead especially for analog and mixed signal design and as we all know Cadence is the AMS design market leader. 10nm is well underway and Cadence is a key player in the development of IP and PDKs to which TSMC acknowledged during their Open Innovation Platform Forum:
“We presented the awards to Cadence based on the quality results delivered through its Soft IP and 16FF+ solutions,” said Suk Lee, TSMC senior director, Design Infrastructure Marketing Division. “Cadence has demonstrated its commitment to working closely with us to bring the highest quality design capabilities to IC designers around the world, and we look forward to continuing our partnership in the years to come.”
Dr. Chi-Ping Hsu, senior vice president, chief strategy officer, EDA, and chief of staff to the CEO at Cadence, commented on the awards, saying, “The award recognition from TSMC reflects our long-standing relationship and further demonstrates our ongoing commitment to delivering a strong IP portfolio and advanced-node technology for next-generation SoC designs.”
Dr. Hsu from Cadence further commented, “Customers that create chips for the world’s newest mobile devices are already tapping into the benefits of the 16FF+ design flows and can start to adopt 10nm FinFET solutions to overcome design complexity and get to market faster.”
This did not come as a surprise to me because of the many EDA people I see in Hsinchu. One of the more critical components of collaboration is the willingness to “show up” and during my travels I most often see Cadence executives. Contrary to unpopular belief, there is no such thing as tossing semiconductor designs over the wall to manufacturing so if you want to know who the key players are in modern semiconductor design and manufacturing spend time at the Hotel Royal, The Sheraton, and the Ambassador Hotel in Hsinchu. Or just hang out in the lobby of TSMC Fab 12.
And yes I know Synopsys and other partners were recognized by TSMC, and rightly so, but I give the SemiWiki award for Most Improved EDA Vendor to Cadence, hands down. Ha ha, you thought I was going to say “absolutely” didn’t you?Share this post via: