WP_Term Object
(
    [term_id] => 15
    [name] => Cadence
    [slug] => cadence
    [term_group] => 0
    [term_taxonomy_id] => 15
    [taxonomy] => category
    [description] => 
    [parent] => 157
    [count] => 461
    [filter] => raw
    [cat_ID] => 15
    [category_count] => 461
    [category_description] => 
    [cat_name] => Cadence
    [category_nicename] => cadence
    [category_parent] => 157
)
            
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WP_Term Object
(
    [term_id] => 15
    [name] => Cadence
    [slug] => cadence
    [term_group] => 0
    [term_taxonomy_id] => 15
    [taxonomy] => category
    [description] => 
    [parent] => 157
    [count] => 461
    [filter] => raw
    [cat_ID] => 15
    [category_count] => 461
    [category_description] => 
    [cat_name] => Cadence
    [category_nicename] => cadence
    [category_parent] => 157
)

Cadence Mixed Signal Technology Forum

Cadence Mixed Signal Technology Forum
by Paul McLellan on 10-29-2014 at 7:00 am

 Yesterday was Cadence’s annual mixed-signal technology forum. I think that there was a definite theme running through many of the presentations, namely that wireless communication of one kind or another is on a sharp rise with more and more devices needing to connect to WiFi, Bluetooth and so on. This was most obvious during the panel session after lunch which was on the ecosystem needed for the internet of things. However, the way to design radios (and analog interfaces in general) is increasingly to design the smallest possible analog blocks and then use digital, even quite complex digital, to calibrate the analog.David Su of Qualcomm gave the opening keynote on Designing WLAN SoCs. He started with a history of wireless LANs, pointing out the huge increase of 3 orders of magnitude increase in data rates. The effect of this has been that data cost has been declining about 2X per year even though the cost of a wireless router has been roughly static. We went from 1MHz to 160MHz channels and now with future standards allowing 4 or 8 channels to be used.He is a big fan of minimizing the analog and using digital to calibrate, what he (and Cadence) calls digital assisted analog design. Of course there are still big challenges. The biggest problem, beyond simply power, is digital interference with the analog on the SoC. There are various strategies for coping with this, minimizing the aggressor (the digital logic) by techniques like clock gating and minimizing switching large registers on one clock cycle. Next, strengthen the victim (analog) by wells and robust analog design. And then try and minimize the coupling by spacing the blocks apart and even potentially some process tricks such as deep wells.Ken Kundert (who used to work at Cadence and was the principal author of Spectre) made a plea that the way that analog engineers designed needed to modernize or designing these kind of digitally trimmed analog is almost impossible. If designs are to be done in a reasonable time then the digital and analog need to be designed in parallel and the most promising way to do that is to start from a spec of the analog block and use that to produce a model and a self-checking testbench. This isn’t as hard as it seems. Digital design has huge state so verification is hard, but synthesis, place & route makes implementation fairly straighforward. Analog is the other way around, specifications are simple, there is little state, but implementation is hard. Hence the need to use models since the schematic comes too late and simulates too slowly for the digital design team. Wilbur Luo of Cadence gave an overview of the mixed signal offering. Increasingly the methodology revolves around having Virtuoso and Encounter Digital Implementation (EDI) running on a common open access database able to share the same semantics without losing things like constraints in implementation. There are even lower capacity versions of Encounter, Tempus, Voltus etc which run inside Virtuoso to enable digital design.After lunch there was a panel with Rob Consaro of Freeescale, Ron Moore of ARM, Ian Dennison from Cadence Scotland and Doug Patulio from TSMC. Rob related a tale of how the tools and methodologies now mean that power methodology is now a solved problem compared to a few years ago when he tried and failed to design a chip with lots of power domains in the days before CPF/UPF. But noise is the big challenge going forward. Ron said in some cases ARM is going back to a single power domain to keep the area down which makes it a challenge to handle leakage.Doug pointed out that TSMC has always been in the business of helping customers get to the next node. But he feels that 28nm is the last time that will happen. Some people will move to 16FF+ of course. But TSMC is putting a lot of effort into re-engineering older processes using what they have learned from the advanced processes, especially for ultra-low power aimed specifically at IoT. Ian talked about putting sensors and analog and digital all on the same die, perhaps using TSVs or other 3D technologies. There is a mismatch at present as to which process sensors and other MEMS devices need for fabrication, with which digital technologies make most sense. One question from the audience asked about software: how do we get analog models running on emulators so that we can use virtual platform technology to do early software development? There is some possibility that using real-number models will help but there was no clear answer.Oh, and I won a copy of the Mixed-signal Methodology Guide.
More articles by Paul McLellan…


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