IEDM 2016 – Marie Semeria LETI Interview

IEDM 2016 – Marie Semeria LETI Interview
by Scotten Jones on 12-21-2016 at 7:00 am

Marie Semeria is the CEO of Leti, one of the world’s premier research organization for semiconductor technology and the key development center for FDSOI. I first interviewed Marie at SEMICON West and at IEDM I had a chance to sit down with her and get an update on Leti’s efforts over the last several months.

My interview… Read More


Advanced Semiconductor Process Cost Trends

Advanced Semiconductor Process Cost Trends
by Scotten Jones on 12-13-2016 at 4:00 pm

The cost trend for leading edge semiconductor technologies is a subject of some controversy in the industry. Cost is a complex issue with many interacting factors and much of the information out in the industry is in my opinion misleading or incorrect. In this article, I will discuss each of the factors as well as present a view of … Read More


The post election Semicap bubble just burst in one day

The post election Semicap bubble just burst in one day
by Robert Maire on 12-04-2016 at 12:00 pm

Back to a more normal reality… Market gets”De-Fanged”… Where to from here? The “Icarus” Effect… Much of the market, and especially Tech & “FANG” (Facebook, Amazon, Netflix & Google) stocks gave back most all of their post election day gains in one session.Read More


Soitec – Enabling the FDSOI Revolution

Soitec – Enabling the FDSOI Revolution
by Scotten Jones on 10-18-2016 at 12:00 pm

Recently I published two blogs on Fully Depleted Silicon On Insulator (FDSOI) and the potential the technology shows for a variety of low power and wireless applications. In order to produce FDSOI devices, the device layer has to be thin enough to ensure the device is fully depleted and ideally the buried oxide has to be thin enough… Read More


The 2016 Leading Edge Semiconductor Landscape

The 2016 Leading Edge Semiconductor Landscape
by Scotten Jones on 09-03-2016 at 7:00 am

The leading edge semiconductor logic landscape has in recent years collapsed to just four companies. The following is a summary of what is currently known about each company’s plans and how they compare. ASML has analyzed many logic nodes and developed a formula that normalizes processes to a “standard node”.… Read More


SEMICON West – Harry Levinson and Mike Lercel Interview

SEMICON West – Harry Levinson and Mike Lercel Interview
by Scotten Jones on 08-02-2016 at 12:00 pm

On Tuesday morning at SEMICON I had the opportunity to sit down with Harry Levinson, Sr. Director of Technology Research and Sr. Fellow at Global Foundries and Michael Lercel, Director of Strategic Marketing at ASML to discuss the state of lithography.

I opened the discussion with a question about how we are going to address lithography… Read More


SEMICON West – Leti FDSOI and IOT, status and roadmap

SEMICON West – Leti FDSOI and IOT, status and roadmap
by Scotten Jones on 07-28-2016 at 7:00 am

On Tuesday, July 12th at SEMICON West I had an opportunity to sit down with Marie Semeria, the CEO of Leti and discuss the status and future of FDSOI. Leti pioneered FDSOI 15 years ago and has been the leading FDSOI research ever since.

Two years ago Leti and ST Micro demonstrated products on 28nm that are cost competitive with bulk technology.… Read More


IMEC Technology Forum at SEMICON – Coventor could save you billions!

IMEC Technology Forum at SEMICON – Coventor could save you billions!
by Scotten Jones on 07-22-2016 at 7:00 am

The development of leading edge semiconductor technology is incredibly expensive, with estimates ranging from a few to several billion dollars for new nodes. The time to develop a leading edge process is also a critical competitive issue with some of the largest opportunities awarded based on who is first to yield on a new node.… Read More


IMEC-Horizontal Nanowires for 5nm at the VLSI Technology Symposium

IMEC-Horizontal Nanowires for 5nm at the VLSI Technology Symposium
by Scotten Jones on 07-21-2016 at 12:00 pm

At the VLSI Technology Symposium, IMEC presented a paper entitled “Gate-All-Around MOSFETs based on Vertically Stacked Horizontal Si Nanowires in a Replacement Metal Gate Process on Bulk Silicon Wafers”. I have wanted to blog about this paper since the symposium was held but also wanted to tie it in with an interview… Read More