In the first session of IEDM on Monday, December 5th there were two papers presented on 7nm processes. The first paper was from TSMC and the second paper was from the Global Alliance of GLOBALFOUNDRIES, IBM and Samsung.
TSMC 7nm paper
The TSMC process includes 5th generation high-k metal gate (HKMG), 4th generation FinFETs, dual gate oxides and dual raised source/drains. The metal stack is 12 layers of copper with M0 to M4 pitches at a 1.0x minimum metal pitch of 40nm (MMP), M5 to M9 at a 1.6x minimum pitch, M10 at 3.1x minimum pitch and M11 and M12 at 13x the minimum pitch. In the paper, it is also noted that single patterning is used for metal layers with a pitch of 2x and above. This means that multi-patterning is used for the first 9 metal layers!
The resulting performance compared to TSMC’s 16nm process provides >3.3X routed gate density and a 35% to 40% speed gain or >65% power reduction. Four threshold voltages were shown with a spread of 200mV. An SRAM cell size of 0.027µm[SUP]2[/SUP] is achieved and a 256Mb SRAM has been demonstrated down to 0.5 volts.
TSMC also reported that they compared EUV to multi-patterning for metal and vias and achieve comparable SRAM yields. In answer to a question from the crowd, the presenter said that EUV was a test vehicle. This is consistent with TSMC’s public statements that they won’t implement EUV until 5nm.
I did not hear a value for the contacted poly pitch presented and I don’t see it in the paper. Following the conference there have been some reports that a 54nm CPP was disclosed, I didn’t see that presented but it is consistent with what I have recently heard. The interesting thing to me about that is that TSMC has said on their quarterly investor calls that the density at 7nm is 1.63x the density of their 10nm process. Based on my understating of CPP and MMP at 10nm this is only a 1.3x improvement, however I have heard that they are also offering 6 track cells for the 7nm process whereas at 10nm – 7.5 track cells were the most compact cells available, including a 7.5 track to 6 track cell shrink results in a 1.63x density improvement exactly as reported. The 54nm CPP and 40nm MMP for this process are the same CPP and MMP numbers I have heard for Intel’s 10nm process. Limiting the MMP to 40nm allows TSMC and Intel to use Self Aligned Double Patterning (SADP) for metal layers yielding a lower cost versus a smaller metal pitch that would require Self Aligned Quadruple Patterning (SAQP).
Alliance 7nm paper (GLOBALFOUNDRIES, IBM, Samsung)
The presenter for this paper was from IBM and the work shown here was done at Albany Nanotech. Since IBM has transferred all their semiconductor production assets to GLOBALFOUNDRIES the only possible production of this process would be at GLOBALFOUNDRIES or Samsung. One question I have after seeing this paper was how representative is it of the 7nm processes that GLOBALFOUNDRIES and Samsung are both developing for their own production use. During an interview I had with GLOBALFOUNDRIES at IEDM I asked that question and they wouldn’t comment. My guess is pieces of this development may be adapted by GLOBALFOUNDRIES or Samsung but probably not the entire process. The process experts I talked to at IEDM were particularly skeptical that the SiGe channel PMOS with SRB (described below) would be implemented for leakage reasons, although Samsung also presented a paper on the same technique for 5nm so they are clearly looking at it.
The process begins with a stress relaxed buffer (SRB) of silicon germanium (SiGe) with a germanium content of ~25% deposited on the silicon wafer. Super steep retrograde wells are then formed followed by silicon (Si) and SiGe channel formation. Deposited Si on SiGe results in tensile stress in the Si. It is very difficult to introduce tensile stress in Si channels for FinFETs, raised silicon carbon (SiC) source/drains are one route but incorporating sufficient C has been problematic to date. The Si on SRB technique offers a new method for incorporating high levels of tensile strain. Deposited SiGe on SiGe can result in compressive strain for the deposited SiGe if the Ge concentration in the deposited channel is higher than the Ge concentration in the SRB. The deposited SiGe – Ge concentration is ~50%. The resulting stress for both channels is ~1.6GPa, tensile for NFETs and compressive for PFETs. The formation of the channels by selective epitaxial deposition is followed dummy gate deposition (this is a replacement metal gate process flow). Spacers and raised source/drains are then formed followed by interlayer dielectric deposition. The dummy gate is then removed and the work function metals are deposited. Finally self-aligned contacts and interconnects are formed. The contacts and local interconnect are formed using dual damascene cobalt providing a 50% resistance reduction versus tungsten. The BEOL interconnects are dual damascene copper.
The CPP is 44/48nm and the MMP is 36nm. Fin structures were produced using SAQP, gate by SADP and then EUV was used for Middle Of Line (MOL) and lower Back End Of Line (BEOL) layers. The SRAM cell size was not disclosed directly but during an audience question the presenter said the SRAM cell size was exactly one half the size disclosed previously for 10nm. The disclosed 10nm SRAM cell size is 0.053µm[SUP]2[/SUP] and one half is 0.027µm[SUP]2[/SUP].
The TSMC process is likely their actual production process whereas the Alliance paper is less certain to be implemented in production. Assuming the TSMC process is a shrink of their previous FinFET processes without any major new enhancement techniques, then the Alliance process flow is more complex and higher cost than the TSMC process flow. The pitches are tighter for the Alliance process flow with CPP x MMP of 1,584nm[SUP]2[/SUP]for the high-density cells versus 2,160nm[SUP]2[/SUP] for TSMC but then the question becomes what is available for cells. If the Alliance process only has 7.5 track cells, then the 6 track TSMC cell will be 9% larger than the Alliance cell (or the same size as a 48 x 36 Alliance cell). If the Alliance process supports 6 track cells then the density advantage is 36% for a 44 x 36 Alliance cell. The fact that the two processes result in identical SRAM cell sizes suggests that practically speaking there isn’t a lot of density difference between them especially when a high percentage of most SOC designs is SRAM.
The TSMC 7nm process is due to enter risk production late next year giving TSMC the lead in foundry process density. GLOBALFOUNDRIES is developing an optically patterned 7nm process due in the first half of 2018 and assuming GLOBALFOUDRIES adopts the Alliance pitches they would then take the foundry process density lead. Samsung is developing an EUV patterned 7nm process due in late 2018. Assuming ASML can hit their EUV productivity targets and Samsung can ship in late 2018, they would then match GLOBALFOUNDRIES for process density while likely achieving lower cost. I should also note that GLOBALFOUNDRIES has said their 7nm process will be optical based but also be EUV compatible and they can implement a second generation 7nm version on EUV when it is available.
At IEDM TSMC and the Alliance presented two different approaches to 7nm. TSMC took a more incremental approach while the Alliance process is more aggressive with a lot of new technology. The Alliance process is higher complexity and cost but potentially higher density. Over the next two years it will be interesting to see what enters production for 7nm technologies and how the processes compare for real world designs.
Also read:Advanced Semiconductor Process Cost Trends