Day 1 of the SPIE conference featured a number of customer updates on the status of their EUV programs. On Tuesday morning we got to hear ASML’s update on their work.… Read More
Today is the first day of the SPIE Advanced Lithography Conference and Extreme Ultraviolet (EUV) updates were a big focus.… Read More
For any invention, technical proof of concept or prototyping happens years ahead of the invention being infused into actual products. When we talk about 5nm chip manufacturing, a test chip was already prototyped in last October, thanks to Cadence and Imec. Details about this chip can be found in a blog at Semiwiki (link is given … Read More
Recently imec and Cadence disclosed that they had fabricated 5nm test chips. This afternoon Dan Nenni and I had a conference call with Praveen Raghavan, principal engineer at imec, and Vassilios Gerousis, distinguished engineer at Cadence to get more details on what the test chip is and what was learned.
First off Vassilios really… Read More
We live in very interesting times, you can wear an Android watch from Samsung that uses 14 nm FinFET technology, attend the 52nd DAC conference in June to learn about EDA and IP vendors supporting FinFET, and read about research work for new devices down to 5 nm. TCAD is that critical software technology that enables the development… Read More
Yesterday I attended the IMEC Technology Forum at Semicon West. As always with IMEC, they present so much information it is like drinking from a firehose. I’ll say more about the future of process technology in a blog later this week, but this blog is about IMEC itself. It is an amazing success story. Let’s face it, if you were going … Read More