TSMC and Solido on Variation-Aware Design of Memory and Standard Cell at Advanced Process Nodes

TSMC and Solido on Variation-Aware Design of Memory and Standard Cell at Advanced Process Nodes
by Daniel Nenni on 05-10-2016 at 12:00 pm

Being that TSMC and Solido are founding members of SemiWiki, you should be able find out everything you ever wanted to know on their respective landing pages. If not, just ask a question in the SemiWiki forum and I can assure you it will be answered in great detail. And here are some other interesting 2015 factoids from Solido:… Read More


EUV is coming but will we need it?

EUV is coming but will we need it?
by Scotten Jones on 04-12-2016 at 4:00 pm

I have written multiple articles about this year’s SPIE Advanced Lithography Conference describing all of the progress EUV has made in the last year. Source power is improving, photoresists are getting faster, prototype pellicles are in testing, multiple sites around the world are exposing wafers by the thousands and more. Read More


10nm SRAM Projections – Who will lead

10nm SRAM Projections – Who will lead
by Scotten Jones on 03-25-2016 at 12:00 pm

At ISSCC this year Samsung published a paper entitled “A 10nm FinFET 128Mb SRAM with Assist Adjustment System for Power, Performance, and Area Optimization. In the paper Samsung disclosed a high density 6T SRAM cell size of 0.040µm[SUP]2[/SUP]. I thought it would be interesting to take a look at how this cell size stacks … Read More


How 16nm and 14nm FinFETs Require New SPICE Simulators

How 16nm and 14nm FinFETs Require New SPICE Simulators
by Daniel Payne on 02-07-2016 at 7:00 am

About 35 years ago the first commercial SPICE circuit simulators emerged and they were quickly put to work helping circuit designers predict the timing and power of 6um NMOS designs. Then we had to limit our circuit simulations to just hundreds of transistors and interconnect elements to fit into the RAM and complete simulation… Read More


FinFET will finally arrive for GPU’s in 2016

FinFET will finally arrive for GPU’s in 2016
by Tom Simon on 01-13-2016 at 12:00 pm

It used to be that GPU chips moved to new process nodes pretty frequently, previously as often as annually. That is up until 2011. That was the year that 28nm GPU’s were unveiled. Since then there has been a long pause. Now in the wake of the 2016 CES both Nvidia, with its previously announced Pascal, and AMD, with the just announced Polaris,… Read More


Xilinx Skips 10nm

Xilinx Skips 10nm
by Paul McLellan on 09-28-2015 at 7:00 am

At TSMC’s OIP Symposium recently, Xilinx announced that they would not be building products at the 10nm node. I say “announced” since I was hearing it for the first time, but maybe I just missed it before. Xilinx would go straight from the 16FF+ arrays that they have announced but not started shipping, and to the… Read More


SEMI SMC: Atoms Still Don’t Scale

SEMI SMC: Atoms Still Don’t Scale
by Paul McLellan on 09-24-2015 at 7:00 am

Last Tuesday was the SEMI’s annual Strategic Materials Conference (SMC). The opening keynotes were given by Gary Patton, the CTO of GlobalFoundries, and Mark Thirsk, Managing Partner of Linx Consulting. This year it was held in the Computer History Museum (which always makes the commute interesting since you have to fight… Read More


TSMC OIP: What to Do With 20,000 Wafers Per Day

TSMC OIP: What to Do With 20,000 Wafers Per Day
by Paul McLellan on 09-17-2015 at 4:42 pm

Today it is TSMC’s OIP Ecosystem Innovation forum. This is an annual event but is also a semi-annual update on TSMC’s processes, investment, volume ramps and more. TSMC have changed the rules for the conference this year: they have published all the presentations by their partners/customers. Tom Quan of TSMC told… Read More


Tackling Layout Gradient Effects in 16 nm FinFET using Layout Automation

Tackling Layout Gradient Effects in 16 nm FinFET using Layout Automation
by Daniel Payne on 07-10-2015 at 12:00 pm

My first exposure to automating IC layout was back in the 1980’s at Intel where I coded a layout compiler to auto-generate about 6% of a graphics processor chip. The need to use automation for IC layout continues today, and with the advent of FinFET technology there are some new challenges like layout gradient effects that … Read More