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Electrostatic Discharge analysis of FinFET technology

Electrostatic Discharge analysis of FinFET technology
by bkeppens on 06-05-2016 at 12:00 pm

Sofics recently had the opportunity to characterize FinFET technology through cooperation with one of its customers. We analyzed the technology related to ESD and identified several challenges.

Advanced circuits fail easily during ESD stress

The maximum allowed voltage on core circuits continues to drop.

Traditional ESD solutions run out of steam
In mature and mainstream technology nodes ESD protection is rather straightforward. Several options exist for core and local protection.

We analyzed the NMOS and PMOS devices in both core and IO voltage domains and also so-called BIGfet circuits or rail clamps and diodes

Increased design complexity
There is a significant increase in the number of design rules in FinFET technology. Several EDA vendors already pointed out that verifying FinFET-based circuits requires a computer system with several CPU-cores and a lot of DRAM memory. We also noticed a strong increase in ESD design complexity.

More information?
Contact us (16nmreport@sofics.com) if you want more information.


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